From 3119c54632b7b75552222c5745b743fd12ec880c Mon Sep 17 00:00:00 2001 From: Artemis Tosini Date: Sun, 4 Feb 2024 02:38:44 +0000 Subject: [PATCH] old zephyr sam3s port template --- flake.lock | 14 +- flake.nix | 10 +- rp2040/shell.nix | 2 +- zephyr/blink/CMakeLists.txt | 3 + zephyr/ports/asf/Atmel.SAM3S_DFP.pdsc | 2417 + zephyr/ports/asf/package.content | 667 + .../Device/SAM3S/Source/ARM/startup_SAM3S.s | 269 + .../armcc/Device/SAM3S/Source/system_SAM3S.c | 569 + zephyr/ports/asf/sam3s/atdf/ATSAM3S1A.atdf | 7079 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S1B.atdf | 7684 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S1C.atdf | 7879 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S2A.atdf | 7083 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S2B.atdf | 7688 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S2C.atdf | 7883 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S4A.atdf | 7091 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S4B.atdf | 7696 ++ zephyr/ports/asf/sam3s/atdf/ATSAM3S4C.atdf | 7891 ++ .../ports/asf/sam3s/gcc/gcc/sam3s1a_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s1a_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s1b_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s1b_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s1c_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s1c_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s2a_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s2a_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s2b_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s2b_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s2c_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s2c_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s4a_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s4a_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s4b_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s4b_sram.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s4c_flash.ld | 51 + .../ports/asf/sam3s/gcc/gcc/sam3s4c_sram.ld | 51 + zephyr/ports/asf/sam3s/gcc/gcc/sam3s_flash.ld | 139 + zephyr/ports/asf/sam3s/gcc/gcc/sam3s_sram.ld | 139 + .../ports/asf/sam3s/gcc/gcc/startup_sam3s.c | 237 + zephyr/ports/asf/sam3s/gcc/system_sam3s.c | 235 + .../asf/sam3s/include/component-version.h | 72 + .../ports/asf/sam3s/include/component/acc.h | 127 + .../ports/asf/sam3s/include/component/adc.h | 452 + .../asf/sam3s/include/component/chipid.h | 154 + .../ports/asf/sam3s/include/component/crccu.h | 108 + .../ports/asf/sam3s/include/component/dacc.h | 223 + .../ports/asf/sam3s/include/component/efc.h | 92 + .../ports/asf/sam3s/include/component/gpbr.h | 53 + .../ports/asf/sam3s/include/component/hsmci.h | 391 + .../asf/sam3s/include/component/matrix.h | 188 + .../ports/asf/sam3s/include/component/pdc.h | 98 + .../ports/asf/sam3s/include/component/pio.h | 1571 + .../ports/asf/sam3s/include/component/pmc.h | 377 + .../ports/asf/sam3s/include/component/pwm.h | 547 + .../ports/asf/sam3s/include/component/rstc.h | 73 + .../ports/asf/sam3s/include/component/rtc.h | 173 + .../ports/asf/sam3s/include/component/rtt.h | 69 + .../ports/asf/sam3s/include/component/smc.h | 141 + .../ports/asf/sam3s/include/component/spi.h | 228 + .../ports/asf/sam3s/include/component/ssc.h | 343 + .../ports/asf/sam3s/include/component/supc.h | 286 + zephyr/ports/asf/sam3s/include/component/tc.h | 323 + .../ports/asf/sam3s/include/component/twi.h | 218 + .../ports/asf/sam3s/include/component/uart.h | 187 + .../ports/asf/sam3s/include/component/udp.h | 186 + .../ports/asf/sam3s/include/component/usart.h | 371 + .../ports/asf/sam3s/include/component/wdt.h | 73 + zephyr/ports/asf/sam3s/include/instance/acc.h | 56 + zephyr/ports/asf/sam3s/include/instance/adc.h | 90 + .../ports/asf/sam3s/include/instance/chipid.h | 42 + .../ports/asf/sam3s/include/instance/crccu.h | 68 + .../ports/asf/sam3s/include/instance/dacc.h | 76 + zephyr/ports/asf/sam3s/include/instance/efc.h | 46 + .../ports/asf/sam3s/include/instance/gpbr.h | 40 + .../ports/asf/sam3s/include/instance/hsmci.h | 96 + .../ports/asf/sam3s/include/instance/matrix.h | 60 + .../ports/asf/sam3s/include/instance/pioa.h | 142 + .../ports/asf/sam3s/include/instance/piob.h | 130 + .../ports/asf/sam3s/include/instance/pioc.h | 130 + zephyr/ports/asf/sam3s/include/instance/pmc.h | 90 + zephyr/ports/asf/sam3s/include/instance/pwm.h | 240 + .../ports/asf/sam3s/include/instance/rstc.h | 44 + zephyr/ports/asf/sam3s/include/instance/rtc.h | 62 + zephyr/ports/asf/sam3s/include/instance/rtt.h | 46 + zephyr/ports/asf/sam3s/include/instance/smc.h | 80 + zephyr/ports/asf/sam3s/include/instance/spi.h | 80 + zephyr/ports/asf/sam3s/include/instance/ssc.h | 94 + .../ports/asf/sam3s/include/instance/supc.h | 50 + zephyr/ports/asf/sam3s/include/instance/tc0.h | 120 + zephyr/ports/asf/sam3s/include/instance/tc1.h | 120 + .../ports/asf/sam3s/include/instance/twi0.h | 80 + .../ports/asf/sam3s/include/instance/twi1.h | 80 + .../ports/asf/sam3s/include/instance/uart0.h | 76 + .../ports/asf/sam3s/include/instance/uart1.h | 76 + zephyr/ports/asf/sam3s/include/instance/udp.h | 62 + .../ports/asf/sam3s/include/instance/usart0.h | 94 + .../ports/asf/sam3s/include/instance/usart1.h | 94 + zephyr/ports/asf/sam3s/include/instance/wdt.h | 44 + zephyr/ports/asf/sam3s/include/pio/sam3s1a.h | 234 + zephyr/ports/asf/sam3s/include/pio/sam3s1b.h | 277 + zephyr/ports/asf/sam3s/include/pio/sam3s1c.h | 395 + zephyr/ports/asf/sam3s/include/pio/sam3s2a.h | 234 + zephyr/ports/asf/sam3s/include/pio/sam3s2b.h | 277 + zephyr/ports/asf/sam3s/include/pio/sam3s2c.h | 395 + zephyr/ports/asf/sam3s/include/pio/sam3s4a.h | 234 + zephyr/ports/asf/sam3s/include/pio/sam3s4b.h | 277 + zephyr/ports/asf/sam3s/include/pio/sam3s4c.h | 395 + zephyr/ports/asf/sam3s/include/sam.h | 70 + zephyr/ports/asf/sam3s/include/sam3s.h | 55 + zephyr/ports/asf/sam3s/include/sam3s1a.h | 479 + zephyr/ports/asf/sam3s/include/sam3s1b.h | 496 + zephyr/ports/asf/sam3s/include/sam3s1c.h | 519 + zephyr/ports/asf/sam3s/include/sam3s2a.h | 479 + zephyr/ports/asf/sam3s/include/sam3s2b.h | 496 + zephyr/ports/asf/sam3s/include/sam3s2c.h | 519 + zephyr/ports/asf/sam3s/include/sam3s4a.h | 479 + zephyr/ports/asf/sam3s/include/sam3s4b.h | 496 + zephyr/ports/asf/sam3s/include/sam3s4c.h | 519 + zephyr/ports/asf/sam3s/include/system_sam3s.h | 70 + .../asf/sam3s/keil/Flash/ATSAM3S_128.FLM | Bin 0 -> 13192 bytes .../asf/sam3s/keil/Flash/ATSAM3S_256.FLM | Bin 0 -> 13192 bytes .../ports/asf/sam3s/keil/Flash/ATSAM3S_64.FLM | Bin 0 -> 13188 bytes .../asf/sam3s/keil/Flash/ATSAM3S_GPNVM.FLM | Bin 0 -> 13980 bytes zephyr/ports/asf/sam3s/svd/ATSAM3S1A.svd | 45860 +++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S1B.svd | 49672 +++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S1C.svd | 64309 +++++++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S2A.svd | 45860 +++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S2B.svd | 49672 +++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S2C.svd | 64309 +++++++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S4A.svd | 45860 +++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S4B.svd | 49672 +++++++++++ zephyr/ports/asf/sam3s/svd/ATSAM3S4C.svd | 64309 +++++++++++++++ zephyr/ports/asf/sam3s/templates/library.c | 15 + zephyr/ports/asf/sam3s/templates/library.cpp | 15 + zephyr/ports/asf/sam3s/templates/main.c | 21 + zephyr/ports/asf/sam3s/templates/main.cpp | 21 + .../SAM3SD8/Source/ARM/startup_SAM3SD8.s | 271 + .../Device/SAM3SD8/Source/system_SAM3SD8.c | 570 + zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8B.atdf | 7868 ++ zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8C.atdf | 8074 ++ zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8B.atdf | 7870 ++ zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8C.atdf | 8076 ++ .../asf/sam3sd8/gcc/gcc/sam3s8b_flash.ld | 48 + .../ports/asf/sam3sd8/gcc/gcc/sam3s8b_sram.ld | 48 + .../asf/sam3sd8/gcc/gcc/sam3s8c_flash.ld | 48 + .../ports/asf/sam3sd8/gcc/gcc/sam3s8c_sram.ld | 48 + .../asf/sam3sd8/gcc/gcc/sam3sd8_flash.ld | 128 + .../ports/asf/sam3sd8/gcc/gcc/sam3sd8_sram.ld | 128 + .../asf/sam3sd8/gcc/gcc/sam3sd8b_flash.ld | 48 + .../asf/sam3sd8/gcc/gcc/sam3sd8b_sram.ld | 48 + .../asf/sam3sd8/gcc/gcc/sam3sd8c_flash.ld | 48 + .../asf/sam3sd8/gcc/gcc/sam3sd8c_sram.ld | 48 + .../asf/sam3sd8/gcc/gcc/startup_sam3sd8.c | 232 + zephyr/ports/asf/sam3sd8/gcc/system_sam3sd8.c | 237 + .../asf/sam3sd8/include/component-version.h | 72 + .../ports/asf/sam3sd8/include/component/acc.h | 124 + .../ports/asf/sam3sd8/include/component/adc.h | 509 + .../asf/sam3sd8/include/component/chipid.h | 159 + .../asf/sam3sd8/include/component/crccu.h | 107 + .../asf/sam3sd8/include/component/dacc.h | 210 + .../ports/asf/sam3sd8/include/component/efc.h | 89 + .../asf/sam3sd8/include/component/gpbr.h | 53 + .../asf/sam3sd8/include/component/hsmci.h | 384 + .../asf/sam3sd8/include/component/matrix.h | 188 + .../ports/asf/sam3sd8/include/component/pdc.h | 98 + .../ports/asf/sam3sd8/include/component/pio.h | 1644 + .../ports/asf/sam3sd8/include/component/pmc.h | 393 + .../ports/asf/sam3sd8/include/component/pwm.h | 538 + .../asf/sam3sd8/include/component/rstc.h | 73 + .../ports/asf/sam3sd8/include/component/rtc.h | 219 + .../ports/asf/sam3sd8/include/component/rtt.h | 71 + .../ports/asf/sam3sd8/include/component/smc.h | 139 + .../ports/asf/sam3sd8/include/component/spi.h | 226 + .../ports/asf/sam3sd8/include/component/ssc.h | 337 + .../asf/sam3sd8/include/component/supc.h | 322 + .../ports/asf/sam3sd8/include/component/tc.h | 303 + .../ports/asf/sam3sd8/include/component/twi.h | 217 + .../asf/sam3sd8/include/component/uart.h | 185 + .../ports/asf/sam3sd8/include/component/udp.h | 185 + .../asf/sam3sd8/include/component/usart.h | 362 + .../ports/asf/sam3sd8/include/component/wdt.h | 72 + .../ports/asf/sam3sd8/include/instance/acc.h | 56 + .../ports/asf/sam3sd8/include/instance/adc.h | 92 + .../asf/sam3sd8/include/instance/chipid.h | 42 + .../asf/sam3sd8/include/instance/crccu.h | 68 + .../ports/asf/sam3sd8/include/instance/dacc.h | 76 + .../ports/asf/sam3sd8/include/instance/efc.h | 46 + .../ports/asf/sam3sd8/include/instance/gpbr.h | 40 + .../asf/sam3sd8/include/instance/hsmci.h | 96 + .../asf/sam3sd8/include/instance/matrix.h | 60 + .../ports/asf/sam3sd8/include/instance/pioa.h | 156 + .../ports/asf/sam3sd8/include/instance/piob.h | 144 + .../ports/asf/sam3sd8/include/instance/pioc.h | 144 + .../ports/asf/sam3sd8/include/instance/pmc.h | 90 + .../ports/asf/sam3sd8/include/instance/pwm.h | 238 + .../ports/asf/sam3sd8/include/instance/rstc.h | 44 + .../ports/asf/sam3sd8/include/instance/rtc.h | 62 + .../ports/asf/sam3sd8/include/instance/rtt.h | 46 + .../ports/asf/sam3sd8/include/instance/smc.h | 80 + .../ports/asf/sam3sd8/include/instance/spi.h | 80 + .../ports/asf/sam3sd8/include/instance/ssc.h | 94 + .../ports/asf/sam3sd8/include/instance/supc.h | 50 + .../ports/asf/sam3sd8/include/instance/tc0.h | 120 + .../ports/asf/sam3sd8/include/instance/tc1.h | 120 + .../ports/asf/sam3sd8/include/instance/twi0.h | 80 + .../ports/asf/sam3sd8/include/instance/twi1.h | 80 + .../asf/sam3sd8/include/instance/uart0.h | 76 + .../asf/sam3sd8/include/instance/uart1.h | 76 + .../ports/asf/sam3sd8/include/instance/udp.h | 62 + .../asf/sam3sd8/include/instance/usart0.h | 94 + .../asf/sam3sd8/include/instance/usart1.h | 94 + .../asf/sam3sd8/include/instance/usart2.h | 94 + .../ports/asf/sam3sd8/include/instance/wdt.h | 44 + .../ports/asf/sam3sd8/include/pio/sam3s8b.h | 279 + .../ports/asf/sam3sd8/include/pio/sam3s8c.h | 403 + .../ports/asf/sam3sd8/include/pio/sam3sd8b.h | 279 + .../ports/asf/sam3sd8/include/pio/sam3sd8c.h | 403 + zephyr/ports/asf/sam3sd8/include/sam.h | 60 + zephyr/ports/asf/sam3sd8/include/sam3s8b.h | 496 + zephyr/ports/asf/sam3sd8/include/sam3s8c.h | 527 + zephyr/ports/asf/sam3sd8/include/sam3sd8.h | 45 + zephyr/ports/asf/sam3sd8/include/sam3sd8b.h | 507 + zephyr/ports/asf/sam3sd8/include/sam3sd8c.h | 538 + .../asf/sam3sd8/include/system_sam3sd8.h | 70 + .../asf/sam3sd8/keil/Flash/ATSAM3S_512.FLM | Bin 0 -> 13192 bytes .../asf/sam3sd8/keil/Flash/ATSAM3S_GPNVM.FLM | Bin 0 -> 13980 bytes zephyr/ports/asf/sam3sd8/svd/ATSAM3S8B.svd | 51033 ++++++++++++ zephyr/ports/asf/sam3sd8/svd/ATSAM3S8C.svd | 68019 ++++++++++++++++ zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8B.svd | 51033 ++++++++++++ zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8C.svd | 68019 ++++++++++++++++ zephyr/ports/asf/sam3sd8/templates/library.c | 15 + .../ports/asf/sam3sd8/templates/library.cpp | 15 + zephyr/ports/asf/sam3sd8/templates/main.c | 21 + zephyr/ports/asf/sam3sd8/templates/main.cpp | 21 + zephyr/ports/ports.cmake | 3 + .../soc/arm/atmel_sam/sam3s/CMakeLists.txt | 5 + .../atmel_sam/sam3s/Kconfig.defconfig.series | 32 + .../soc/arm/atmel_sam/sam3s/Kconfig.series | 20 + .../ports/soc/arm/atmel_sam/sam3s/Kconfig.soc | 111 + .../ports/soc/arm/atmel_sam/sam3s/linker.ld | 9 + zephyr/ports/soc/arm/atmel_sam/sam3s/soc.c | 197 + zephyr/ports/soc/arm/atmel_sam/sam3s/soc.h | 69 + 241 files changed, 856395 insertions(+), 10 deletions(-) create mode 100644 zephyr/ports/asf/Atmel.SAM3S_DFP.pdsc create mode 100644 zephyr/ports/asf/package.content create mode 100644 zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/ARM/startup_SAM3S.s create mode 100644 zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/system_SAM3S.c create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S1A.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S1B.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S1C.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S2A.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S2B.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S2C.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S4A.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S4B.atdf create mode 100644 zephyr/ports/asf/sam3s/atdf/ATSAM3S4C.atdf create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s_flash.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/sam3s_sram.ld create mode 100644 zephyr/ports/asf/sam3s/gcc/gcc/startup_sam3s.c create mode 100644 zephyr/ports/asf/sam3s/gcc/system_sam3s.c create mode 100644 zephyr/ports/asf/sam3s/include/component-version.h create mode 100644 zephyr/ports/asf/sam3s/include/component/acc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/adc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/chipid.h create mode 100644 zephyr/ports/asf/sam3s/include/component/crccu.h create mode 100644 zephyr/ports/asf/sam3s/include/component/dacc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/efc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/gpbr.h create mode 100644 zephyr/ports/asf/sam3s/include/component/hsmci.h create mode 100644 zephyr/ports/asf/sam3s/include/component/matrix.h create mode 100644 zephyr/ports/asf/sam3s/include/component/pdc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/pio.h create mode 100644 zephyr/ports/asf/sam3s/include/component/pmc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/pwm.h create mode 100644 zephyr/ports/asf/sam3s/include/component/rstc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/rtc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/rtt.h create mode 100644 zephyr/ports/asf/sam3s/include/component/smc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/spi.h create mode 100644 zephyr/ports/asf/sam3s/include/component/ssc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/supc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/tc.h create mode 100644 zephyr/ports/asf/sam3s/include/component/twi.h create mode 100644 zephyr/ports/asf/sam3s/include/component/uart.h create mode 100644 zephyr/ports/asf/sam3s/include/component/udp.h create mode 100644 zephyr/ports/asf/sam3s/include/component/usart.h create mode 100644 zephyr/ports/asf/sam3s/include/component/wdt.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/acc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/adc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/chipid.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/crccu.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/dacc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/efc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/gpbr.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/hsmci.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/matrix.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/pioa.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/piob.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/pioc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/pmc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/pwm.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/rstc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/rtc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/rtt.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/smc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/spi.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/ssc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/supc.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/tc0.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/tc1.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/twi0.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/twi1.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/uart0.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/uart1.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/udp.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/usart0.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/usart1.h create mode 100644 zephyr/ports/asf/sam3s/include/instance/wdt.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s1a.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s1b.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s1c.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s2a.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s2b.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s2c.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s4a.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s4b.h create mode 100644 zephyr/ports/asf/sam3s/include/pio/sam3s4c.h create mode 100644 zephyr/ports/asf/sam3s/include/sam.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s1a.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s1b.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s1c.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s2a.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s2b.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s2c.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s4a.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s4b.h create mode 100644 zephyr/ports/asf/sam3s/include/sam3s4c.h create mode 100644 zephyr/ports/asf/sam3s/include/system_sam3s.h create mode 100644 zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_128.FLM create mode 100644 zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_256.FLM create mode 100644 zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_64.FLM create mode 100644 zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_GPNVM.FLM create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S1A.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S1B.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S1C.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S2A.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S2B.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S2C.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S4A.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S4B.svd create mode 100644 zephyr/ports/asf/sam3s/svd/ATSAM3S4C.svd create mode 100644 zephyr/ports/asf/sam3s/templates/library.c create mode 100644 zephyr/ports/asf/sam3s/templates/library.cpp create mode 100644 zephyr/ports/asf/sam3s/templates/main.c create mode 100644 zephyr/ports/asf/sam3s/templates/main.cpp create mode 100644 zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/ARM/startup_SAM3SD8.s create mode 100644 zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/system_SAM3SD8.c create mode 100644 zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8B.atdf create mode 100644 zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8C.atdf create mode 100644 zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8B.atdf create mode 100644 zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8C.atdf create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_flash.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_sram.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_flash.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_sram.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_flash.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_sram.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_flash.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_sram.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_flash.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_sram.ld create mode 100644 zephyr/ports/asf/sam3sd8/gcc/gcc/startup_sam3sd8.c create mode 100644 zephyr/ports/asf/sam3sd8/gcc/system_sam3sd8.c create mode 100644 zephyr/ports/asf/sam3sd8/include/component-version.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/acc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/adc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/chipid.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/crccu.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/dacc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/efc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/gpbr.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/hsmci.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/matrix.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/pdc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/pio.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/pmc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/pwm.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/rstc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/rtc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/rtt.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/smc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/spi.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/ssc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/supc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/tc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/twi.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/uart.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/udp.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/usart.h create mode 100644 zephyr/ports/asf/sam3sd8/include/component/wdt.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/acc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/adc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/chipid.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/crccu.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/dacc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/efc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/gpbr.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/hsmci.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/matrix.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/pioa.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/piob.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/pioc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/pmc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/pwm.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/rstc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/rtc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/rtt.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/smc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/spi.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/ssc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/supc.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/tc0.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/tc1.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/twi0.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/twi1.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/uart0.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/uart1.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/udp.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/usart0.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/usart1.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/usart2.h create mode 100644 zephyr/ports/asf/sam3sd8/include/instance/wdt.h create mode 100644 zephyr/ports/asf/sam3sd8/include/pio/sam3s8b.h create mode 100644 zephyr/ports/asf/sam3sd8/include/pio/sam3s8c.h create mode 100644 zephyr/ports/asf/sam3sd8/include/pio/sam3sd8b.h create mode 100644 zephyr/ports/asf/sam3sd8/include/pio/sam3sd8c.h create mode 100644 zephyr/ports/asf/sam3sd8/include/sam.h create mode 100644 zephyr/ports/asf/sam3sd8/include/sam3s8b.h create mode 100644 zephyr/ports/asf/sam3sd8/include/sam3s8c.h create mode 100644 zephyr/ports/asf/sam3sd8/include/sam3sd8.h create mode 100644 zephyr/ports/asf/sam3sd8/include/sam3sd8b.h create mode 100644 zephyr/ports/asf/sam3sd8/include/sam3sd8c.h create mode 100644 zephyr/ports/asf/sam3sd8/include/system_sam3sd8.h create mode 100644 zephyr/ports/asf/sam3sd8/keil/Flash/ATSAM3S_512.FLM create mode 100644 zephyr/ports/asf/sam3sd8/keil/Flash/ATSAM3S_GPNVM.FLM create mode 100644 zephyr/ports/asf/sam3sd8/svd/ATSAM3S8B.svd create mode 100644 zephyr/ports/asf/sam3sd8/svd/ATSAM3S8C.svd create mode 100644 zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8B.svd create mode 100644 zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8C.svd create mode 100644 zephyr/ports/asf/sam3sd8/templates/library.c create mode 100644 zephyr/ports/asf/sam3sd8/templates/library.cpp create mode 100644 zephyr/ports/asf/sam3sd8/templates/main.c create mode 100644 zephyr/ports/asf/sam3sd8/templates/main.cpp create mode 100644 zephyr/ports/ports.cmake create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/CMakeLists.txt create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.defconfig.series create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.series create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.soc create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/linker.ld create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/soc.c create mode 100644 zephyr/ports/soc/arm/atmel_sam/sam3s/soc.h diff --git a/flake.lock b/flake.lock index ff309f5..a3eef03 100644 --- a/flake.lock +++ b/flake.lock @@ -10,11 +10,11 @@ ] }, "locked": { - "lastModified": 1699858083, - "narHash": "sha256-EXmVoYDYszdWlaxRzedQ3Q7ehbqIGfbe9EaHSBD4cgQ=", + "lastModified": 1700363859, + "narHash": "sha256-zT0vd5Vhd9dR3bTJpFCwtiBRkjY0+iYhvXVifIQ7vSo=", "ref": "refs/heads/canon", - "rev": "453af715eebd7102131d2cc6846dd23d49f853ac", - "revCount": 12, + "rev": "6400d73e5f103f15550beb8bfb0315a98121dfef", + "revCount": 13, "type": "git", "url": "https://git.mildlyfunctional.gay/artemist/packages.git" }, @@ -25,11 +25,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1699725108, - "narHash": "sha256-NTiPW4jRC+9puakU4Vi8WpFEirhp92kTOSThuZke+FA=", + "lastModified": 1700786208, + "narHash": "sha256-vP0WI7qNkg3teQJN5xjFcxgnBNiKCbkgw3X9HcAxWJY=", "owner": "nixos", "repo": "nixpkgs", - "rev": "911ad1e67f458b6bcf0278fa85e33bb9924fed7e", + "rev": "8b8c9407844599546393146bfac901290e0ab96b", "type": "github" }, "original": { diff --git a/flake.nix b/flake.nix index 5236b18..d3f5341 100644 --- a/flake.nix +++ b/flake.nix @@ -19,8 +19,14 @@ arm-zephyr-eabi riscv64-zephyr-elf ]; - modules = with artemist-packages.packages.${system}.zephyr.modules; - [ mbedtls hal_rpi_pico cmsis ]; + modules = + with artemist-packages.packages.${system}.zephyr.modules; [ + mbedtls + hal_rpi_pico + hal_atmel + cmsis + ]; + extraPackages = with pkgs; [ pyocd ]; }; formatter = pkgs.nixfmt; }); diff --git a/rp2040/shell.nix b/rp2040/shell.nix index cc46e84..3ce5c98 100644 --- a/rp2040/shell.nix +++ b/rp2040/shell.nix @@ -11,7 +11,7 @@ in mkShell rec { name = "pico-env"; - nativeBuildInputs = [ pkgconfig ]; + nativeBuildInputs = [ pkg-config ]; buildInputs = [ gnumake diff --git a/zephyr/blink/CMakeLists.txt b/zephyr/blink/CMakeLists.txt index be8ebaa..a01b59c 100644 --- a/zephyr/blink/CMakeLists.txt +++ b/zephyr/blink/CMakeLists.txt @@ -1,4 +1,7 @@ cmake_minimum_required(VERSION 3.20.0) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../ports/ports.cmake) + find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(blink) diff --git a/zephyr/ports/asf/Atmel.SAM3S_DFP.pdsc b/zephyr/ports/asf/Atmel.SAM3S_DFP.pdsc new file mode 100644 index 0000000..45da8fe --- /dev/null +++ b/zephyr/ports/asf/Atmel.SAM3S_DFP.pdsc @@ -0,0 +1,2417 @@ + + + Atmel + http://packs.download.atmel.com/ + SAM3S_DFP + Atmel SAM3S Series Device Support + + Fix max speed in ATDF files. + Updated documentation links. + Updated documentation links. + Initial release. + + + Atmel + Device Support + Device Family Package Atmel + SAM3S + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 128KB Flash, USB, 48 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 128KB Flash, USB, 100 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 128KB Flash, USB, 64 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 256KB Flash, USB, 100 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 256KB Flash, USB, 64 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 256KB Flash, USB, 48 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 64KB Flash, USB, 48 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 64KB Flash, USB, 64 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 64KB Flash, USB, 100 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 512KB Flash, USB, 100 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 512KB Flash, 64 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 2 x 256KB dual-bank Flash, USB, 64 pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Cortex-M3 Microcontroller with 2 x 256KB dual-bank Flash, USB, 100 Pins + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S2A + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S2C + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S2B + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S4C + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S4B + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S4A + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S1A + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S1B + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S1C + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S8C + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3S8B + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3SD8B + + + + + + + + + + + + + + + + + + + Headers and startup code for Atmel ATSAM3SD8C + + + + + + + + + + + + + + + + + + + diff --git a/zephyr/ports/asf/package.content b/zephyr/ports/asf/package.content new file mode 100644 index 0000000..8cff7f5 --- /dev/null +++ b/zephyr/ports/asf/package.content @@ -0,0 +1,667 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Fix max speed in ATDF files. + Updated documentation links. + Updated documentation links. + Initial release. + + + diff --git a/zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/ARM/startup_SAM3S.s b/zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/ARM/startup_SAM3S.s new file mode 100644 index 0000000..34d5b4a --- /dev/null +++ b/zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/ARM/startup_SAM3S.s @@ -0,0 +1,269 @@ +;/***************************************************************************** +; * @file: startup_SAM3S.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the Atmel SAM3S Device Series +; * @version: V1.20 +; * @date: 14. December 2015 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2011-213 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; 0: Top of Stack + DCD Reset_Handler ; 1: Reset Handler + DCD NMI_Handler ; 2: NMI Handler + DCD HardFault_Handler ; 3: Hard Fault Handler + DCD MemManage_Handler ; 4: MPU Fault Handler + DCD BusFault_Handler ; 5: Bus Fault Handler + DCD UsageFault_Handler ; 6: Usage Fault Handler + DCD 0 ; 7: Reserved + DCD 0 ; 8: Reserved + DCD 0 ; 9: Reserved + DCD 0 ; 10: Reserved + DCD SVC_Handler ; 11: SVCall Handler + DCD DebugMon_Handler ; 12: Debug Monitor Handler + DCD 0 ; 13: Reserved + DCD PendSV_Handler ; 14: PendSV Handler + DCD SysTick_Handler ; 15: SysTick Handler + + ; External Interrupts + DCD SUPC_IRQHandler ; 0: Supply Controller + DCD RSTC_IRQHandler ; 1: Reset Controller + DCD RTC_IRQHandler ; 2: Real Time Clock + DCD RTT_IRQHandler ; 3: Real Time Timer + DCD WDT_IRQHandler ; 4: Watchdog Timer + DCD PMC_IRQHandler ; 5: Power Management Controller + DCD EEFC_IRQHandler ; 6: Enhanced Embedded Flash Controller + DCD 0 ; 7: Reserved + DCD UART0_IRQHandler ; 8: UART0 + DCD UART1_IRQHandler ; 9: UART1 + DCD 0 ; 10: Reserved + DCD PIOA_IRQHandler ; 11: Parallel I/O Controller A + DCD PIOB_IRQHandler ; 12: Parallel I/O Controller B + DCD PIOC_IRQHandler ; 13: Parallel I/O Controller C + DCD USART0_IRQHandler ; 14: USART 0 + DCD USART1_IRQHandler ; 15: USART 1 + DCD 0 ; 16: Reserved + DCD 0 ; 17: Reserved + DCD HSMCI_IRQHandler ; 18: Multimedia Card Interface + DCD TWI0_IRQHandler ; 19: Two Wire Interface 0 + DCD TWI1_IRQHandler ; 20: Two Wire Interface 1 + DCD SPI_IRQHandler ; 21: Serial Peripheral Interface + DCD SSC_IRQHandler ; 22: Synchronous Serial Controller + DCD TC0_IRQHandler ; 23: Timer/Counter 0 + DCD TC1_IRQHandler ; 24: Timer/Counter 1 + DCD TC2_IRQHandler ; 25: Timer/Counter 2 + DCD TC3_IRQHandler ; 26: Timer/Counter 3 + DCD TC4_IRQHandler ; 27: Timer/Counter 4 + DCD TC5_IRQHandler ; 28: Timer/Counter 5 + DCD ADC_IRQHandler ; 29: Analog-to-Digital Converter + DCD DACC_IRQHandler ; 30: Digital-to-Analog Converter + DCD PWM_IRQHandler ; 31: Pulse Width Modulation + DCD CRCCU_IRQHandler ; 32: CRC Calculation Unit + DCD ACC_IRQHandler ; 33: Analog Comparator + DCD UDP_IRQHandler ; 34: USB Device Port + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT SUPC_IRQHandler [WEAK] + EXPORT RSTC_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTT_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT EEFC_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SMC_IRQHandler [WEAK] + EXPORT PIOA_IRQHandler [WEAK] + EXPORT PIOB_IRQHandler [WEAK] + EXPORT PIOC_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT HSMCI_IRQHandler [WEAK] + EXPORT TWI0_IRQHandler [WEAK] + EXPORT TWI1_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT SSC_IRQHandler [WEAK] + EXPORT TC0_IRQHandler [WEAK] + EXPORT TC1_IRQHandler [WEAK] + EXPORT TC2_IRQHandler [WEAK] + EXPORT TC3_IRQHandler [WEAK] + EXPORT TC4_IRQHandler [WEAK] + EXPORT TC5_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT DACC_IRQHandler [WEAK] + EXPORT PWM_IRQHandler [WEAK] + EXPORT CRCCU_IRQHandler [WEAK] + EXPORT ACC_IRQHandler [WEAK] + EXPORT UDP_IRQHandler [WEAK] + +SUPC_IRQHandler +RSTC_IRQHandler +RTC_IRQHandler +RTT_IRQHandler +WDT_IRQHandler +PMC_IRQHandler +EEFC_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SMC_IRQHandler +PIOA_IRQHandler +PIOB_IRQHandler +PIOC_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +HSMCI_IRQHandler +TWI0_IRQHandler +TWI1_IRQHandler +SPI_IRQHandler +SSC_IRQHandler +TC0_IRQHandler +TC1_IRQHandler +TC2_IRQHandler +TC3_IRQHandler +TC4_IRQHandler +TC5_IRQHandler +ADC_IRQHandler +DACC_IRQHandler +PWM_IRQHandler +CRCCU_IRQHandler +ACC_IRQHandler +UDP_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/system_SAM3S.c b/zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/system_SAM3S.c new file mode 100644 index 0000000..0042d12 --- /dev/null +++ b/zephyr/ports/asf/sam3s/armcc/Device/SAM3S/Source/system_SAM3S.c @@ -0,0 +1,569 @@ +/**************************************************************************//** + * @file system_SAM3S.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Atmel SAM3S Device Series + * @version V1.10 + * @date 16. April 2013 + * + * @note + * Copyright (C) 2011-2013 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Embedded Flash Controllers Configuration ------------- +// +// Embedded Flash Controller (EEFC) +// FWS: Flash Wait State <1-16><#-1> +// FAM: Flash Access Mode +// <0=> 128-bit in read mode (enhance speed) +// <1=> 64-bit in read mode (enhance power consumption) +// +*/ +#define EEFC_SETUP 1 // Reset values: +#define EEFC_FMR_Val 0x00000200 // 0x00000000 + + +/*--------------------- Power Management Controller Configuration ------------ +// +// Power Management Controller (PMC) +// System Clock Enable Register (PMC_SCER) +// UDP: USB Device Port Clock Enable +// PCK0: Programmable Clock 0 Output Enable +// PCK1: Programmable Clock 1 Output Enable +// PCK2: Programmable Clock 2 Output Enable +// +// +// Peripheral Clock Enable Register 0 (PMC_PCER0) +// PID2: Real Time Clock Clock Enable +// PID3: Real Time Timer Clock Enable +// PID4: Watchdog Timer Clock Enable +// PID5: Power Management Controller Clock Enable +// PID6: Enhanced Embedded Flash Controller Clock Enable +// PID8: UART 0 Clock Enable +// PID9: UART 1 Clock Enable Clock Enable +// PID10: Static Memory Controller Clock Enable +// PID11: Parallel I/O Controller A Clock Enable +// PID12: Parallel I/O Controller B Clock Enable +// PID13: Parallel I/O Controller C Clock Enable +// PID14: USART 0 Clock Enable +// PID15: USART 1 Clock Enable +// PID18: Multimedia Card Interface Clock Enable +// PID19: Two-wire Interface 0 Clock Enable +// PID20: Two-wire Interface 1 Clock Enable +// PID21: Serial Peripheral Interface Clock Enable +// PID22: Synchronous Serial Controller Clock Enable +// PID23: Timer Counter 0 Clock Enable +// PID24: Timer Counter 1 Clock Enable +// PID25: Timer Counter 2 Clock Enable +// PID26: Timer Counter 3 Clock Enable +// PID27: Timer Counter 4 Clock Enable +// PID28: Timer Counter 5 Clock Enable +// PID29: Analog-to-Digital Converter Clock Enable +// PID30: Digital-to-Analog Converter Clock Enable +// PID31: Pulse Width Modulation Clock Enable +// +// +// Peripheral Clock Enable Register 1 (PMC_PCER1) +// PID32: CRC Calculation Unit Clock Enable +// PID33: Analog Comparator Clock Enable +// PID34: USB Device Port Clock Enable +// +// +// Main Oscillator Register (CKGR_MOR) +// MOSCXTEN: Main Crystal Oscillator Enable +// MOSCXTBY: Main Crystal Oscillator Bypass +// WAITMODE: Wait Mode Command +// MOSCRCEN: Main On-chip RC Oscillator Enable +// MOSCRCF: Main On-chip RC Oscillator Frequency Selection +// <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved +// MOSCXTST: Main Crystal Oscillator Startup Time <0-255> +// MOSCSEL: Main Oscillator Selection +// <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator +// CFDEN: Clock Failure Detector Enable +// +// +// Clock Generator Phase Locked Loop A Register (CKGR_PLLAR) +// PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1) +// Example: XTAL = 12 MHz, DIVA = 1, MULA = 14 => PLLA = 168 MHz +// DIVA: PLL Divider A <0-255> +// 0 - Divider output is 0 +// 1 - Divider is bypassed +// 2 .. 255 - Divider output is the Main Clock divided by DIVA +// PLLACOUNT: PLL A Counter <0-63> +// Number of Slow Clocks before the LOCKA bit is set in +// PMC_SR after CKGR_PLLAR is written +// MULA: PLL A Multiplier <0-2047> +// 0 - The PLL A is deactivated +// 1 .. 2047 - The PLL A Clock frequency is the PLLA input +// frequency multiplied by MULA + 1 +// +// +// Clock Generator Phase Locked Loop B Register (CKGR_PLLBR) +// PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1) +// Example: XTAL = 12 MHz, DIVB = 1, MULB = 14 => PLLB = 168 MHz +// DIVB: PLL Divider B <0-255> +// 0 - Divider output is 0 +// 1 - Divider is bypassed +// 2 .. 255 - Divider output is the Main Clock divided by DIVB +// PLLBCOUNT: PLL B Counter <0-63> +// Number of Slow Clocks before the LOCKB bit is set in +// PMC_SR after CKGR_PLLBR is written +// MULB: PLL B Multiplier <0-2047> +// 0 - The PLL B is deactivated +// 1 .. 2047 - The PLL B Clock frequency is the PLLB input +// frequency multiplied by MULB + 1 +// +// +// Master Clock Register (PMC_MCKR) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLL A Clock +// <3=> PLL B Clock +// PRES: Master Clock Prescaler +// <0=> Clock <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Clock / 3 +// PLLADIV2: PLLA Divisor by 2 +// PLLBDIV2: PLLB Divisor by 2 +// +// +// USB Clock Register (PMC_USB) +// USBS: USB Input Clock Selection +// <0=> PLLA Clock +// <1=> PLLB Clock +// USBDIV: USB Input Clock Devider <0-15> +// USB Clock is Input clock divided by USBDIV+1 +// +// +// Programmable Clock Register 0 (PMC_PCK0) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLLA Clock +// <3=> PLLB Clock +// <4=> Master Clock +// <5=> Master Clock +// <6=> Master Clock +// <7=> Master Clock +// PRES: Programmable Clock Prescaler +// <0=> Clock <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Reserved +// +// +// Programmable Clock Register 1 (PMC_PCK1) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLLA Clock +// <3=> PLLB Clock +// <4=> Master Clock +// <5=> Master Clock +// <6=> Master Clock +// <7=> Master Clock +// PRES: Programmable Clock Prescaler +// <0=> None <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Reserved +// +// +// Programmable Clock Register 2 (PMC_PCK2) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLLA Clock +// <3=> PLLB Clock +// <4=> Master Clock +// <5=> Master Clock +// <6=> Master Clock +// <7=> Master Clock +// PRES: Programmable Clock Prescaler +// <0=> None <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Reserved +// +// +*/ +#define PMC_SETUP 1 // Reset values: +#define PMC_SCER_Val 0x00000000 // WO register (0x00000001) +#define PMC_PCER0_Val 0x00000000 // WO register (0x00000000) +#define PMC_PCER1_Val 0x00001C00 // WO register (0x00000000) +#define CKGR_MOR_Val 0x01370F01 // 0x00000001 +#define CKGR_PLLAR_Val 0x201F0603 // 0x00003F00 +#define CKGR_PLLBR_Val 0x20170603 // 0x00003F00 +#define PMC_MCKR_Val 0x00000012 // 0x00000001 +#define PMC_USB_Val 0x00000101 // 0x00000000 +#define PMC_PCK0_Val 0x00000000 // 0x00000000 +#define PMC_PCK1_Val 0x00000000 // 0x00000000 +#define PMC_PCK2_Val 0x00000000 // 0x00000000 + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Disable +// +*/ +#define WDT_SETUP 1 // Reset values: + + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Embedded Flash Controllers Configuration ----------------------------------*/ +#if (CHECK_RSVD((EEFC_FMR_Val), ~0x01000F01)) + #error "EEFC_FMR: Invalid values of reserved bits!" +#endif + +/* Power Management Controller Configuration ---------------------------------*/ +#if (CHECK_RSVD((PMC_SCER_Val), ~0x00000780)) + #error "PMC_SCER: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCER0_Val), ~0xFFFFFFFC)) + #error "PMC_PCER0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCER1_Val), ~0xFFFFFFFF)) + #error "PMC_PCER1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CKGR_MOR_Val), ~0x03FFFF7F)) + #error "CKGR_MOR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CKGR_PLLAR_Val), ~0x27FFFFFF)) + #error "CKGR_PLLAR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CKGR_PLLBR_Val), ~0x27FF3FFF)) + #error "CKGR_PLLBR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_MCKR_Val), ~0x00003073)) + #error "PMC_MCKR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_USB_Val), ~0x00000F01)) + #error "PMC_USB: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCK0_Val), ~0x00000077)) + #error "PMC_PCK0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCK1_Val), ~0x00000077)) + #error "PMC_PCK1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCK2_Val), ~0x00000077)) + #error "PMC_PCK2: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Crystal frequency */ +#define XTAL32 ( 32768UL) /* 32k crystal frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */ +#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */ +#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */ + + + +#if (PMC_SETUP) + /* Determine clock frequency according to clock register values */ + #if ((PMC_MCKR_Val & 3) == 0) /* Slow Clock is selected */ + #if (1 /* PMC_SR & (1 << 7) */) /* MUST be checked with correct register */ + #define __CORE_CLK_PRE (OSC32_CLK) + #else + #define __CORE_CLK_PRE (ERC_OSC) + #endif + #elif ((PMC_MCKR_Val & 3) == 1) /* Main Clock is selected */ + #if (CKGR_MOR_Val & (1 << 24)) + #if ((CKGR_MOR_Val & (1<< 0)) == 0) + #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!" + #endif + #define __CORE_CLK_PRE (OSC_CLK) + #else + #if ((CKGR_MOR_Val & (1<< 3)) == 0) + #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!" + #endif + #if (((CKGR_MOR_Val >> 4) & 3) == 0) + #define __CORE_CLK_PRE (EFRC_OSC) + #elif (((CKGR_MOR_Val >> 4) & 3) == 1) + #define __CORE_CLK_PRE (EFRC_OSC * 2) + #elif (((CKGR_MOR_Val >> 4) & 3) == 2) + #define __CORE_CLK_PRE (EFRC_OSC * 3) + #else + #define __CORE_CLK_PRE (EFRC_OSC) + #endif + #endif + #elif ((PMC_MCKR_Val & 3) == 2) /* PLLA Clock is selected */ + #if (CKGR_MOR_Val & (1 << 24)) + #if ((CKGR_MOR_Val & (1<< 0)) == 0) + #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!" + #endif + #define __PLLA_CLK (OSC_CLK) + #else + #if ((CKGR_MOR_Val & (1<< 3)) == 0) + #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!" + #endif + #if (((CKGR_MOR_Val >> 4) & 3) == 0) + #define __PLLA_CLK (EFRC_OSC) + #elif (((CKGR_MOR_Val >> 4) & 3) == 1) + #define __PLLA_CLK (EFRC_OSC * 2) + #elif (((CKGR_MOR_Val >> 4) & 3) == 2) + #define __PLLA_CLK (EFRC_OSC * 3) + #else + #define __PLLA_CLK (EFRC_OSC) + #endif + #endif + + #define __PLLA_MUL ((((CKGR_PLLAR_Val) >> 16) & 0x7FF) + 1) + #define __PLLA_DIV ((((CKGR_PLLAR_Val) >> 0) & 0x0FF)) + #define __CORE_CLK_PRE (__PLLA_CLK * __PLLA_MUL / __PLLA_DIV) + #else /* PLLB Clock is selected */ + #if (CKGR_MOR_Val & (1 << 24)) + #if ((CKGR_MOR_Val & (1<< 0)) == 0) + #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!" + #endif + #define __PLLB_CLK (OSC_CLK) + #else + #if ((CKGR_MOR_Val & (1<< 3)) == 0) + #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!" + #endif + #if (((CKGR_MOR_Val >> 4) & 3) == 0) + #define __PLLB_CLK (EFRC_OSC) + #elif (((CKGR_MOR_Val >> 4) & 3) == 1) + #define __PLLB_CLK (EFRC_OSC * 2) + #elif (((CKGR_MOR_Val >> 4) & 3) == 2) + #define __PLLB_CLK (EFRC_OSC * 3) + #else + #define __PLLB_CLK (EFRC_OSC) + #endif + #endif + + #define __PLLB_MUL ((((CKGR_PLLBR_Val) >> 16) & 0x7FF) + 1) + #define __PLLB_DIV ((((CKGR_PLLBR_Val) >> 0) & 0x0FF)) + #define __CORE_CLK_PRE (__PLLB_CLK * __PLLB_MUL / __PLLB_DIV) + #endif + + #if (((PMC_MCKR_Val >> 4) & 7) == 7) + #define __CORE_CLK (__CORE_CLK_PRE / 3) + #else + #define __CORE_CLK (__CORE_CLK_PRE >> ((PMC_MCKR_Val >> 4) & 7)) + #endif + +#else + #define __CORE_CLK (EFRC_OSC) +#endif + +#if (__CORE_CLK > 64000000UL) + #error "Core Clock > 64MHz!" +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & 3) { + case 0: /* Slow clock */ + if (SUPC->SUPC_SR & (1 << 7)) + SystemCoreClock = OSC32_CLK; + else + SystemCoreClock = ERC_OSC; + break; + case 1: /* Main clock */ + if (PMC->CKGR_MOR & (1 << 24)) + SystemCoreClock = OSC_CLK; + else { + SystemCoreClock = EFRC_OSC; + switch ((PMC->CKGR_MOR >> 4) & 3) { + case 0: + break; + case 1: + SystemCoreClock *= 2; + break; + case 2: + SystemCoreClock *= 3; + break; + case 3: + break; + } + } + break; + case 2: /* PLLA clock */ + if (PMC->CKGR_MOR & (1 << 24)) + SystemCoreClock = OSC_CLK; + else { + SystemCoreClock = EFRC_OSC; + switch ((PMC->CKGR_MOR >> 4) & 3) { + case 0: + break; + case 1: + SystemCoreClock *= 2; + break; + case 2: + SystemCoreClock *= 3; + break; + case 3: + break; + } + } + SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> 16) & 0x7FF) + 1); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> 0) & 0x0FF)); + break; + case 3: /* PLLB clock */ + if (PMC->CKGR_MOR & (1 << 24)) + SystemCoreClock = OSC_CLK; + else { + SystemCoreClock = EFRC_OSC; + switch ((PMC->CKGR_MOR >> 4) & 3) { + case 0: + break; + case 1: + SystemCoreClock *= 2; + break; + case 2: + SystemCoreClock *= 3; + break; + case 3: + break; + } + } + SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> 16) & 0x7FF) + 1); + SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> 0) & 0x0FF)); + break; + } + + if (((PMC->PMC_MCKR >> 4) & 7) == 7) + SystemCoreClock /= 3; + else + SystemCoreClock >>= ((PMC->PMC_MCKR >> 4) & 7); + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +void SystemInit (void) +{ +#if (EEFC_SETUP == 1) /* Embedded Flash Controller 0 Setup */ + EFC->EEFC_FMR = EEFC_FMR_Val; +#endif + +PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */ + +#if (PMC_SETUP == 1) /* Power Management Controller Setup */ + +#if (CKGR_MOR_Val & ((1<<3)|(1<<0))) /* If MOSCRCEN or MOSCXTEN set */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & (1<<24)) | /* Keep the current MOSCSEL */ + (CKGR_MOR_Val & ~(1<<24)) | /* Set value except MOSCSEL */ + ((1<<3)|(1<<0)); /* and enable bothe OSC */ +#if (CKGR_MOR_Val & ((1 << 3))) + while (!(PMC->PMC_SR & (1 << 17))); /* Wait for MOSCRCS */ +#endif +#if (CKGR_MOR_Val & ((1 << 0))) + while (!(PMC->PMC_SR & (1 << 0))); /* Wait for MOSCXTS */ +#endif + PMC->CKGR_MOR = CKGR_MOR_Val; /* set the desired selection */ + while (!(PMC->PMC_SR & (1 << 16))); /* Wait for MOSCSELS */ +#endif + +#if (CKGR_PLLAR_Val & ((0x7FF<<16))) /* If MULA != 0 */ + PMC->CKGR_PLLAR = CKGR_PLLAR_Val | (1 << 29); + while (!(PMC->PMC_SR & (1 << 1))); /* Wait for LOCKA */ +#endif + +#if (CKGR_PLLBR_Val & ((0x7FF<<16))) /* If MULB != 0 */ + PMC->CKGR_PLLBR = CKGR_PLLBR_Val; + while (!(PMC->PMC_SR & (1 << 2))); /* Wait for LOCKB */ +#endif + + if ((PMC_MCKR_Val & 0x03) >= 2) { + /* Write PRES field only */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x70) | (PMC_MCKR_Val & 0x70); + } else { + /* Write CSS field only */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x03) | (PMC_MCKR_Val & 0x03); + } + while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */ + PMC->PMC_MCKR = PMC_MCKR_Val; /* Write all MCKR */ + while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */ + +#if (PMC_PCK0_Val) + PMC->PMC_PCK[0] = PMC_PCK0_Val; /* Write PCK0 */ + while (!(PMC->PMC_SR & (1 << 8))); /* Wait for PCKRDY0 */ +#endif +#if (PMC_PCK1_Val) + PMC->PMC_PCK[1] = PMC_PCK1_Val; /* Write PCK1 */ + while (!(PMC->PMC_SR & (1 << 9))); /* Wait for PCKRDY1 */ +#endif +#if (PMC_PCK2_Val) + PMC->PMC_PCK[2] = PMC_PCK2_Val; /* Write PCK2 */ + while (!(PMC->PMC_SR & (1 << 10))); /* Wait for PCKRDY2 */ +#endif + + PMC->PMC_USB = PMC_USB_Val; + PMC->PMC_SCER = PMC_SCER_Val; + PMC->PMC_PCER0 = PMC_PCER0_Val; + PMC->PMC_PCER1 = PMC_PCER1_Val; +#endif + +PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */ + +#if (WDT_SETUP == 1) /* Watchdog Setup */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S1A.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S1A.atdf new file mode 100644 index 0000000..8030d76 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S1A.atdf @@ -0,0 +1,7079 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S1B.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S1B.atdf new file mode 100644 index 0000000..f7e4ed9 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S1B.atdf @@ -0,0 +1,7684 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S1C.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S1C.atdf new file mode 100644 index 0000000..54f0b53 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S1C.atdf @@ -0,0 +1,7879 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S2A.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S2A.atdf new file mode 100644 index 0000000..44c5c83 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S2A.atdf @@ -0,0 +1,7083 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S2B.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S2B.atdf new file mode 100644 index 0000000..c10df31 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S2B.atdf @@ -0,0 +1,7688 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S2C.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S2C.atdf new file mode 100644 index 0000000..fc4390d --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S2C.atdf @@ -0,0 +1,7883 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S4A.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S4A.atdf new file mode 100644 index 0000000..a26ade7 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S4A.atdf @@ -0,0 +1,7091 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S4B.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S4B.atdf new file mode 100644 index 0000000..821a277 --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S4B.atdf @@ -0,0 +1,7696 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/atdf/ATSAM3S4C.atdf b/zephyr/ports/asf/sam3s/atdf/ATSAM3S4C.atdf new file mode 100644 index 0000000..abf225b --- /dev/null +++ b/zephyr/ports/asf/sam3s/atdf/ATSAM3S4C.atdf @@ -0,0 +1,7891 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_flash.ld new file mode 100644 index 0000000..317a5b7 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S1A + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00010000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_sram.ld new file mode 100644 index 0000000..2c00107 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1a_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S1A + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00010000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_flash.ld new file mode 100644 index 0000000..4459663 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S1B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00010000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_sram.ld new file mode 100644 index 0000000..862a25e --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1b_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S1B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00010000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_flash.ld new file mode 100644 index 0000000..7a96d37 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S1C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00010000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_sram.ld new file mode 100644 index 0000000..4a3ff89 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s1c_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S1C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00010000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00004000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_flash.ld new file mode 100644 index 0000000..a2325de --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S2A + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00020000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_sram.ld new file mode 100644 index 0000000..8ef4fab --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2a_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S2A + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00020000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_flash.ld new file mode 100644 index 0000000..a8beda8 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S2B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00020000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_sram.ld new file mode 100644 index 0000000..26b4d83 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2b_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S2B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00020000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_flash.ld new file mode 100644 index 0000000..aacc4ea --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S2C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00020000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_sram.ld new file mode 100644 index 0000000..c7b09e1 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s2c_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S2C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00020000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_flash.ld new file mode 100644 index 0000000..2230f24 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S4A + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_sram.ld new file mode 100644 index 0000000..5312ac5 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4a_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S4A + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_flash.ld new file mode 100644 index 0000000..9ed0bf8 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S4B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_sram.ld new file mode 100644 index 0000000..5c9bede --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4b_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S4B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_flash.ld new file mode 100644 index 0000000..8a7730a --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_flash.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S4C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_flash.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_sram.ld new file mode 100644 index 0000000..e3d4ec3 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s4c_sram.ld @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S4C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0000C000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x400; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x200; + +INCLUDE sam3s_sram.ld diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s_flash.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s_flash.ld new file mode 100644 index 0000000..2ba1381 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s_flash.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/sam3s_sram.ld b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s_sram.ld new file mode 100644 index 0000000..11b3f54 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/sam3s_sram.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(8); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(8); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/zephyr/ports/asf/sam3s/gcc/gcc/startup_sam3s.c b/zephyr/ports/asf/sam3s/gcc/gcc/startup_sam3s.c new file mode 100644 index 0000000..fa6e441 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/gcc/startup_sam3s.c @@ -0,0 +1,237 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#include "sam3s.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M3 core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3S_PIOC_INSTANCE_ +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3S_PIOC_INSTANCE_ */ +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3S_USART1_INSTANCE_ +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3S_USART1_INSTANCE_ */ +#ifdef _SAM3S_HSMCI_INSTANCE_ +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3S_HSMCI_INSTANCE_ */ +void TWI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3S_TC1_INSTANCE_ +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3S_TC1_INSTANCE_ */ +#ifdef _SAM3S_TC1_INSTANCE_ +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3S_TC1_INSTANCE_ */ +#ifdef _SAM3S_TC1_INSTANCE_ +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3S_TC1_INSTANCE_ */ +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CRCCU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UDP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNMI_Handler = (void*) NMI_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManage_Handler = (void*) MemManage_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pfnReserved1_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved2_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved3_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved4_Handler = (void*) (0UL), /* Reserved */ + .pfnSVC_Handler = (void*) SVC_Handler, + .pfnDebugMon_Handler = (void*) DebugMon_Handler, + .pfnReserved5_Handler = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */ + .pvReserved7 = (void*) (0UL), /* 7 Reserved */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 8 UART 0 */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 9 UART 1 */ + .pvReserved10 = (void*) (0UL), /* 10 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 11 Parallel I/O Controller A */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 12 Parallel I/O Controller B */ +#ifdef _SAM3S_PIOC_INSTANCE_ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 13 Parallel I/O Controller C */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif /* _SAM3S_PIOC_INSTANCE_ */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 14 USART 0 */ +#ifdef _SAM3S_USART1_INSTANCE_ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 15 USART 1 */ +#else + .pvReserved15 = (void*) (0UL), /* 15 Reserved */ +#endif /* _SAM3S_USART1_INSTANCE_ */ + .pvReserved16 = (void*) (0UL), /* 16 Reserved */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ +#ifdef _SAM3S_HSMCI_INSTANCE_ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */ +#else + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ +#endif /* _SAM3S_HSMCI_INSTANCE_ */ + .pfnTWI0_Handler = (void*) TWI0_Handler, /* 19 Two Wire Interface 0 */ + .pfnTWI1_Handler = (void*) TWI1_Handler, /* 20 Two Wire Interface 1 */ + .pfnSPI_Handler = (void*) SPI_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controler */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */ +#ifdef _SAM3S_TC1_INSTANCE_ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif /* _SAM3S_TC1_INSTANCE_ */ +#ifdef _SAM3S_TC1_INSTANCE_ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif /* _SAM3S_TC1_INSTANCE_ */ +#ifdef _SAM3S_TC1_INSTANCE_ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif /* _SAM3S_TC1_INSTANCE_ */ + .pfnADC_Handler = (void*) ADC_Handler, /* 29 Analog To Digital Converter */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */ + .pfnPWM_Handler = (void*) PWM_Handler, /* 31 Pulse Width Modulation */ + .pfnCRCCU_Handler = (void*) CRCCU_Handler, /* 32 CRC Calculation Unit */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */ + .pfnUDP_Handler = (void*) UDP_Handler /* 34 USB Device Port */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/zephyr/ports/asf/sam3s/gcc/system_sam3s.c b/zephyr/ports/asf/sam3s/gcc/system_sam3s.c new file mode 100644 index 0000000..ccbfc22 --- /dev/null +++ b/zephyr/ports/asf/sam3s/gcc/system_sam3s.c @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#include "sam3s.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* Clock settings (64MHz) */ +#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8UL)) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x1fUL) | \ + CKGR_PLLAR_PLLACOUNT(0x3fUL) | CKGR_PLLAR_DIVA(0x3UL)) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) + +uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + +/** + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +void SystemInit( void ) +{ + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC->EEFC_FMR = EEFC_FMR_FWS(3); + + /* Initialize main oscillator */ + if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) + { + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) + { + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) + { + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) + { + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) + { + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; + + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +} + +void SystemCoreClockUpdate( void ) +{ + /* Determine clock frequency according to clock register values */ + switch ( PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk ) + { + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_32K; + } + else + { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + } + break; + + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + break; + + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + + if ( (uint32_t)(PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK ) + { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos)); + } + else + { + SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >> CKGR_PLLBR_MULB_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> CKGR_PLLBR_DIVB_Pos)); + } + break; + + default: + break; + } + + if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 ) + { + SystemCoreClock /= 3U; + } + else + { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos); + } +} + +/** + * Initialize flash. + */ +void system_init_flash( uint32_t dw_clk ) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if ( dw_clk < CHIP_FREQ_FWS_0 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 0 ); + } + else + { + if ( dw_clk < CHIP_FREQ_FWS_1 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 1 ); + } + else + { + if ( dw_clk < CHIP_FREQ_FWS_2 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 2 ); + } + else + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 3 ) ; + } + } + } +} + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/zephyr/ports/asf/sam3s/include/component-version.h b/zephyr/ports/asf/sam3s/include/component-version.h new file mode 100644 index 0000000..d54b32d --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component-version.h @@ -0,0 +1,72 @@ +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 0 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION +// is at least 8 digits long. +// +#define COMPONENT_VERSION 00010000 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 70 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.0" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2016-09-15 13:24:33" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/zephyr/ports/asf/sam3s/include/component/acc.h b/zephyr/ports/asf/sam3s/include/component/acc.h new file mode 100644 index 0000000..1f3de03 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/acc.h @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_ACC_COMPONENT_ +#define _SAM3S_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */ +#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */ +#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */ +#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */ +#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */ +#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */ +#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */ +#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */ +#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */ +#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */ +#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */ +#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ +#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ + +/*@}*/ + + +#endif /* _SAM3S_ACC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/adc.h b/zephyr/ports/asf/sam3s/include/component/adc.h new file mode 100644 index 0000000..5960558 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/adc.h @@ -0,0 +1,452 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_ADC_COMPONENT_ +#define _SAM3S_ADC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */ +/* ============================================================================= */ +/** \addtogroup SAM3S_ADC Analog-to-Digital Converter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Adc hardware registers */ +typedef struct { + __O uint32_t ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + __IO uint32_t ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + __IO uint32_t ADC_SEQR[2]; /**< \brief (Adc Offset: 0x08) Channel Sequence Register */ + __O uint32_t ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + __O uint32_t ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + __I uint32_t ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + __I uint32_t Reserved1[1]; + __I uint32_t ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + __O uint32_t ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[2]; + __I uint32_t ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + __IO uint32_t ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + __IO uint32_t ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + __IO uint32_t ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + __IO uint32_t ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + __I uint32_t ADC_CDR[15]; /**< \brief (Adc Offset: 0x50) Channel Data Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved4[19]; + __IO uint32_t ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ + __I uint32_t Reserved5[5]; + __IO uint32_t ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ + __IO uint32_t ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ + __I uint32_t Reserved7[2]; + __O uint32_t ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ + __I uint32_t ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define ADC_MR_TRGSEL_Pos 1 +#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos))) +#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */ +#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */ +#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */ +#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */ +#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ +#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The wake-up time can be modified by programming FWUP bit */ +#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions */ +#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */ +#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */ +#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */ +#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */ +#define ADC_MR_PRESCAL_Pos 8 +#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) +#define ADC_MR_STARTUP_Pos 16 +#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos))) +#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */ +#define ADC_MR_SETTLING_Pos 20 +#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_SETTLING(value) ((ADC_MR_SETTLING_Msk & ((value) << ADC_MR_SETTLING_Pos))) +#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */ +#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */ +#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */ +#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */ +#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */ +#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */ +#define ADC_MR_TRACKTIM_Pos 24 +#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) +#define ADC_MR_TRANSFER_Pos 28 +#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */ +#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos))) +#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */ +#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. */ +#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. */ +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ +#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ +#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ +#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ +#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ +#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ +#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ +#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ +#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ +#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA_Pos 0 +#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB_Pos 12 +#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ +#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ +#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ +#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ +#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ +#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ +#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ +#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ +#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ +#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ +#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ +#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ +#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ +#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ +#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ +#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ +#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ +#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ +#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ +#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */ +#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ +#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ +#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ +#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE_Pos 0 +#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE(value) ((ADC_EMR_CMPMODE_Msk & ((value) << ADC_EMR_CMPMODE_Pos))) +#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */ +#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define ADC_EMR_CMPSEL_Pos 4 +#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) +#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of the ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES_Pos 0 +#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) +#define ADC_CWR_HIGHTHRES_Pos 16 +#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */ +#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0_Pos 0 +#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for Channel 0 */ +#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos))) +#define ADC_CGR_GAIN1_Pos 2 +#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for Channel 1 */ +#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos))) +#define ADC_CGR_GAIN2_Pos 4 +#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for Channel 2 */ +#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos))) +#define ADC_CGR_GAIN3_Pos 6 +#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for Channel 3 */ +#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos))) +#define ADC_CGR_GAIN4_Pos 8 +#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for Channel 4 */ +#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos))) +#define ADC_CGR_GAIN5_Pos 10 +#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for Channel 5 */ +#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos))) +#define ADC_CGR_GAIN6_Pos 12 +#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for Channel 6 */ +#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos))) +#define ADC_CGR_GAIN7_Pos 14 +#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for Channel 7 */ +#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos))) +#define ADC_CGR_GAIN8_Pos 16 +#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for Channel 8 */ +#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos))) +#define ADC_CGR_GAIN9_Pos 18 +#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for Channel 9 */ +#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos))) +#define ADC_CGR_GAIN10_Pos 20 +#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for Channel 10 */ +#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos))) +#define ADC_CGR_GAIN11_Pos 22 +#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for Channel 11 */ +#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos))) +#define ADC_CGR_GAIN12_Pos 24 +#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for Channel 12 */ +#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos))) +#define ADC_CGR_GAIN13_Pos 26 +#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for Channel 13 */ +#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos))) +#define ADC_CGR_GAIN14_Pos 28 +#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for Channel 14 */ +#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos))) +#define ADC_CGR_GAIN15_Pos 30 +#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for Channel 15 */ +#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos))) +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */ +#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */ +#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */ +#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */ +#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ +#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ +#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ +#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ +/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */ +#define ADC_CDR_DATA_Pos 0 +#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ +#define ADC_ACR_IBCTL_Pos 8 +#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */ +#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY_Pos 8 +#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */ +#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) +#define ADC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (ADC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC_Pos 8 +#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */ +/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ +#define ADC_RPR_RXPTR_Pos 0 +#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ +#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) +/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ +#define ADC_RCR_RXCTR_Pos 0 +#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */ +#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) +/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ +#define ADC_RNPR_RXNPTR_Pos 0 +#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */ +#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) +/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ +#define ADC_RNCR_RXNCTR_Pos 0 +#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */ +#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) +/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ +#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ +#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ +#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ +#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ +/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ +#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ +#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_ADC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/chipid.h b/zephyr/ports/asf/sam3s/include/component/chipid.h new file mode 100644 index 0000000..eed0a1b --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/chipid.h @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_CHIPID_COMPONENT_ +#define _SAM3S_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAM3S_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */ +#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */ +#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */ +#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */ +#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */ +#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */ +#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */ +#define CHIPID_CIDR_ARCH_AT91SAM4SH2 (0x45u << 20) /**< \brief (CHIPID_CIDR) AT91SAM4SH2 Series */ +#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */ +#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */ +#define CHIPID_CIDR_ARCH_SAM4CxxC (0x64u << 20) /**< \brief (CHIPID_CIDR) SAM4CxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */ +#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */ +#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */ +#define CHIPID_CIDR_ARCH_SAM4LxA (0xB0u << 20) /**< \brief (CHIPID_CIDR) SAM4LxA Series (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4LxB (0xB1u << 20) /**< \brief (CHIPID_CIDR) SAM4LxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4LxC (0xB2u << 20) /**< \brief (CHIPID_CIDR) SAM4LxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAM3S_CHIPID_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/crccu.h b/zephyr/ports/asf/sam3s/include/component/crccu.h new file mode 100644 index 0000000..24cb350 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/crccu.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_CRCCU_COMPONENT_ +#define _SAM3S_CRCCU_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ +/* ============================================================================= */ +/** \addtogroup SAM3S_CRCCU Cyclic Redundancy Check Calculation Unit */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Crccu hardware registers */ +typedef struct { + __IO uint32_t CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ + __I uint32_t Reserved1[1]; + __O uint32_t CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ + __O uint32_t CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ + __I uint32_t CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ + __O uint32_t CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ + __O uint32_t CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ + __I uint32_t CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ + __I uint32_t CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ + __I uint32_t Reserved2[4]; + __O uint32_t CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ + __IO uint32_t CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ + __I uint32_t CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ + __O uint32_t CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ + __O uint32_t CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ + __I uint32_t CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ + __I uint32_t CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ +} Crccu; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ +#define CRCCU_DSCR_DSCR_Pos 9 +#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ +#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) +/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ +#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ +/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ +#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ +/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ +#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ +/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ +#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ +/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ +#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ +/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ +#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ +/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ +#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ +/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ +#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ +/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ +#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */ +#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */ +#define CRCCU_MR_PTYPE_Pos 2 +#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */ +#define CRCCU_MR_PTYPE(value) ((CRCCU_MR_PTYPE_Msk & ((value) << CRCCU_MR_PTYPE_Pos))) +#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ +#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ +#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ +#define CRCCU_MR_DIVIDER_Pos 4 +#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */ +#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) +/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ +#define CRCCU_SR_CRC_Pos 0 +#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ +/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ +#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ +/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ +#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ +/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ +#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ +/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ +#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ + +/*@}*/ + + +#endif /* _SAM3S_CRCCU_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/dacc.h b/zephyr/ports/asf/sam3s/include/component/dacc.h new file mode 100644 index 0000000..ff78b6a --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/dacc.h @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_DACC_COMPONENT_ +#define _SAM3S_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved3[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved4[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ + __I uint32_t Reserved5[7]; + __IO uint32_t DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ + __I uint32_t DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */ +#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */ +#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */ +#define DACC_MR_TRGSEL_Pos 1 +#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */ +#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos))) +#define DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /**< \brief (DACC_MR) External trigger */ +#define DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 0 */ +#define DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 1 */ +#define DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /**< \brief (DACC_MR) TIO Output of the Timer Counter Channel 2 */ +#define DACC_MR_TRGSEL_TRGSEL4 (0x4u << 1) /**< \brief (DACC_MR) PWM Event Line 0 */ +#define DACC_MR_TRGSEL_TRGSEL5 (0x5u << 1) /**< \brief (DACC_MR) PWM Event Line 1 */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */ +#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */ +#define DACC_MR_SLEEP_DISABLED (0x0u << 5) /**< \brief (DACC_MR) Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. */ +#define DACC_MR_SLEEP_ENABLED (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. */ +#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ +#define DACC_MR_FASTWKUP_STAMODE (0x0u << 6) /**< \brief (DACC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. */ +#define DACC_MR_FASTWKUP_FASTWAKEUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_USER_SEL_Pos 16 +#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL(value) ((DACC_MR_USER_SEL_Msk & ((value) << DACC_MR_USER_SEL_Pos))) +#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */ +#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */ +#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */ +#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */ +#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */ +#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */ +#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */ +#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_STARTUP_Pos 24 +#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */ +#define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos))) +#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */ +#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */ +#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */ +#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */ +#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */ +#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */ +#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */ +#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */ +#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */ +#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */ +#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */ +#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */ +#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */ +#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */ +#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */ +#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */ +#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */ +#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */ +#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */ +#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */ +#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */ +#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */ +#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */ +#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */ +#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */ +#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */ +#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */ +#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */ +#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */ +#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */ +#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */ +#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ +#define DACC_CDR_DATA_Pos 0 +#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */ +#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ +#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ +#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ +#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ +#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ +#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ +#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ +#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ +#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ +#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ +#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ +#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ +#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +#define DACC_ACR_IBCTLDACCORE_Pos 8 +#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ +#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ +#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */ +#define DACC_WPSR_WPROTADDR_Pos 8 +#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */ +/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ +#define DACC_TPR_TXPTR_Pos 0 +#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */ +#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) +/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ +#define DACC_TCR_TXCTR_Pos 0 +#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */ +#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) +/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define DACC_TNPR_TXNPTR_Pos 0 +#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */ +#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) +/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define DACC_TNCR_TXNCTR_Pos 0 +#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */ +#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) +/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ +#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ +#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ +#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ +#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ +/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ +#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ +#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_DACC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/efc.h b/zephyr/ports/asf/sam3s/include/component/efc.h new file mode 100644 index 0000000..8084912 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/efc.h @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_EFC_COMPONENT_ +#define _SAM3S_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash Descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set Lock Bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear Lock Bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get Lock Bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM Bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM Bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM Bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start Read Unique Identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop Read Unique Identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB Bit */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ + +/*@}*/ + + +#endif /* _SAM3S_EFC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/gpbr.h b/zephyr/ports/asf/sam3s/include/component/gpbr.h new file mode 100644 index 0000000..14f3787 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_GPBR_COMPONENT_ +#define _SAM3S_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAM3S_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAM3S_GPBR_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/hsmci.h b/zephyr/ports/asf/sam3s/include/component/hsmci.h new file mode 100644 index 0000000..558d239 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/hsmci.h @@ -0,0 +1,391 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_HSMCI_COMPONENT_ +#define _SAM3S_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3S_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved3[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[5]; + __IO uint32_t HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ + __IO uint32_t HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ + __IO uint32_t HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ + __I uint32_t HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ + __I uint32_t Reserved5[54]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ +#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ +#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ +#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ +#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ +#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ +#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ +#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ +#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_Pos 8 +#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS_Pos 0 +#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ +#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ +#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ +#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ +#define HSMCI_WPSR_WP_VSRC_Pos 8 +#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ +#define HSMCI_RPR_RXPTR_Pos 0 +#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */ +#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos))) +/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ +#define HSMCI_RCR_RXCTR_Pos 0 +#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */ +#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos))) +/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ +#define HSMCI_TPR_TXPTR_Pos 0 +#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */ +#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos))) +/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ +#define HSMCI_TCR_TXCTR_Pos 0 +#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */ +#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos))) +/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ +#define HSMCI_RNPR_RXNPTR_Pos 0 +#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ +#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos))) +/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ +#define HSMCI_RNCR_RXNCTR_Pos 0 +#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */ +#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos))) +/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define HSMCI_TNPR_TXNPTR_Pos 0 +#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ +#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos))) +/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define HSMCI_TNCR_TXNCTR_Pos 0 +#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ +#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos))) +/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ +#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ +#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ +#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ +#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ +/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ +#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ +#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_HSMCI_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/matrix.h b/zephyr/ports/asf/sam3s/include/component/matrix.h new file mode 100644 index 0000000..d86b46f --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/matrix.h @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_MATRIX_COMPONENT_ +#define _SAM3S_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAM3S_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Matrix hardware registers */ +typedef struct { + __IO uint32_t MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + __I uint32_t Reserved1[12]; + __IO uint32_t MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved2[11]; + __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + __I uint32_t Reserved3[1]; + __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + __I uint32_t Reserved4[1]; + __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + __I uint32_t Reserved5[1]; + __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + __I uint32_t Reserved6[1]; + __IO uint32_t MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + __I uint32_t Reserved7[1]; + __I uint32_t Reserved8[27]; + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */ + __I uint32_t Reserved9[1]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ + __I uint32_t Reserved10[49]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +#define MATRIX_SCFG_ARBT_Pos 24 +#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ +#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR_Pos 0 +#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) +#define MATRIX_PRAS0_M1PR_Pos 4 +#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) +#define MATRIX_PRAS0_M2PR_Pos 8 +#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) +#define MATRIX_PRAS0_M3PR_Pos 12 +#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) +#define MATRIX_PRAS0_M4PR_Pos 16 +#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR_Pos 0 +#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) +#define MATRIX_PRAS1_M1PR_Pos 4 +#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) +#define MATRIX_PRAS1_M2PR_Pos 8 +#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) +#define MATRIX_PRAS1_M3PR_Pos 12 +#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) +#define MATRIX_PRAS1_M4PR_Pos 16 +#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR_Pos 0 +#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) +#define MATRIX_PRAS2_M1PR_Pos 4 +#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) +#define MATRIX_PRAS2_M2PR_Pos 8 +#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) +#define MATRIX_PRAS2_M3PR_Pos 12 +#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) +#define MATRIX_PRAS2_M4PR_Pos 16 +#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR_Pos 0 +#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) +#define MATRIX_PRAS3_M1PR_Pos 4 +#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) +#define MATRIX_PRAS3_M2PR_Pos 8 +#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) +#define MATRIX_PRAS3_M3PR_Pos 12 +#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) +#define MATRIX_PRAS3_M4PR_Pos 16 +#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR_Pos 0 +#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) +#define MATRIX_PRAS4_M1PR_Pos 4 +#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) +#define MATRIX_PRAS4_M2PR_Pos 8 +#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) +#define MATRIX_PRAS4_M3PR_Pos 12 +#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) +#define MATRIX_PRAS4_M4PR_Pos 16 +#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ +#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3S_MATRIX_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/pdc.h b/zephyr/ports/asf/sam3s/include/component/pdc.h new file mode 100644 index 0000000..951f428 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/pdc.h @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PDC_COMPONENT_ +#define _SAM3S_PDC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_PDC Peripheral DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pdc hardware registers */ +typedef struct { + __IO uint32_t PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */ + __IO uint32_t PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */ + __IO uint32_t PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */ + __IO uint32_t PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */ + __IO uint32_t PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */ + __IO uint32_t PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */ + __IO uint32_t PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */ + __IO uint32_t PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */ + __O uint32_t PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */ + __I uint32_t PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */ +} Pdc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */ +#define PERIPH_RPR_RXPTR_Pos 0 +#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ +#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) +/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */ +#define PERIPH_RCR_RXCTR_Pos 0 +#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ +#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) +/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */ +#define PERIPH_TPR_TXPTR_Pos 0 +#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ +#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) +/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */ +#define PERIPH_TCR_TXCTR_Pos 0 +#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ +#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) +/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */ +#define PERIPH_RNPR_RXNPTR_Pos 0 +#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ +#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) +/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */ +#define PERIPH_RNCR_RXNCTR_Pos 0 +#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ +#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) +/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */ +#define PERIPH_TNPR_TXNPTR_Pos 0 +#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ +#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) +/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */ +#define PERIPH_TNCR_TXNCTR_Pos 0 +#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ +#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) +/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */ +#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ +#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ +#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ +#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ +/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */ +#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ +#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_PDC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/pio.h b/zephyr/ports/asf/sam3s/include/component/pio.h new file mode 100644 index 0000000..c763715 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/pio.h @@ -0,0 +1,1571 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PIO_COMPONENT_ +#define _SAM3S_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[2]; + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __IO uint32_t PIO_RPR; /**< \brief (Pio Offset: 0x104) Receive Pointer Register */ + __IO uint32_t PIO_RCR; /**< \brief (Pio Offset: 0x108) Receive Counter Register */ + __I uint32_t Reserved13[2]; + __IO uint32_t PIO_RNPR; /**< \brief (Pio Offset: 0x114) Receive Next Pointer Register */ + __IO uint32_t PIO_RNCR; /**< \brief (Pio Offset: 0x118) Receive Next Counter Register */ + __I uint32_t Reserved14[2]; + __O uint32_t PIO_PTCR; /**< \brief (Pio Offset: 0x124) Transfer Control Register */ + __I uint32_t PIO_PTSR; /**< \brief (Pio Offset: 0x128) Transfer Status Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY. */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_RPR : (PIO Offset: 0x104) Receive Pointer Register -------- */ +#define PIO_RPR_RXPTR_Pos 0 +#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */ +#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos))) +/* -------- PIO_RCR : (PIO Offset: 0x108) Receive Counter Register -------- */ +#define PIO_RCR_RXCTR_Pos 0 +#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */ +#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos))) +/* -------- PIO_RNPR : (PIO Offset: 0x114) Receive Next Pointer Register -------- */ +#define PIO_RNPR_RXNPTR_Pos 0 +#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */ +#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos))) +/* -------- PIO_RNCR : (PIO Offset: 0x118) Receive Next Counter Register -------- */ +#define PIO_RNCR_RXNCTR_Pos 0 +#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */ +#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos))) +/* -------- PIO_PTCR : (PIO Offset: 0x124) Transfer Control Register -------- */ +#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */ +#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */ +#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */ +#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */ +/* -------- PIO_PTSR : (PIO Offset: 0x128) Transfer Status Register -------- */ +#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */ +#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_PIO_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/pmc.h b/zephyr/ports/asf/sam3s/include/component/pmc.h new file mode 100644 index 0000000..f899663 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/pmc.h @@ -0,0 +1,377 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PMC_COMPONENT_ +#define _SAM3S_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __I uint32_t Reserved2[1]; + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __I uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __IO uint32_t CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[5]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Start-up Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Start-up Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + __I uint32_t Reserved7[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __I uint32_t Reserved8[1]; + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ +#define CKGR_PLLBR_DIVB_Pos 0 +#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ +#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) +#define CKGR_PLLBR_PLLBCOUNT_Pos 8 +#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ +#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) +#define CKGR_PLLBR_MULB_Pos 16 +#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ +#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ +#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ +#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Start-up Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Start-up Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Start-up Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Start-up Input Polarityx */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ + +/*@}*/ + + +#endif /* _SAM3S_PMC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/pwm.h b/zephyr/ports/asf/sam3s/include/component/pwm.h new file mode 100644 index 0000000..48d8d7f --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/pwm.h @@ -0,0 +1,547 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PWM_COMPONENT_ +#define _SAM3S_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved3[11]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[12]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + __I uint32_t Reserved5[7]; + __IO uint32_t PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ + __I uint32_t PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ + __I uint32_t Reserved7[2]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved8[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ +#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ +#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ +#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ +#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ +#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ +#define PWM_TPR_TXPTR_Pos 0 +#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */ +#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos))) +/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ +#define PWM_TCR_TXCTR_Pos 0 +#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */ +#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos))) +/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PWM_TNPR_TXNPTR_Pos 0 +#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */ +#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos))) +/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PWM_TNCR_TXNCTR_Pos 0 +#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */ +#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos))) +/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ +#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ +#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ +#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ +#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ +/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ +#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ +#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) + +/*@}*/ + + +#endif /* _SAM3S_PWM_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/rstc.h b/zephyr/ports/asf/sam3s/include/component/rstc.h new file mode 100644 index 0000000..62eb22d --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/rstc.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_RSTC_COMPONENT_ +#define _SAM3S_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) + +/*@}*/ + + +#endif /* _SAM3S_RSTC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/rtc.h b/zephyr/ports/asf/sam3s/include/component/rtc.h new file mode 100644 index 0000000..012875a --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/rtc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_RTC_COMPONENT_ +#define _SAM3S_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAM3S_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + + +#endif /* _SAM3S_RTC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/rtt.h b/zephyr/ports/asf/sam3s/include/component/rtt.h new file mode 100644 index 0000000..b9dc6b3 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/rtt.h @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_RTT_COMPONENT_ +#define _SAM3S_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAM3S_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ + +/*@}*/ + + +#endif /* _SAM3S_RTT_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/smc.h b/zephyr/ports/asf/sam3s/include/component/smc.h new file mode 100644 index 0000000..b61c3e5 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/smc.h @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SMC_COMPONENT_ +#define _SAM3S_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3S_SMC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/spi.h b/zephyr/ports/asf/sam3s/include/component/spi.h new file mode 100644 index 0000000..1040330 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/spi.h @@ -0,0 +1,228 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SPI_COMPONENT_ +#define _SAM3S_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3S_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[5]; + __IO uint32_t SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ + __IO uint32_t SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ + __IO uint32_t SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ + __I uint32_t SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */ +#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */ +#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */ +#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ +#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ +#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ +#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ +#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ +#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ +#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ +#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ +#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ +#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protect Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protect Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ +/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ +#define SPI_RPR_RXPTR_Pos 0 +#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */ +#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos))) +/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ +#define SPI_RCR_RXCTR_Pos 0 +#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */ +#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos))) +/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ +#define SPI_TPR_TXPTR_Pos 0 +#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */ +#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos))) +/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ +#define SPI_TCR_TXCTR_Pos 0 +#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */ +#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos))) +/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ +#define SPI_RNPR_RXNPTR_Pos 0 +#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */ +#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos))) +/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ +#define SPI_RNCR_RXNCTR_Pos 0 +#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */ +#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos))) +/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SPI_TNPR_TXNPTR_Pos 0 +#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */ +#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos))) +/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SPI_TNCR_TXNCTR_Pos 0 +#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */ +#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos))) +/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ +#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ +#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ +#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ +#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ +/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ +#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ +#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_SPI_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/ssc.h b/zephyr/ports/asf/sam3s/include/component/ssc.h new file mode 100644 index 0000000..97d1fec --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/ssc.h @@ -0,0 +1,343 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SSC_COMPONENT_ +#define _SAM3S_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ + __I uint32_t Reserved4[5]; + __IO uint32_t SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ + __IO uint32_t SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ + __IO uint32_t SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ + __I uint32_t SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, RF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, RF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, RF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */ +#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */ +#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ +#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ +#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ +#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ +#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ +#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ +#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ +#define SSC_RPR_RXPTR_Pos 0 +#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */ +#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos))) +/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ +#define SSC_RCR_RXCTR_Pos 0 +#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */ +#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos))) +/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ +#define SSC_TPR_TXPTR_Pos 0 +#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */ +#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos))) +/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ +#define SSC_TCR_TXCTR_Pos 0 +#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */ +#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos))) +/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ +#define SSC_RNPR_RXNPTR_Pos 0 +#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */ +#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos))) +/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ +#define SSC_RNCR_RXNCTR_Pos 0 +#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */ +#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos))) +/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SSC_TNPR_TXNPTR_Pos 0 +#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */ +#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos))) +/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SSC_TNCR_TXNCTR_Pos 0 +#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */ +#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos))) +/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ +#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ +#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ +#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ +#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ +/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ +#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ +#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_SSC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/supc.h b/zephyr/ports/asf/sam3s/include/component/supc.h new file mode 100644 index 0000000..94332e3 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/supc.h @@ -0,0 +1,286 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SUPC_COMPONENT_ +#define _SAM3S_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3S_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used) */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) internal voltage regulator is used */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake-up Input Enable 14 */ +#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake-up Input Enable 15 */ +#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 */ +#define SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 1 */ +#define SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 2 */ +#define SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 3 */ +#define SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 4 */ +#define SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 5 */ +#define SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 6 */ +#define SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 7 */ +#define SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 8 */ +#define SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 9 */ +#define SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 10 */ +#define SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 11 */ +#define SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 12 */ +#define SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 13 */ +#define SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake-up Input Type 14 */ +#define SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake-up Input Type 15 */ +#define SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ +#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ +#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. */ + +/*@}*/ + + +#endif /* _SAM3S_SUPC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/tc.h b/zephyr/ports/asf/sam3s/include/component/tc.h new file mode 100644 index 0000000..bc235d2 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/tc.h @@ -0,0 +1,323 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_TC_COMPONENT_ +#define _SAM3S_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAM3S_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t Reserved1[1]; + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ +#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAM3S_TC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/twi.h b/zephyr/ports/asf/sam3s/include/component/twi.h new file mode 100644 index 0000000..6041d97 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/twi.h @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_TWI_COMPONENT_ +#define _SAM3S_TWI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3S_TWI Two-wire Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twi hardware registers */ +typedef struct { + __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + __I uint32_t Reserved2[50]; + __IO uint32_t TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ + __IO uint32_t TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ + __IO uint32_t TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ + __I uint32_t TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ +} Twi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ(value) ((TWI_MMR_IADRSZ_Msk & ((value) << TWI_MMR_IADRSZ_Pos))) +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */ +#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */ +#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ +#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ +#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ +#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ +#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ +#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ +#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ +#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ +#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ +#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ +#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) +/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ +#define TWI_RPR_RXPTR_Pos 0 +#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ +#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) +/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ +#define TWI_RCR_RXCTR_Pos 0 +#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ +#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) +/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ +#define TWI_TPR_TXPTR_Pos 0 +#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ +#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) +/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ +#define TWI_TCR_TXCTR_Pos 0 +#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ +#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) +/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ +#define TWI_RNPR_RXNPTR_Pos 0 +#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ +#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) +/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ +#define TWI_RNCR_RXNCTR_Pos 0 +#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ +#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) +/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define TWI_TNPR_TXNPTR_Pos 0 +#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ +#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) +/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define TWI_TNCR_TXNCTR_Pos 0 +#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ +#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) +/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ +#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ +#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ +#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ +#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ +/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ +#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ +#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_TWI_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/uart.h b/zephyr/ports/asf/sam3s/include/component/uart.h new file mode 100644 index 0000000..8396f12 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/uart.h @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_UART_COMPONENT_ +#define _SAM3S_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAM3S_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ + __IO uint32_t UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ + __IO uint32_t UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ + __I uint32_t UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No Parity */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ +#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ +#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ +#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ +#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ +#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ +#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */ +#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ +#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ +#define UART_RPR_RXPTR_Pos 0 +#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */ +#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) +/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ +#define UART_RCR_RXCTR_Pos 0 +#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */ +#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) +/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ +#define UART_TPR_TXPTR_Pos 0 +#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */ +#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) +/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ +#define UART_TCR_TXCTR_Pos 0 +#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */ +#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) +/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ +#define UART_RNPR_RXNPTR_Pos 0 +#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */ +#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) +/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ +#define UART_RNCR_RXNCTR_Pos 0 +#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */ +#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) +/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define UART_TNPR_TXNPTR_Pos 0 +#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */ +#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) +/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define UART_TNCR_TXNCTR_Pos 0 +#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */ +#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) +/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ +#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ +#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ +#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ +#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ +/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ +#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ +#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_UART_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/udp.h b/zephyr/ports/asf/sam3s/include/component/udp.h new file mode 100644 index 0000000..18e09f6 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/udp.h @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_UDP_COMPONENT_ +#define _SAM3S_UDP_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Device Port */ +/* ============================================================================= */ +/** \addtogroup SAM3S_UDP USB Device Port */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Udp hardware registers */ +typedef struct { + __I uint32_t UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ + __IO uint32_t UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ + __IO uint32_t UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ + __I uint32_t Reserved1[1]; + __O uint32_t UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ + __O uint32_t UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ + __I uint32_t UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ + __I uint32_t UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ + __O uint32_t UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */ + __IO uint32_t UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ +} Udp; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ +#define UDP_FRM_NUM_FRM_NUM_Pos 0 +#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ +#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ +#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ +/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ +#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ +#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */ +#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ +#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */ +#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ +#define UDP_FADDR_FADD_Pos 0 +#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ +#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) +#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ +#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ +#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ +#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ +#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ +#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ +#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ +#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ +#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ +#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ +#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ +#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */ +#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ +#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ +#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ +#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ +#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ +#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ +#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ +#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ +#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ +#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ +#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ +#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ +#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */ +#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ +#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ +/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ +#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ +#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ +#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ +#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ +#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ +#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ +#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ +#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ +#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ +#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ +#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */ +#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ +#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ +#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ +/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ +#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ +#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ +#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ +#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ +#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ +#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ +#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ +#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ +#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ +#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */ +#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ +#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ +#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ +#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ +#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ +#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */ +#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ +#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ +#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ +/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ +#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ +#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ +#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ +#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ +#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ +#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ +#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ +#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ +/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */ +#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ +#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ +#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */ +#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent */ +#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ +#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ +#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ +#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ +#define UDP_CSR_EPTYPE_Pos 8 +#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ +#define UDP_CSR_EPTYPE(value) ((UDP_CSR_EPTYPE_Msk & ((value) << UDP_CSR_EPTYPE_Pos))) +#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ +#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ +#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ +#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ +#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ +#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ +#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ +#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ +#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ +#define UDP_CSR_RXBYTECNT_Pos 16 +#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ +#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) +#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) A CRC error has been detected in an isochronous transfer */ +/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */ +#define UDP_FDR_FIFO_DATA_Pos 0 +#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */ +#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos))) +/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ +#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ +#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */ + +/*@}*/ + + +#endif /* _SAM3S_UDP_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/usart.h b/zephyr/ports/asf/sam3s/include/component/usart.h new file mode 100644 index 0000000..0ea4f01 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/usart.h @@ -0,0 +1,371 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_USART_COMPONENT_ +#define _SAM3S_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAM3S_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + __I uint32_t Reserved3[36]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protect Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protect Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0x00FC) Version Register */ + __IO uint32_t US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ + __IO uint32_t US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ + __IO uint32_t US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ + __I uint32_t US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) Inverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max Number of Repetitions Reached Interrupt Disable */ +#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max Number of Repetitions Reached Interrupt Mask */ +#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */ +#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max Number of Repetitions Reached */ +#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ +#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0xffffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY. */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */ +/* -------- US_VERSION : (USART Offset: 0x00FC) Version Register -------- */ +#define US_VERSION_VERSION_Pos 0 +#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Hardware Module Version */ +#define US_VERSION_MFN_Pos 16 +#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */ +/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ +#define US_RPR_RXPTR_Pos 0 +#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ +#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) +/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ +#define US_RCR_RXCTR_Pos 0 +#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ +#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) +/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ +#define US_TPR_TXPTR_Pos 0 +#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ +#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) +/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ +#define US_TCR_TXCTR_Pos 0 +#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ +#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) +/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ +#define US_RNPR_RXNPTR_Pos 0 +#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ +#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) +/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ +#define US_RNCR_RXNCTR_Pos 0 +#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ +#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) +/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define US_TNPR_TXNPTR_Pos 0 +#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ +#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) +/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define US_TNCR_TXNCTR_Pos 0 +#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ +#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) +/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ +#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ +#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ +#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ +#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ +/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ +#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ +#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3S_USART_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/component/wdt.h b/zephyr/ports/asf/sam3s/include/component/wdt.h new file mode 100644 index 0000000..cb9fd04 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/component/wdt.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_WDT_COMPONENT_ +#define _SAM3S_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAM3S_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password. */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + + +#endif /* _SAM3S_WDT_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/acc.h b/zephyr/ports/asf/sam3s/include/instance/acc.h new file mode 100644 index 0000000..fe0d979 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/acc.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_ACC_INSTANCE_ +#define _SAM3S_ACC_INSTANCE_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ACC_CR (0x40040000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (0x40040004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (0x40040030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (0x40040094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ + #define REG_ACC_WPSR (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +#else + #define REG_ACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ + #define REG_ACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_ACC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/adc.h b/zephyr/ports/asf/sam3s/include/instance/adc.h new file mode 100644 index 0000000..1375968 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/adc.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_ADC_INSTANCE_ +#define _SAM3S_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */ + #define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */ + #define REG_ADC_SEQR (0x40038008U) /**< \brief (ADC) Channel Sequence Register */ + #define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */ + #define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */ + #define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */ + #define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */ + #define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ + #define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ + #define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ + #define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */ + #define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */ + #define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */ + #define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */ + #define REG_ADC_CGR (0x40038048U) /**< \brief (ADC) Channel Gain Register */ + #define REG_ADC_COR (0x4003804CU) /**< \brief (ADC) Channel Offset Register */ + #define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */ + #define REG_ADC_ACR (0x40038094U) /**< \brief (ADC) Analog Control Register */ + #define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ + #define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ + #define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */ + #define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */ + #define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ + #define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ + #define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */ + #define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */ +#else + #define REG_ADC_CR (*(__O uint32_t*)0x40038000U) /**< \brief (ADC) Control Register */ + #define REG_ADC_MR (*(__IO uint32_t*)0x40038004U) /**< \brief (ADC) Mode Register */ + #define REG_ADC_SEQR (*(__IO uint32_t*)0x40038008U) /**< \brief (ADC) Channel Sequence Register */ + #define REG_ADC_CHER (*(__O uint32_t*)0x40038010U) /**< \brief (ADC) Channel Enable Register */ + #define REG_ADC_CHDR (*(__O uint32_t*)0x40038014U) /**< \brief (ADC) Channel Disable Register */ + #define REG_ADC_CHSR (*(__I uint32_t*)0x40038018U) /**< \brief (ADC) Channel Status Register */ + #define REG_ADC_LCDR (*(__I uint32_t*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */ + #define REG_ADC_IER (*(__O uint32_t*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ + #define REG_ADC_IDR (*(__O uint32_t*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ + #define REG_ADC_IMR (*(__I uint32_t*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ + #define REG_ADC_ISR (*(__I uint32_t*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */ + #define REG_ADC_OVER (*(__I uint32_t*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */ + #define REG_ADC_EMR (*(__IO uint32_t*)0x40038040U) /**< \brief (ADC) Extended Mode Register */ + #define REG_ADC_CWR (*(__IO uint32_t*)0x40038044U) /**< \brief (ADC) Compare Window Register */ + #define REG_ADC_CGR (*(__IO uint32_t*)0x40038048U) /**< \brief (ADC) Channel Gain Register */ + #define REG_ADC_COR (*(__IO uint32_t*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */ + #define REG_ADC_CDR (*(__I uint32_t*)0x40038050U) /**< \brief (ADC) Channel Data Register */ + #define REG_ADC_ACR (*(__IO uint32_t*)0x40038094U) /**< \brief (ADC) Analog Control Register */ + #define REG_ADC_WPMR (*(__IO uint32_t*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ + #define REG_ADC_WPSR (*(__I uint32_t*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ + #define REG_ADC_RPR (*(__IO uint32_t*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */ + #define REG_ADC_RCR (*(__IO uint32_t*)0x40038104U) /**< \brief (ADC) Receive Counter Register */ + #define REG_ADC_RNPR (*(__IO uint32_t*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ + #define REG_ADC_RNCR (*(__IO uint32_t*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ + #define REG_ADC_PTCR (*(__O uint32_t*)0x40038120U) /**< \brief (ADC) Transfer Control Register */ + #define REG_ADC_PTSR (*(__I uint32_t*)0x40038124U) /**< \brief (ADC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_ADC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/chipid.h b/zephyr/ports/asf/sam3s/include/instance/chipid.h new file mode 100644 index 0000000..ffef6b3 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/chipid.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_CHIPID_INSTANCE_ +#define _SAM3S_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else + #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_CHIPID_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/crccu.h b/zephyr/ports/asf/sam3s/include/instance/crccu.h new file mode 100644 index 0000000..e548b4f --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/crccu.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_CRCCU_INSTANCE_ +#define _SAM3S_CRCCU_INSTANCE_ + +/* ========== Register definition for CRCCU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ + #define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ + #define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ + #define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ + #define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ + #define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ + #define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ + #define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ + #define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ + #define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ + #define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ + #define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ + #define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ + #define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ + #define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +#else + #define REG_CRCCU_DSCR (*(__IO uint32_t*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ + #define REG_CRCCU_DMA_EN (*(__O uint32_t*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ + #define REG_CRCCU_DMA_DIS (*(__O uint32_t*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ + #define REG_CRCCU_DMA_SR (*(__I uint32_t*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ + #define REG_CRCCU_DMA_IER (*(__O uint32_t*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ + #define REG_CRCCU_DMA_IDR (*(__O uint32_t*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ + #define REG_CRCCU_DMA_IMR (*(__I uint32_t*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ + #define REG_CRCCU_DMA_ISR (*(__I uint32_t*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ + #define REG_CRCCU_CR (*(__O uint32_t*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ + #define REG_CRCCU_MR (*(__IO uint32_t*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ + #define REG_CRCCU_SR (*(__I uint32_t*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ + #define REG_CRCCU_IER (*(__O uint32_t*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ + #define REG_CRCCU_IDR (*(__O uint32_t*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ + #define REG_CRCCU_IMR (*(__I uint32_t*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ + #define REG_CRCCU_ISR (*(__I uint32_t*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_CRCCU_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/dacc.h b/zephyr/ports/asf/sam3s/include/instance/dacc.h new file mode 100644 index 0000000..07a4e37 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/dacc.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_DACC_INSTANCE_ +#define _SAM3S_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_DACC_CR (0x4003C000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (0x4003C004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_CHER (0x4003C010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (0x4003C014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (0x4003C018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (0x4003C020U) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (0x4003C094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ + #define REG_DACC_WPSR (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ + #define REG_DACC_TPR (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ + #define REG_DACC_TCR (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ + #define REG_DACC_TNPR (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ + #define REG_DACC_TNCR (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ + #define REG_DACC_PTCR (0x4003C120U) /**< \brief (DACC) Transfer Control Register */ + #define REG_DACC_PTSR (0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +#else + #define REG_DACC_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_CHER (*(__O uint32_t*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (*(__O uint32_t*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (*(__I uint32_t*)0x4003C018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (*(__O uint32_t*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ + #define REG_DACC_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ + #define REG_DACC_TPR (*(__IO uint32_t*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ + #define REG_DACC_TCR (*(__IO uint32_t*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ + #define REG_DACC_TNPR (*(__IO uint32_t*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ + #define REG_DACC_TNCR (*(__IO uint32_t*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ + #define REG_DACC_PTCR (*(__O uint32_t*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */ + #define REG_DACC_PTSR (*(__I uint32_t*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_DACC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/efc.h b/zephyr/ports/asf/sam3s/include/instance/efc.h new file mode 100644 index 0000000..35d2de0 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/efc.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_EFC_INSTANCE_ +#define _SAM3S_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +#else + #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (*(__O uint32_t*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (*(__I uint32_t*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (*(__I uint32_t*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_EFC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/gpbr.h b/zephyr/ports/asf/sam3s/include/instance/gpbr.h new file mode 100644 index 0000000..06264da --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/gpbr.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_GPBR_INSTANCE_ +#define _SAM3S_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ +#else + #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_GPBR_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/hsmci.h b/zephyr/ports/asf/sam3s/include/instance/hsmci.h new file mode 100644 index 0000000..af95f6e --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/hsmci.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_HSMCI_INSTANCE_ +#define _SAM3S_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_RPR (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ + #define REG_HSMCI_RCR (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ + #define REG_HSMCI_TPR (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ + #define REG_HSMCI_TCR (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ + #define REG_HSMCI_RNPR (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ + #define REG_HSMCI_RNCR (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ + #define REG_HSMCI_TNPR (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ + #define REG_HSMCI_TNCR (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ + #define REG_HSMCI_PTCR (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ + #define REG_HSMCI_PTSR (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ + #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else + #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_RPR (*(__IO uint32_t*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ + #define REG_HSMCI_RCR (*(__IO uint32_t*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ + #define REG_HSMCI_TPR (*(__IO uint32_t*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ + #define REG_HSMCI_TCR (*(__IO uint32_t*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ + #define REG_HSMCI_RNPR (*(__IO uint32_t*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ + #define REG_HSMCI_RNCR (*(__IO uint32_t*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ + #define REG_HSMCI_TNPR (*(__IO uint32_t*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ + #define REG_HSMCI_TNCR (*(__IO uint32_t*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ + #define REG_HSMCI_PTCR (*(__O uint32_t*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ + #define REG_HSMCI_PTSR (*(__I uint32_t*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ + #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_HSMCI_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/matrix.h b/zephyr/ports/asf/sam3s/include/instance/matrix.h new file mode 100644 index 0000000..336e84d --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/matrix.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_MATRIX_INSTANCE_ +#define _SAM3S_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ + #define REG_CCFG_SMCNFCS (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ + #define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ + #define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else + #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ + #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ + #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ + #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_MATRIX_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/pioa.h b/zephyr/ports/asf/sam3s/include/instance/pioa.h new file mode 100644 index 0000000..7396961 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/pioa.h @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PIOA_INSTANCE_ +#define _SAM3S_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ + #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ + #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ + #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ + #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ + #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_RPR (0x400E0F04U) /**< \brief (PIOA) Receive Pointer Register */ + #define REG_PIOA_RCR (0x400E0F08U) /**< \brief (PIOA) Receive Counter Register */ + #define REG_PIOA_RNPR (0x400E0F14U) /**< \brief (PIOA) Receive Next Pointer Register */ + #define REG_PIOA_RNCR (0x400E0F18U) /**< \brief (PIOA) Receive Next Counter Register */ + #define REG_PIOA_PTCR (0x400E0F24U) /**< \brief (PIOA) Transfer Control Register */ + #define REG_PIOA_PTSR (0x400E0F28U) /**< \brief (PIOA) Transfer Status Register */ +#else + #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ + #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ + #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ + #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ + #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ + #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_RPR (*(__IO uint32_t*)0x400E0F04U) /**< \brief (PIOA) Receive Pointer Register */ + #define REG_PIOA_RCR (*(__IO uint32_t*)0x400E0F08U) /**< \brief (PIOA) Receive Counter Register */ + #define REG_PIOA_RNPR (*(__IO uint32_t*)0x400E0F14U) /**< \brief (PIOA) Receive Next Pointer Register */ + #define REG_PIOA_RNCR (*(__IO uint32_t*)0x400E0F18U) /**< \brief (PIOA) Receive Next Counter Register */ + #define REG_PIOA_PTCR (*(__O uint32_t*)0x400E0F24U) /**< \brief (PIOA) Transfer Control Register */ + #define REG_PIOA_PTSR (*(__I uint32_t*)0x400E0F28U) /**< \brief (PIOA) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_PIOA_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/piob.h b/zephyr/ports/asf/sam3s/include/instance/piob.h new file mode 100644 index 0000000..f10ea05 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/piob.h @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PIOB_INSTANCE_ +#define _SAM3S_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ + #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ + #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ + #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ + #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ + #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#else + #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ + #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ + #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ + #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ + #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ + #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_PIOB_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/pioc.h b/zephyr/ports/asf/sam3s/include/instance/pioc.h new file mode 100644 index 0000000..e25a29c --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/pioc.h @@ -0,0 +1,130 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PIOC_INSTANCE_ +#define _SAM3S_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ + #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ + #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ + #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ + #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ + #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ +#else + #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ + #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ + #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ + #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ + #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ + #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_PIOC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/pmc.h b/zephyr/ports/asf/sam3s/include/instance/pmc.h new file mode 100644 index 0000000..f7b698a --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/pmc.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PMC_INSTANCE_ +#define _SAM3S_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */ + #define REG_CKGR_PLLBR (0x400E042CU) /**< \brief (PMC) PLLB Register */ + #define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Start-up Mode Register */ + #define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Start-up Polarity Register */ + #define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ + #define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ + #define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +#else + #define REG_PMC_SCER (*(__O uint32_t*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (*(__I uint32_t*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0428U) /**< \brief (PMC) PLLA Register */ + #define REG_CKGR_PLLBR (*(__IO uint32_t*)0x400E042CU) /**< \brief (PMC) PLLB Register */ + #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0430U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (*(__IO uint32_t*)0x400E0438U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (*(__O uint32_t*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (*(__O uint32_t*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (*(__I uint32_t*)0x400E0468U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (*(__I uint32_t*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0470U) /**< \brief (PMC) Fast Start-up Mode Register */ + #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0474U) /**< \brief (PMC) Fast Start-up Polarity Register */ + #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ + #define REG_PMC_WPSR (*(__I uint32_t*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ + #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_PMC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/pwm.h b/zephyr/ports/asf/sam3s/include/instance/pwm.h new file mode 100644 index 0000000..184f9e6 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/pwm.h @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_PWM_INSTANCE_ +#define _SAM3S_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM_CLK (0x40020000U) /**< \brief (PWM) PWM Clock Register */ + #define REG_PWM_ENA (0x40020004U) /**< \brief (PWM) PWM Enable Register */ + #define REG_PWM_DIS (0x40020008U) /**< \brief (PWM) PWM Disable Register */ + #define REG_PWM_SR (0x4002000CU) /**< \brief (PWM) PWM Status Register */ + #define REG_PWM_IER1 (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ + #define REG_PWM_IDR1 (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ + #define REG_PWM_IMR1 (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ + #define REG_PWM_ISR1 (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ + #define REG_PWM_SCM (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ + #define REG_PWM_SCUC (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ + #define REG_PWM_SCUP (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ + #define REG_PWM_SCUPUPD (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ + #define REG_PWM_IER2 (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ + #define REG_PWM_IDR2 (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ + #define REG_PWM_IMR2 (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ + #define REG_PWM_ISR2 (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ + #define REG_PWM_OOV (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ + #define REG_PWM_OS (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ + #define REG_PWM_OSS (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ + #define REG_PWM_OSC (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ + #define REG_PWM_OSSUPD (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ + #define REG_PWM_OSCUPD (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ + #define REG_PWM_FMR (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ + #define REG_PWM_FSR (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ + #define REG_PWM_FCR (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ + #define REG_PWM_FPV (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ + #define REG_PWM_FPE (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ + #define REG_PWM_ELMR (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ + #define REG_PWM_SMMR (0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ + #define REG_PWM_WPCR (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ + #define REG_PWM_WPSR (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ + #define REG_PWM_TPR (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ + #define REG_PWM_TCR (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ + #define REG_PWM_TNPR (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ + #define REG_PWM_TNCR (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ + #define REG_PWM_PTCR (0x40020120U) /**< \brief (PWM) Transfer Control Register */ + #define REG_PWM_PTSR (0x40020124U) /**< \brief (PWM) Transfer Status Register */ + #define REG_PWM_CMPV0 (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ + #define REG_PWM_CMPVUPD0 (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ + #define REG_PWM_CMPM0 (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ + #define REG_PWM_CMPMUPD0 (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ + #define REG_PWM_CMPV1 (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ + #define REG_PWM_CMPVUPD1 (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ + #define REG_PWM_CMPM1 (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ + #define REG_PWM_CMPMUPD1 (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ + #define REG_PWM_CMPV2 (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ + #define REG_PWM_CMPVUPD2 (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ + #define REG_PWM_CMPM2 (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ + #define REG_PWM_CMPMUPD2 (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ + #define REG_PWM_CMPV3 (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ + #define REG_PWM_CMPVUPD3 (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ + #define REG_PWM_CMPM3 (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ + #define REG_PWM_CMPMUPD3 (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ + #define REG_PWM_CMPV4 (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ + #define REG_PWM_CMPVUPD4 (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ + #define REG_PWM_CMPM4 (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ + #define REG_PWM_CMPMUPD4 (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ + #define REG_PWM_CMPV5 (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ + #define REG_PWM_CMPVUPD5 (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ + #define REG_PWM_CMPM5 (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ + #define REG_PWM_CMPMUPD5 (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ + #define REG_PWM_CMPV6 (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ + #define REG_PWM_CMPVUPD6 (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ + #define REG_PWM_CMPM6 (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ + #define REG_PWM_CMPMUPD6 (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ + #define REG_PWM_CMPV7 (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ + #define REG_PWM_CMPVUPD7 (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ + #define REG_PWM_CMPM7 (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ + #define REG_PWM_CMPMUPD7 (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ + #define REG_PWM_CMR0 (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM_CDTY0 (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM_CDTYUPD0 (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM_CPRD0 (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM_CPRDUPD0 (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM_CCNT0 (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM_DT0 (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM_DTUPD0 (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM_CMR1 (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM_CDTY1 (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM_CDTYUPD1 (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM_CPRD1 (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM_CPRDUPD1 (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM_CCNT1 (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM_DT1 (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM_DTUPD1 (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM_CMR2 (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM_CDTY2 (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM_CDTYUPD2 (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM_CPRD2 (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM_CPRDUPD2 (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM_CCNT2 (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM_DT2 (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM_DTUPD2 (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM_CMR3 (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM_CDTY3 (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM_CDTYUPD3 (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM_CPRD3 (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM_CPRDUPD3 (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM_CCNT3 (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM_DT3 (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM_DTUPD3 (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#else + #define REG_PWM_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM) PWM Clock Register */ + #define REG_PWM_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM) PWM Enable Register */ + #define REG_PWM_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM) PWM Disable Register */ + #define REG_PWM_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM) PWM Status Register */ + #define REG_PWM_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ + #define REG_PWM_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ + #define REG_PWM_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ + #define REG_PWM_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ + #define REG_PWM_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ + #define REG_PWM_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ + #define REG_PWM_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ + #define REG_PWM_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ + #define REG_PWM_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ + #define REG_PWM_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ + #define REG_PWM_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ + #define REG_PWM_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ + #define REG_PWM_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ + #define REG_PWM_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ + #define REG_PWM_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ + #define REG_PWM_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ + #define REG_PWM_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ + #define REG_PWM_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ + #define REG_PWM_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ + #define REG_PWM_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ + #define REG_PWM_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ + #define REG_PWM_FPV (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ + #define REG_PWM_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ + #define REG_PWM_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ + #define REG_PWM_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */ + #define REG_PWM_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ + #define REG_PWM_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ + #define REG_PWM_TPR (*(__IO uint32_t*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ + #define REG_PWM_TCR (*(__IO uint32_t*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ + #define REG_PWM_TNPR (*(__IO uint32_t*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ + #define REG_PWM_TNCR (*(__IO uint32_t*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ + #define REG_PWM_PTCR (*(__O uint32_t*)0x40020120U) /**< \brief (PWM) Transfer Control Register */ + #define REG_PWM_PTSR (*(__I uint32_t*)0x40020124U) /**< \brief (PWM) Transfer Status Register */ + #define REG_PWM_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ + #define REG_PWM_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ + #define REG_PWM_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ + #define REG_PWM_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ + #define REG_PWM_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ + #define REG_PWM_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ + #define REG_PWM_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ + #define REG_PWM_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ + #define REG_PWM_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ + #define REG_PWM_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ + #define REG_PWM_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ + #define REG_PWM_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ + #define REG_PWM_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ + #define REG_PWM_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ + #define REG_PWM_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ + #define REG_PWM_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ + #define REG_PWM_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ + #define REG_PWM_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ + #define REG_PWM_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ + #define REG_PWM_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ + #define REG_PWM_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ + #define REG_PWM_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ + #define REG_PWM_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ + #define REG_PWM_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ + #define REG_PWM_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ + #define REG_PWM_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ + #define REG_PWM_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ + #define REG_PWM_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ + #define REG_PWM_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ + #define REG_PWM_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ + #define REG_PWM_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ + #define REG_PWM_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ + #define REG_PWM_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_PWM_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/rstc.h b/zephyr/ports/asf/sam3s/include/instance/rstc.h new file mode 100644 index 0000000..7bc5731 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/rstc.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_RSTC_INSTANCE_ +#define _SAM3S_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */ +#else + #define REG_RSTC_CR (*(__O uint32_t*)0x400E1400U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (*(__I uint32_t*)0x400E1404U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1408U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_RSTC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/rtc.h b/zephyr/ports/asf/sam3s/include/instance/rtc.h new file mode 100644 index 0000000..ba84d00 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/rtc.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_RTC_INSTANCE_ +#define _SAM3S_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +#else + #define REG_RTC_CR (*(__IO uint32_t*)0x400E1460U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (*(__IO uint32_t*)0x400E1464U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1468U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (*(__IO uint32_t*)0x400E146CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (*(__I uint32_t*)0x400E1478U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (*(__O uint32_t*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (*(__O uint32_t*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (*(__O uint32_t*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (*(__I uint32_t*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (*(__I uint32_t*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_RTC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/rtt.h b/zephyr/ports/asf/sam3s/include/instance/rtt.h new file mode 100644 index 0000000..2da5c9d --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/rtt.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_RTT_INSTANCE_ +#define _SAM3S_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */ +#else + #define REG_RTT_MR (*(__IO uint32_t*)0x400E1430U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (*(__IO uint32_t*)0x400E1434U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (*(__I uint32_t*)0x400E1438U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (*(__I uint32_t*)0x400E143CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_RTT_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/smc.h b/zephyr/ports/asf/sam3s/include/instance/smc.h new file mode 100644 index 0000000..41fc98d --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/smc.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SMC_INSTANCE_ +#define _SAM3S_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SMC_SETUP0 (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ + #define REG_SMC_WPSR (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +#else + #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (*(__IO uint32_t*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (*(__IO uint32_t*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (*(__IO uint32_t*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (*(__IO uint32_t*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (*(__IO uint32_t*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (*(__O uint32_t*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (*(__O uint32_t*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (*(__IO uint32_t*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ + #define REG_SMC_WPSR (*(__I uint32_t*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_SMC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/spi.h b/zephyr/ports/asf/sam3s/include/instance/spi.h new file mode 100644 index 0000000..ebf9566 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/spi.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SPI_INSTANCE_ +#define _SAM3S_SPI_INSTANCE_ + +/* ========== Register definition for SPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */ + #define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */ + #define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */ + #define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */ + #define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */ + #define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ + #define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ + #define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ + #define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */ + #define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ + #define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ + #define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */ + #define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */ + #define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ + #define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ + #define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ + #define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ + #define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ + #define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ + #define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */ + #define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */ +#else + #define REG_SPI_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI) Control Register */ + #define REG_SPI_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI) Mode Register */ + #define REG_SPI_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI) Receive Data Register */ + #define REG_SPI_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */ + #define REG_SPI_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI) Status Register */ + #define REG_SPI_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ + #define REG_SPI_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ + #define REG_SPI_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ + #define REG_SPI_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI) Chip Select Register */ + #define REG_SPI_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ + #define REG_SPI_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ + #define REG_SPI_RPR (*(__IO uint32_t*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */ + #define REG_SPI_RCR (*(__IO uint32_t*)0x40008104U) /**< \brief (SPI) Receive Counter Register */ + #define REG_SPI_TPR (*(__IO uint32_t*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ + #define REG_SPI_TCR (*(__IO uint32_t*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ + #define REG_SPI_RNPR (*(__IO uint32_t*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ + #define REG_SPI_RNCR (*(__IO uint32_t*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ + #define REG_SPI_TNPR (*(__IO uint32_t*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ + #define REG_SPI_TNCR (*(__IO uint32_t*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ + #define REG_SPI_PTCR (*(__O uint32_t*)0x40008120U) /**< \brief (SPI) Transfer Control Register */ + #define REG_SPI_PTSR (*(__I uint32_t*)0x40008124U) /**< \brief (SPI) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_SPI_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/ssc.h b/zephyr/ports/asf/sam3s/include/instance/ssc.h new file mode 100644 index 0000000..22441d5 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/ssc.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SSC_INSTANCE_ +#define _SAM3S_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ + #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ + #define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */ + #define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */ + #define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ + #define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ + #define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ + #define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ + #define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ + #define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ + #define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */ + #define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */ +#else + #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ + #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ + #define REG_SSC_RPR (*(__IO uint32_t*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */ + #define REG_SSC_RCR (*(__IO uint32_t*)0x40004104U) /**< \brief (SSC) Receive Counter Register */ + #define REG_SSC_TPR (*(__IO uint32_t*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ + #define REG_SSC_TCR (*(__IO uint32_t*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ + #define REG_SSC_RNPR (*(__IO uint32_t*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ + #define REG_SSC_RNCR (*(__IO uint32_t*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ + #define REG_SSC_TNPR (*(__IO uint32_t*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ + #define REG_SSC_TNCR (*(__IO uint32_t*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ + #define REG_SSC_PTCR (*(__O uint32_t*)0x40004120U) /**< \brief (SSC) Transfer Control Register */ + #define REG_SSC_PTSR (*(__I uint32_t*)0x40004124U) /**< \brief (SSC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_SSC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/supc.h b/zephyr/ports/asf/sam3s/include/instance/supc.h new file mode 100644 index 0000000..0891f23 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/supc.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_SUPC_INSTANCE_ +#define _SAM3S_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +#else + #define REG_SUPC_CR (*(__O uint32_t*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (*(__I uint32_t*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_SUPC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/tc0.h b/zephyr/ports/asf/sam3s/include/instance/tc0.h new file mode 100644 index 0000000..94f39d6 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/tc0.h @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_TC0_INSTANCE_ +#define _SAM3S_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (0x400100D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#else + #define REG_TC0_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_TC0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/tc1.h b/zephyr/ports/asf/sam3s/include/instance/tc1.h new file mode 100644 index 0000000..2179e26 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/tc1.h @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_TC1_INSTANCE_ +#define _SAM3S_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (0x400140D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#else + #define REG_TC1_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_TC1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/twi0.h b/zephyr/ports/asf/sam3s/include/instance/twi0.h new file mode 100644 index 0000000..e141504 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/twi0.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_TWI0_INSTANCE_ +#define _SAM3S_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWI0_CR (0x40018000U) /**< \brief (TWI0) Control Register */ + #define REG_TWI0_MMR (0x40018004U) /**< \brief (TWI0) Master Mode Register */ + #define REG_TWI0_SMR (0x40018008U) /**< \brief (TWI0) Slave Mode Register */ + #define REG_TWI0_IADR (0x4001800CU) /**< \brief (TWI0) Internal Address Register */ + #define REG_TWI0_CWGR (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ + #define REG_TWI0_SR (0x40018020U) /**< \brief (TWI0) Status Register */ + #define REG_TWI0_IER (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ + #define REG_TWI0_IDR (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ + #define REG_TWI0_IMR (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ + #define REG_TWI0_RHR (0x40018030U) /**< \brief (TWI0) Receive Holding Register */ + #define REG_TWI0_THR (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ + #define REG_TWI0_RPR (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ + #define REG_TWI0_RCR (0x40018104U) /**< \brief (TWI0) Receive Counter Register */ + #define REG_TWI0_TPR (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ + #define REG_TWI0_TCR (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ + #define REG_TWI0_RNPR (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ + #define REG_TWI0_RNCR (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ + #define REG_TWI0_TNPR (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ + #define REG_TWI0_TNCR (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ + #define REG_TWI0_PTCR (0x40018120U) /**< \brief (TWI0) Transfer Control Register */ + #define REG_TWI0_PTSR (0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +#else + #define REG_TWI0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWI0) Control Register */ + #define REG_TWI0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWI0) Master Mode Register */ + #define REG_TWI0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */ + #define REG_TWI0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */ + #define REG_TWI0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ + #define REG_TWI0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWI0) Status Register */ + #define REG_TWI0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ + #define REG_TWI0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ + #define REG_TWI0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ + #define REG_TWI0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */ + #define REG_TWI0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ + #define REG_TWI0_RPR (*(__IO uint32_t*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ + #define REG_TWI0_RCR (*(__IO uint32_t*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */ + #define REG_TWI0_TPR (*(__IO uint32_t*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ + #define REG_TWI0_TCR (*(__IO uint32_t*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ + #define REG_TWI0_RNPR (*(__IO uint32_t*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ + #define REG_TWI0_RNCR (*(__IO uint32_t*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ + #define REG_TWI0_TNPR (*(__IO uint32_t*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ + #define REG_TWI0_TNCR (*(__IO uint32_t*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ + #define REG_TWI0_PTCR (*(__O uint32_t*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */ + #define REG_TWI0_PTSR (*(__I uint32_t*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_TWI0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/twi1.h b/zephyr/ports/asf/sam3s/include/instance/twi1.h new file mode 100644 index 0000000..1b36528 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/twi1.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_TWI1_INSTANCE_ +#define _SAM3S_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWI1_CR (0x4001C000U) /**< \brief (TWI1) Control Register */ + #define REG_TWI1_MMR (0x4001C004U) /**< \brief (TWI1) Master Mode Register */ + #define REG_TWI1_SMR (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ + #define REG_TWI1_IADR (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ + #define REG_TWI1_CWGR (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ + #define REG_TWI1_SR (0x4001C020U) /**< \brief (TWI1) Status Register */ + #define REG_TWI1_IER (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ + #define REG_TWI1_IDR (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ + #define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ + #define REG_TWI1_RHR (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ + #define REG_TWI1_THR (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ + #define REG_TWI1_RPR (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ + #define REG_TWI1_RCR (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ + #define REG_TWI1_TPR (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ + #define REG_TWI1_TCR (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ + #define REG_TWI1_RNPR (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ + #define REG_TWI1_RNCR (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ + #define REG_TWI1_TNPR (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ + #define REG_TWI1_TNCR (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ + #define REG_TWI1_PTCR (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ + #define REG_TWI1_PTSR (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +#else + #define REG_TWI1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWI1) Control Register */ + #define REG_TWI1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */ + #define REG_TWI1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ + #define REG_TWI1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ + #define REG_TWI1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ + #define REG_TWI1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWI1) Status Register */ + #define REG_TWI1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ + #define REG_TWI1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ + #define REG_TWI1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ + #define REG_TWI1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ + #define REG_TWI1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ + #define REG_TWI1_RPR (*(__IO uint32_t*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ + #define REG_TWI1_RCR (*(__IO uint32_t*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ + #define REG_TWI1_TPR (*(__IO uint32_t*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ + #define REG_TWI1_TCR (*(__IO uint32_t*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ + #define REG_TWI1_RNPR (*(__IO uint32_t*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ + #define REG_TWI1_RNCR (*(__IO uint32_t*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ + #define REG_TWI1_TNPR (*(__IO uint32_t*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ + #define REG_TWI1_TNCR (*(__IO uint32_t*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ + #define REG_TWI1_PTCR (*(__O uint32_t*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ + #define REG_TWI1_PTSR (*(__I uint32_t*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_TWI1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/uart0.h b/zephyr/ports/asf/sam3s/include/instance/uart0.h new file mode 100644 index 0000000..0ebc172 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/uart0.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_UART0_INSTANCE_ +#define _SAM3S_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ + #define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */ + #define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ + #define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ + #define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ + #define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ + #define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ + #define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ + #define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */ + #define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +#else + #define REG_UART0_CR (*(__O uint32_t*)0x400E0600U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (*(__IO uint32_t*)0x400E0604U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (*(__O uint32_t*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (*(__O uint32_t*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (*(__I uint32_t*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (*(__I uint32_t*)0x400E0614U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (*(__I uint32_t*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (*(__O uint32_t*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_RPR (*(__IO uint32_t*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ + #define REG_UART0_RCR (*(__IO uint32_t*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */ + #define REG_UART0_TPR (*(__IO uint32_t*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ + #define REG_UART0_TCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ + #define REG_UART0_RNPR (*(__IO uint32_t*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ + #define REG_UART0_RNCR (*(__IO uint32_t*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ + #define REG_UART0_TNPR (*(__IO uint32_t*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ + #define REG_UART0_TNCR (*(__IO uint32_t*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ + #define REG_UART0_PTCR (*(__O uint32_t*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */ + #define REG_UART0_PTSR (*(__I uint32_t*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_UART0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/uart1.h b/zephyr/ports/asf/sam3s/include/instance/uart1.h new file mode 100644 index 0000000..0ea496d --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/uart1.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_UART1_INSTANCE_ +#define _SAM3S_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART1_CR (0x400E0800U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (0x400E0804U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (0x400E0814U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (0x400E0818U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_RPR (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ + #define REG_UART1_RCR (0x400E0904U) /**< \brief (UART1) Receive Counter Register */ + #define REG_UART1_TPR (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ + #define REG_UART1_TCR (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ + #define REG_UART1_RNPR (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ + #define REG_UART1_RNCR (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ + #define REG_UART1_TNPR (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ + #define REG_UART1_TNCR (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ + #define REG_UART1_PTCR (0x400E0920U) /**< \brief (UART1) Transfer Control Register */ + #define REG_UART1_PTSR (0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +#else + #define REG_UART1_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_RPR (*(__IO uint32_t*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ + #define REG_UART1_RCR (*(__IO uint32_t*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */ + #define REG_UART1_TPR (*(__IO uint32_t*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ + #define REG_UART1_TCR (*(__IO uint32_t*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ + #define REG_UART1_RNPR (*(__IO uint32_t*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ + #define REG_UART1_RNCR (*(__IO uint32_t*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ + #define REG_UART1_TNPR (*(__IO uint32_t*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ + #define REG_UART1_TNCR (*(__IO uint32_t*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ + #define REG_UART1_PTCR (*(__O uint32_t*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */ + #define REG_UART1_PTSR (*(__I uint32_t*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_UART1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/udp.h b/zephyr/ports/asf/sam3s/include/instance/udp.h new file mode 100644 index 0000000..ed40469 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/udp.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_UDP_INSTANCE_ +#define _SAM3S_UDP_INSTANCE_ + +/* ========== Register definition for UDP peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UDP_FRM_NUM (0x40034000U) /**< \brief (UDP) Frame Number Register */ + #define REG_UDP_GLB_STAT (0x40034004U) /**< \brief (UDP) Global State Register */ + #define REG_UDP_FADDR (0x40034008U) /**< \brief (UDP) Function Address Register */ + #define REG_UDP_IER (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ + #define REG_UDP_IDR (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ + #define REG_UDP_IMR (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ + #define REG_UDP_ISR (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ + #define REG_UDP_ICR (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ + #define REG_UDP_RST_EP (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ + #define REG_UDP_CSR (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */ + #define REG_UDP_FDR (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */ + #define REG_UDP_TXVC (0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +#else + #define REG_UDP_FRM_NUM (*(__I uint32_t*)0x40034000U) /**< \brief (UDP) Frame Number Register */ + #define REG_UDP_GLB_STAT (*(__IO uint32_t*)0x40034004U) /**< \brief (UDP) Global State Register */ + #define REG_UDP_FADDR (*(__IO uint32_t*)0x40034008U) /**< \brief (UDP) Function Address Register */ + #define REG_UDP_IER (*(__O uint32_t*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ + #define REG_UDP_IDR (*(__O uint32_t*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ + #define REG_UDP_IMR (*(__I uint32_t*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ + #define REG_UDP_ISR (*(__I uint32_t*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ + #define REG_UDP_ICR (*(__O uint32_t*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ + #define REG_UDP_RST_EP (*(__IO uint32_t*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ + #define REG_UDP_CSR (*(__IO uint32_t*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */ + #define REG_UDP_FDR (*(__IO uint32_t*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */ + #define REG_UDP_TXVC (*(__IO uint32_t*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_UDP_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/usart0.h b/zephyr/ports/asf/sam3s/include/instance/usart0.h new file mode 100644 index 0000000..c41a692 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/usart0.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_USART0_INSTANCE_ +#define _SAM3S_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receiver Holding Register */ + #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ + #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ + #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ + #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ + #define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */ + #define REG_USART0_RPR (0x40024100U) /**< \brief (USART0) Receive Pointer Register */ + #define REG_USART0_RCR (0x40024104U) /**< \brief (USART0) Receive Counter Register */ + #define REG_USART0_TPR (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ + #define REG_USART0_TCR (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ + #define REG_USART0_RNPR (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ + #define REG_USART0_RNCR (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ + #define REG_USART0_TNPR (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ + #define REG_USART0_TNCR (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ + #define REG_USART0_PTCR (0x40024120U) /**< \brief (USART0) Transfer Control Register */ + #define REG_USART0_PTSR (0x40024124U) /**< \brief (USART0) Transfer Status Register */ +#else + #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */ + #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ + #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ + #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ + #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ + #define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) /**< \brief (USART0) Version Register */ + #define REG_USART0_RPR (*(__IO uint32_t*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */ + #define REG_USART0_RCR (*(__IO uint32_t*)0x40024104U) /**< \brief (USART0) Receive Counter Register */ + #define REG_USART0_TPR (*(__IO uint32_t*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ + #define REG_USART0_TCR (*(__IO uint32_t*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ + #define REG_USART0_RNPR (*(__IO uint32_t*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ + #define REG_USART0_RNCR (*(__IO uint32_t*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ + #define REG_USART0_TNPR (*(__IO uint32_t*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ + #define REG_USART0_TNCR (*(__IO uint32_t*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ + #define REG_USART0_PTCR (*(__O uint32_t*)0x40024120U) /**< \brief (USART0) Transfer Control Register */ + #define REG_USART0_PTSR (*(__I uint32_t*)0x40024124U) /**< \brief (USART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_USART0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/usart1.h b/zephyr/ports/asf/sam3s/include/instance/usart1.h new file mode 100644 index 0000000..28ac463 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/usart1.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_USART1_INSTANCE_ +#define _SAM3S_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receiver Holding Register */ + #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ + #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ + #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ + #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ + #define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */ + #define REG_USART1_RPR (0x40028100U) /**< \brief (USART1) Receive Pointer Register */ + #define REG_USART1_RCR (0x40028104U) /**< \brief (USART1) Receive Counter Register */ + #define REG_USART1_TPR (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ + #define REG_USART1_TCR (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ + #define REG_USART1_RNPR (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ + #define REG_USART1_RNCR (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ + #define REG_USART1_TNPR (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ + #define REG_USART1_TNCR (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ + #define REG_USART1_PTCR (0x40028120U) /**< \brief (USART1) Transfer Control Register */ + #define REG_USART1_PTSR (0x40028124U) /**< \brief (USART1) Transfer Status Register */ +#else + #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */ + #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ + #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ + #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ + #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ + #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */ + #define REG_USART1_RPR (*(__IO uint32_t*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */ + #define REG_USART1_RCR (*(__IO uint32_t*)0x40028104U) /**< \brief (USART1) Receive Counter Register */ + #define REG_USART1_TPR (*(__IO uint32_t*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ + #define REG_USART1_TCR (*(__IO uint32_t*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ + #define REG_USART1_RNPR (*(__IO uint32_t*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ + #define REG_USART1_RNCR (*(__IO uint32_t*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ + #define REG_USART1_TNPR (*(__IO uint32_t*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ + #define REG_USART1_TNCR (*(__IO uint32_t*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ + #define REG_USART1_PTCR (*(__O uint32_t*)0x40028120U) /**< \brief (USART1) Transfer Control Register */ + #define REG_USART1_PTSR (*(__I uint32_t*)0x40028124U) /**< \brief (USART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_USART1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/instance/wdt.h b/zephyr/ports/asf/sam3s/include/instance/wdt.h new file mode 100644 index 0000000..cab66ce --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/instance/wdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_WDT_INSTANCE_ +#define _SAM3S_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */ +#else + #define REG_WDT_CR (*(__O uint32_t*)0x400E1450U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (*(__IO uint32_t*)0x400E1454U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (*(__I uint32_t*)0x400E1458U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3S_WDT_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s1a.h b/zephyr/ports/asf/sam3s/include/pio/sam3s1a.h new file mode 100644 index 0000000..994cff5 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s1a.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S1A_PIO_ +#define _SAM3S1A_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 + +#endif /* _SAM3S1A_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s1b.h b/zephyr/ports/asf/sam3s/include/pio/sam3s1b.h new file mode 100644 index 0000000..7b61620 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s1b.h @@ -0,0 +1,277 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S1B_PIO_ +#define _SAM3S1B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 + +#endif /* _SAM3S1B_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s1c.h b/zephyr/ports/asf/sam3s/include/pio/sam3s1c.h new file mode 100644 index 0000000..20ab454 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s1c.h @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S1C_PIO_ +#define _SAM3S1C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 + +#endif /* _SAM3S1C_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s2a.h b/zephyr/ports/asf/sam3s/include/pio/sam3s2a.h new file mode 100644 index 0000000..539bf4c --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s2a.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S2A_PIO_ +#define _SAM3S2A_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 + +#endif /* _SAM3S2A_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s2b.h b/zephyr/ports/asf/sam3s/include/pio/sam3s2b.h new file mode 100644 index 0000000..e76f219 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s2b.h @@ -0,0 +1,277 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S2B_PIO_ +#define _SAM3S2B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 + +#endif /* _SAM3S2B_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s2c.h b/zephyr/ports/asf/sam3s/include/pio/sam3s2c.h new file mode 100644 index 0000000..73a2e4f --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s2c.h @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S2C_PIO_ +#define _SAM3S2C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 + +#endif /* _SAM3S2C_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s4a.h b/zephyr/ports/asf/sam3s/include/pio/sam3s4a.h new file mode 100644 index 0000000..7735373 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s4a.h @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S4A_PIO_ +#define _SAM3S4A_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 + +#endif /* _SAM3S4A_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s4b.h b/zephyr/ports/asf/sam3s/include/pio/sam3s4b.h new file mode 100644 index 0000000..9ecc446 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s4b.h @@ -0,0 +1,277 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S4B_PIO_ +#define _SAM3S4B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 + +#endif /* _SAM3S4B_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/pio/sam3s4c.h b/zephyr/ports/asf/sam3s/include/pio/sam3s4c.h new file mode 100644 index 0000000..d0e19ef --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/pio/sam3s4c.h @@ -0,0 +1,395 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S4C_PIO_ +#define _SAM3S4C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 + +#endif /* _SAM3S4C_PIO_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam.h b/zephyr/ports/asf/sam3s/include/sam.h new file mode 100644 index 0000000..df3ecde --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAM3S1A__) || defined(__ATSAM3S1A__) + #include "sam3s1a.h" +#elif defined(__SAM3S1B__) || defined(__ATSAM3S1B__) + #include "sam3s1b.h" +#elif defined(__SAM3S1C__) || defined(__ATSAM3S1C__) + #include "sam3s1c.h" +#elif defined(__SAM3S2A__) || defined(__ATSAM3S2A__) + #include "sam3s2a.h" +#elif defined(__SAM3S2B__) || defined(__ATSAM3S2B__) + #include "sam3s2b.h" +#elif defined(__SAM3S2C__) || defined(__ATSAM3S2C__) + #include "sam3s2c.h" +#elif defined(__SAM3S4A__) || defined(__ATSAM3S4A__) + #include "sam3s4a.h" +#elif defined(__SAM3S4B__) || defined(__ATSAM3S4B__) + #include "sam3s4b.h" +#elif defined(__SAM3S4C__) || defined(__ATSAM3S4C__) + #include "sam3s4c.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_ */ + diff --git a/zephyr/ports/asf/sam3s/include/sam3s.h b/zephyr/ports/asf/sam3s/include/sam3s.h new file mode 100644 index 0000000..4fca977 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S_ +#define _SAM3S_ + +#if defined __SAM3S1A__ + #include "sam3s1a.h" +#elif defined __SAM3S1B__ + #include "sam3s1b.h" +#elif defined __SAM3S1C__ + #include "sam3s1c.h" +#elif defined __SAM3S2A__ + #include "sam3s2a.h" +#elif defined __SAM3S2B__ + #include "sam3s2b.h" +#elif defined __SAM3S2C__ + #include "sam3s2c.h" +#elif defined __SAM3S4A__ + #include "sam3s4a.h" +#elif defined __SAM3S4B__ + #include "sam3s4b.h" +#elif defined __SAM3S4C__ + #include "sam3s4c.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAM3S_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s1a.h b/zephyr/ports/asf/sam3s/include/sam3s1a.h new file mode 100644 index 0000000..3b67bc5 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s1a.h @@ -0,0 +1,479 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S1A_ +#define _SAM3S1A_ + +/** \addtogroup SAM3S1A_definitions SAM3S1A definitions + This file defines all structures and symbols for SAM3S1A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1A_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S1A specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S1A Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S1A Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S1A Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S1A Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S1A Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S1A Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S1A Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S1A UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S1A UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S1A Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S1A Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S1A USART 0 (USART0) */ + TWI0_IRQn = 19, /**< 19 SAM3S1A Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S1A Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S1A Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S1A Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S1A Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S1A Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S1A Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S1A Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S1A Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S1A Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S1A CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S1A Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S1A USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pvReserved15; + void* pvReserved16; + void* pvReserved17; + void* pvReserved18; + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S1A core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S1A does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S1A uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1A_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1A_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1A_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s1a.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x10000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (256u) +#define IFLASH_NB_OF_LOCK_BITS (4u) +#define IRAM_SIZE (0x4000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28890561UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (8UL) +#define NB_CH_DAC (0UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S1A */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S1A_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s1b.h b/zephyr/ports/asf/sam3s/include/sam3s1b.h new file mode 100644 index 0000000..39525f2 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s1b.h @@ -0,0 +1,496 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S1B_ +#define _SAM3S1B_ + +/** \addtogroup SAM3S1B_definitions SAM3S1B definitions + This file defines all structures and symbols for SAM3S1B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S1B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S1B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S1B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S1B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S1B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S1B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S1B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S1B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S1B UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S1B UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S1B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S1B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S1B USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S1B USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S1B Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S1B Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S1B Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S1B Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S1B Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S1B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S1B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S1B Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S1B Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S1B Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S1B Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S1B CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S1B Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S1B USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S1B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S1B does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S1B uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s1b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x10000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (256u) +#define IFLASH_NB_OF_LOCK_BITS (4u) +#define IRAM_SIZE (0x4000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28990561UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (10UL) +#define NB_CH_DAC (2UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S1B */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S1B_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s1c.h b/zephyr/ports/asf/sam3s/include/sam3s1c.h new file mode 100644 index 0000000..012a7b8 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s1c.h @@ -0,0 +1,519 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S1C_ +#define _SAM3S1C_ + +/** \addtogroup SAM3S1C_definitions SAM3S1C definitions + This file defines all structures and symbols for SAM3S1C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S1C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S1C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S1C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S1C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S1C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S1C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S1C Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S1C Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S1C UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S1C UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S1C Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S1C Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3S1C Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 SAM3S1C USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S1C USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S1C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S1C Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S1C Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S1C Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S1C Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S1C Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S1C Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S1C Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAM3S1C Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAM3S1C Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAM3S1C Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 SAM3S1C Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S1C Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S1C Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S1C CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S1C Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S1C USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S1C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S1C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S1C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S1C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1C_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/smc.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S1C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s1c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x10000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (256u) +#define IFLASH_NB_OF_LOCK_BITS (4u) +#define IRAM_SIZE (0x4000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28A90561UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (16UL) +#define NB_CH_DAC (2UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S1C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S1C_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s2a.h b/zephyr/ports/asf/sam3s/include/sam3s2a.h new file mode 100644 index 0000000..f8fce4f --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s2a.h @@ -0,0 +1,479 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S2A_ +#define _SAM3S2A_ + +/** \addtogroup SAM3S2A_definitions SAM3S2A definitions + This file defines all structures and symbols for SAM3S2A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2A_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S2A specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S2A Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S2A Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S2A Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S2A Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S2A Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S2A Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S2A Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S2A UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S2A UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S2A Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S2A Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S2A USART 0 (USART0) */ + TWI0_IRQn = 19, /**< 19 SAM3S2A Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S2A Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S2A Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S2A Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S2A Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S2A Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S2A Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S2A Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S2A Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S2A Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S2A CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S2A Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S2A USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pvReserved15; + void* pvReserved16; + void* pvReserved17; + void* pvReserved18; + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S2A core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S2A does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S2A uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2A_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2A_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2A_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s2a.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x20000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (512u) +#define IFLASH_NB_OF_LOCK_BITS (8u) +#define IRAM_SIZE (0x8000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x288A0760UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (8UL) +#define NB_CH_DAC (0UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S2A */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S2A_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s2b.h b/zephyr/ports/asf/sam3s/include/sam3s2b.h new file mode 100644 index 0000000..52449b1 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s2b.h @@ -0,0 +1,496 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S2B_ +#define _SAM3S2B_ + +/** \addtogroup SAM3S2B_definitions SAM3S2B definitions + This file defines all structures and symbols for SAM3S2B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S2B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S2B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S2B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S2B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S2B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S2B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S2B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S2B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S2B UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S2B UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S2B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S2B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S2B USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S2B USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S2B Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S2B Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S2B Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S2B Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S2B Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S2B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S2B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S2B Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S2B Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S2B Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S2B Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S2B CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S2B Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S2B USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S2B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S2B does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S2B uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s2b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x20000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (512u) +#define IFLASH_NB_OF_LOCK_BITS (8u) +#define IRAM_SIZE (0x8000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x289A0760UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (10UL) +#define NB_CH_DAC (2UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S2B */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S2B_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s2c.h b/zephyr/ports/asf/sam3s/include/sam3s2c.h new file mode 100644 index 0000000..2f00558 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s2c.h @@ -0,0 +1,519 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S2C_ +#define _SAM3S2C_ + +/** \addtogroup SAM3S2C_definitions SAM3S2C definitions + This file defines all structures and symbols for SAM3S2C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S2C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S2C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S2C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S2C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S2C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S2C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S2C Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S2C Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S2C UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S2C UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S2C Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S2C Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3S2C Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 SAM3S2C USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S2C USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S2C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S2C Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S2C Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S2C Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S2C Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S2C Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S2C Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S2C Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAM3S2C Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAM3S2C Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAM3S2C Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 SAM3S2C Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S2C Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S2C Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S2C CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S2C Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S2C USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S2C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S2C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S2C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S2C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2C_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/smc.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S2C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s2c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x20000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (512u) +#define IFLASH_NB_OF_LOCK_BITS (8u) +#define IRAM_SIZE (0x8000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28AA0760UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (16UL) +#define NB_CH_DAC (2UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S2C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S2C_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s4a.h b/zephyr/ports/asf/sam3s/include/sam3s4a.h new file mode 100644 index 0000000..3bb7ce3 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s4a.h @@ -0,0 +1,479 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S4A_ +#define _SAM3S4A_ + +/** \addtogroup SAM3S4A_definitions SAM3S4A definitions + This file defines all structures and symbols for SAM3S4A: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4A_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S4A specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S4A Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S4A Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S4A Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S4A Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S4A Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S4A Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S4A Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S4A UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S4A UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S4A Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S4A Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S4A USART 0 (USART0) */ + TWI0_IRQn = 19, /**< 19 SAM3S4A Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S4A Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S4A Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S4A Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S4A Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S4A Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S4A Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S4A Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S4A Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S4A Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S4A CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S4A Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S4A USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pvReserved15; + void* pvReserved16; + void* pvReserved17; + void* pvReserved18; + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S4A core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S4A does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S4A uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4A_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4A_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4A_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s4a.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x40000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0xC000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28800960UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (8UL) +#define NB_CH_DAC (0UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S4A */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S4A_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s4b.h b/zephyr/ports/asf/sam3s/include/sam3s4b.h new file mode 100644 index 0000000..c6c9a9b --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s4b.h @@ -0,0 +1,496 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S4B_ +#define _SAM3S4B_ + +/** \addtogroup SAM3S4B_definitions SAM3S4B definitions + This file defines all structures and symbols for SAM3S4B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S4B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S4B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S4B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S4B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S4B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S4B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S4B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S4B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S4B UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S4B UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S4B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S4B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S4B USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S4B USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S4B Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S4B Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S4B Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S4B Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S4B Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S4B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S4B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S4B Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S4B Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S4B Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S4B Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S4B CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S4B Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S4B USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S4B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S4B does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S4B uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s4b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x40000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0xC000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28900960UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (10UL) +#define NB_CH_DAC (2UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S4B */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S4B_ */ diff --git a/zephyr/ports/asf/sam3s/include/sam3s4c.h b/zephyr/ports/asf/sam3s/include/sam3s4c.h new file mode 100644 index 0000000..c14e9a7 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/sam3s4c.h @@ -0,0 +1,519 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S4C_ +#define _SAM3S4C_ + +/** \addtogroup SAM3S4C_definitions SAM3S4C definitions + This file defines all structures and symbols for SAM3S4C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S4C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S4C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S4C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S4C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S4C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S4C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S4C Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S4C Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S4C UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S4C UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S4C Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S4C Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3S4C Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 SAM3S4C USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S4C USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S4C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S4C Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S4C Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S4C Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S4C Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S4C Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S4C Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S4C Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAM3S4C Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAM3S4C Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAM3S4C Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 SAM3S4C Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S4C Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S4C Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S4C CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S4C Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S4C USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S4C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S4C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S4C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3s.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4C_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/smc.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F00U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S4C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s4c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x40000u) +#define IFLASH_PAGE_SIZE (256u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0xC000u) + +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28A00960UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (16UL) +#define NB_CH_DAC (2UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S4C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (4U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (17000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (30000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (54000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S4C_ */ diff --git a/zephyr/ports/asf/sam3s/include/system_sam3s.h b/zephyr/ports/asf/sam3s/include/system_sam3s.h new file mode 100644 index 0000000..0a18354 --- /dev/null +++ b/zephyr/ports/asf/sam3s/include/system_sam3s.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAM3S_H_INCLUDED +#define SYSTEM_SAM3S_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAM3S_H_INCLUDED */ diff --git a/zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_128.FLM b/zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_128.FLM new file mode 100644 index 0000000000000000000000000000000000000000..7a00aeae5e7efce58dcbbc8c811a0c29f63adb26 GIT binary patch literal 13192 zcmeHNYiwIbc0O}2NzsyQNtB;!hq<=stZd6NDN(ZQ$cZSDk{FQ^Bg&TID4{8ml4wgL z!-s4K&J#{Hi`}-nKpLcrO<=T}?PGtmKiUFCyM+;S(QMHcNs$x)%jJ5 z9O_EHa(PF~&pr`{6?A-R?9k#e8O2Ghch5&hr;bGemtI+8o%h$i+0ydy(a6tzit^1C z+b2hAeAaPC_D?y_C_YoTdVkLq-4~07JZoLkwu2tc)9%quK72Iz%%ykM{u!2kc!<5x zeq{XFj)#rgbnM?hYM*Kyu?3edy}foD{I}P}T3+s;4~60VzKw_8x@&A~_pUJt#^Sea zyT(MvX|a>&V!K8cWn}OXA~2r_#0C?FZ(!ugxG}MwDz7Q#|4Pdi8(yU9*@H+u!X7Y)4=_0^1STj=**Vwj;0|f$a!vM_@Yw+Y#7~z;*=wKSe+src)hw z95{?Y>3Hnf6WL2-^H5vcV{N*V$lfJ%=TT?3{h+f;xJ0Le$k9w9YN->L4?(3uw4;s$ zp=erYZ6vZvn<6NQ_C^BHPKC1YE`<@SlQ_S(VoAO>0VGW<66Ag3=_HVG8SdPfg0MSrCG|zTC z+Hs~scRt=8*=xpTxS4DcPuGc)mfT34WU3qJ^-MF7NoVV%$-PW?v`#P;iAI}AMCa;+ zNyO^0I$C#i3?X~GnZeF7d8|%0-DP5+PHZsJN;KZgkVZfb*2$I;5JL|kXg=g4=Tq23 zh$iaP#g3;s7BI?5lcdloHm390j>FZ!LX`v2AE}4kQNtp=Km;LD8>@_Vxbd+I$yU8*@ zv|^XdDmT2)*X)+BL^%tD)@2hUx}w-@e_bJF&l^gfd3iR->#-mK*eI$IaIl{sPUQ2Xs)B+G_ysQ)P>#UwCZKTsDNV~Di zwUb(?MYL!wy3^*gI~~pzXS;LPe=qC&!m>{7i^@91y|Nf}t;_*pybqOOzlATNeI3%u*kElcnl!o8VV4{sDJ*U9xRjJzq_l>)}OD%o!{ z7A~dArsB7S{v*xxoDg?)a+eW_0=sxY=smXt9s4z1jv!&to#@hpVG4tA2Qryb1A!+H z77Vgyl zLqHHqgEJso+RSEr=(CI6XO+jLlko z8WtX$um~QL5RXO!7NxgF8Mi2Xvb$Jt+QPm1@9JB+8zk5F(4AjOo==RM5g5_`ZmXc5 zTpvSlRR5{uXl9V&!D({+3+Q9|FWK0%tsavhayc}uCn`-xRB$husESBNqADJ1CNpOF zyDrg*gu;s!9=G@v6Q2!Q_%;1aJ3Dcp?!+*;z6K|5NXdn`X-V(7W6t?P-0WHJ`BYGx zvw$~(PPF!>GdlBTNzx*rvd(yg_6lqwp?AWP*+vNb8L#w(I?oP zsd(oe#Q||~rBtHMzd*1)0+$~92Tgoev&$nOxRxujV{C;_;9=C}eml|cd%F06rC@FL zP+@UCq>rFlWBKEIv^8kovWbs1JD)$L)P_8;pv{^bQ7)GD_W*jjZj_&=+;SB;|E~0? z*_$WCQ$;@VYHQyFZKC8rc)2T_x68J zkK7-`bUF-q6t@VdD1Bl?O>whR5!qM&6>*&@Uj-!t5BS5>K`B`2IbrpoGNnVZZ)bl2~6BCjAL&gChIzt!7dN=ru{IDKfx6d}&Yw zCU*xR-D6A^UI~Jpv@qG=uh~XLorK=1*;o*HCt=~^^U%75B!Y|c;TfaXd(G=JMn?_r zF%kn?_=$PRpJ4t7_=7dRG%_82iur@5neQ8hfWIaXn@t20;b`6dfFJzR%;(!nGMGq6 z-k|Dxq>+`31tK%aV05~!&;FgM$;9WviKMU2W#gmFP4Eqi$7Y(Z4egv_qVte++Z^^F z6vvpyHwk>Uh9uCyv&K8*^@se@Z;r_{-xgRk6pA$T=^Fy?g1iObvXGomx&a=qjKxBo z8JL^op-iBtP%qZG!C1)Ts!%=M#7jc}+?`>pw11$d@ zn=yKO4Yp?8w2kA(B+6E>2)@fES)}1w%_6EJi2S-~9zt@M4R-3?LhLuB7*_p##eC8` zi2atBhz1f<$#`HgoJ>S6hK+%tVfikCeNePr2+!fSgd}#JpP8PSU6?U2j9s%c!Kp}` z$sOUv`4I%uz(jQd_6;+F710G`aDWlal?zBB9x;&jyA$Ey{OnwE=6uW;@^K%! zG=_(U2C)DRSrXwHUZ=dux%4%__{+rfIW%`6DIJvive$cpkz?$<8~eCMZ{S+?2A~|O zy5;b_o(rE+8u6RG2lt0x1t#yfKL%i3cZYEYsb5)F6=vN>-vi!w!-O6kMAgXeBzhCj z^Qg588Q}XB7-=X%#$8=f`G9Hx*I5(NB#!&BRdnKac2#Wj*1te4WM`_?_Bkci#uj-SJuL!qxgu(eh!=?`n+yCEBkrY~g={_E%83 zKjz;-`wl9Yq{EV44Fo;?z>GN&yU zv3f3u$HnZmlQA#w72t`&O69^t9N2oUTshajG+V7$&y~1O42<-frVG_dv3fst>e>o) z%js05k}W}f9;L;)*`_v2`PxuawW?wVi+3T*Omb!3@dgy~ZLk!65q0WS6U}#>uoH;bJzQu?AK% zm;q;NI8w!Q`5fNVvZbqq(v?%EN`+$XROxClXPk`Sm3KOuTVKM&ECpkUNMb3HPp?-q z*)6=tOmHbs*~qTTm*4Zo$&mG9ZH^@{b5o0jW9YxIv65Ua6|R=ETfIw{R?M+yko^Cn zV`qc^cgN1&@z{CWT@4m8S#CqTLtqyOmD43`3_P{T)ber(FV+^ef+v8iLOACXj4Z6t z*9+K1Ozn+Sx>2fFUCzTmnfkGSDye0(m6B}pg$nf3W1oQcCYaCIvqWbIth3(-u zl>V}h?3XG^?f?iZr^+2Deg`M5DvI}I5ERV3H};u(|5iEnyHW1V{X`!$IH-7ITjZ7w z6a7Rn8+d%yG>|EZX9sTsL4gZf)%jJ5 z9O_EHa(PF~&pr`{6?A-R?9k#e8O2Ghch5&hr;bGemtI+8o%h$i+0ydy(a6tzit^1C z+b2hAeAaPC_D?y_C_YoTdVkLq-4~07JZoLkwu2tc)9%quK72Iz%%ykM{u!2kc!<5x zeq{XFj)#rgbnM?hYM*Kyu?3edy}foD{I}P}T3+s;4~60VzKw_8x@&A~_pUJt#^Sea zyT(MvX|a>&V!K8cWn}OXA~2r_#0C?_z|ioOabsdVRbErf|CN?!Yz!41Ta$MeSO)b| z9Un!zYZg$p%XS2|Bd{HT?Fei~U^@ca5!jBvb_BK~upNQz2y91SI|BdDA|MXasSYCT zFvg|hv1dICLPP^l2@s3Sor znig6ciLBD52uh;8kwCOlp)9;hAw(SttlRFalUTUx5#kZKY#5sEY-=OxW{`p1y`(!2 zfw@Nlc)8iz1{S+Ow6Bd!U_aA{4nTpvr1-v0qJyRcgNK;Tz(Z}sje937NA`~FAbQvY zi3~;aw-X&!NL$;^wsx34(jndKIV~HH9SukSC<8=~aHGN6mnDE<^>#|ev2JvXVPOW3 zGswURlSb6njd7gphATw<-EjXDbNub5yw^ln!>8y(1KooC8|)^QBl0sqG}I5xvmK9i zoaxY=kGDtmnz0#fCY!|5b>gHYH&Q2=>IQl}(@bR2**a-*FB2ZE6HG;-(Pk3SxjJDI zv3jhI)?FP#$R2NIu(M1atCLN4nHZ=O8;rCPjW;u-5s-s*vSkFs&_f8C5BbRX6gCl} zi8^($DRhdBDZNM?VaJ|mK+(mti4sK_(4C|0eoW5en6X%$!05~#@Hv%c z86b-9l^JSIDbbTA%2PeJPg>%y&%?Gn7#5?vd$00bH@>qPuItEWmE>GTQGZtQaH zq!wxsEn182v^nighqJ}m?%eg?%R0ZXtW*1R9@Ohl~${HuWxDNx)CoGE@#t~ z@{)Y0A6YVA>}faV;brc~)>6%vbF2Am##k@pSIMT;3FWmysX{j4Os}O%+}1=T;n-)I zbTO3O%%!t*>#+L*dMDRS(t1e$M7Z7}@e;Ygo=I(F$@S-;YmClcF9N+ude5tZ@j#|T zU1h!Jrf`>^2QHB}7>TD=vl9EdaL;AS68wg6Z>HA68^y|Xa=i;9Zwhy%fN`!$_S=kw zOR2J{_-NOL_W#9f`-WkjODE?y9N&n-d6eodDnNLX|yx-?;!!XVs%Os3R8;0Z*z zhN|XCMW8?Z0A@+{hEG@LZ!7Q;I&SJaURr%1eRE=uq28MzTl2tXv*+>^s&qXU->eP} zkn39{+I!**c0DI{dg9d)a=l7om*@Bg_J0!Ycr2Jq1jBRWdWSQ`!b28rv+#t4JN5q% z5X92p49J!?vl$<`{uP?-QZin%)M??$(ryb^miFsE(6(5Dv!g=mIphvbPtGM{vsRym zg$E}rg2yDpqtSpx>8(-5ElQv4E*6}&aIgNm`j+kn$@M*S=a-V_6XRwCM)beiD(ENI z#}FLVe=0ee8Kih{nq2<^`k4MpHa2am$7G0H4o&NcO4AV)+)E~^B9f7)ipQGCj9LD! zOLQWk@S=ssEq=wsXM+}gO@GtQP8_H^F-)$n!HFAEav^S7(tGZhbG{Had)9kC6%^+z z;Ef=ZT_M-^N%ZT-e{OGgE9>M|e%Rc~VJF2GLi2U4ztzN)e*Aq$r+Y#PlY2s0u(>B{ zitdRy%jNpk`@7LBEb3V}ZT~yY2|Li=V;qQx`xR}y) zI>P6H0fOa+T}nQvwT`~%Q`FxUxE`sv;g2^w{rf;va?md|sJjQ+$p-!RAcG zJNGCKh>I(w5_SFsg7p!&^w>XW;=7t%9s$9%T#+4PD|`YEqc->3iGJVH#Sbh6YqN(6 zi}N9U1l1bLAK#;`LHm|Xe5~2|{3)e2uL6CI4RiShYE!O0s2sT`A&Sd5W0P{0bIzT7 zG+Jp(qtYk-0R?8V z8(?UdbjLxv*bPg&SkewMns&!-MjT&asTPUsk~ZuPcLPP*&|4e_ObflN+UhXy)g5k= z*51wSwB81D`fg_I18}2Tf5~ycfo>fSNu5XVbz%eur0xN`eYf4vUt$+_+Ydq390kTz zv(F>4I}E$ns|kmkFHZJ%QEl`Bz4aDDocbEQz;_5))M5fnk>tu|dLvD(_(mElFujrX zN5KCI73T=PvfRS=?@W3uo{5cH&l$p(MTHY(~Q^j6Krg2+1w3m>0{)-5CvT$~Tj7`@(WUY{{KYIu*4 z7}&y3%uD_R^GCoRtnsCh>F`s`A3V)`-!KIHHG$Y{BA5tA>-Goy;Gbqb-(HfzL_+cg zRo^3xtYj<@nMnqt({+9J?@Uc5J{L|TeRVDyA7yTWZ&*Aw(|m1c=M)p2hosx)um_ggt4axy$0GBAx^5=+gTg*elFB%awyk1}I`#Iwzeu&FUf zB6$x(s`yD<+QJF2sUZ@nE%dll7$&j2l_51wlSnr+647xsH9{iO%m|u{GbFOjj7gIb zAhFWSNKD41t#J~o&77dc36fZA=1f|g5Q$tfCoz9M!k&dmT;9Too16&}8zu+&H^B)8 zal}1eCt?=EOhwQOb!v1rI4#KtY{?`emnH(SdTPsLDc5-mW|q}5WpgqhCM&lioq> zx5Pv=keEuw1C!xoB62azzZ{hBBG?B-+lBC4!ob|@JU=r%GrKTjU>Lh*XM$6aIFmcV zi}NE0rh$p-1ne7T1S_Ho$lw4Ym@5~ML_A_3?{_D{!TH&_H9fbo}!>2qlALQ*;?_hqm51S7}Tc{lcPjo!eu>#ZdEXU5_;y?| z(X#vyTDEtqlleN0HSjyN&+fhtoV(+*)`hF}pQ7c%oZrsgNgwfBmIwYCV&xq|AvkuY3KK?6nH@*U5O9 z!mYJGUC5U!k}6-{0+mV$7y3%J?D5P`#gdUkU~@3$NqFL6PvC5HV8F9@HtO?v5`ZG% zaMT>O>xd^D7>{fYm|0|HP(6DjWMxic*3|N2OL}trtgG4>o*IFfh3A5w9;3PZ zmHRw7wo;(9!93&S$ufeFt^n9b6&bz0v0PX$1Ipx5tI2Y;Sj69Y<#W;DLGKW#>0*ZcsZybsJ5{<`%o!&mc;%hW=GK=mF-yT%B9d5&{jp6r4@7R86^Mz=-Aod z|J|{(cRY69c2|RiOqSaa?-1ApLgjP`8v{>mGPS&1!i%+qt>6hDs}RmP1tSY<^z{OE z5mS33m2Q+OR+sZIP^Nw?ph{{PZKWjJe4zsUw3(0~uUQPaU-JH_3h!@Rv6p*!UGo|a zSv0lx@%{^*!Tc{;*bY}5VX|LWtBT@%83YA0?~Q%t-oI6j{cea*cQ2^!$dz( z%myBxH4S8n;@QF5Kv3Yq7P%W9q7Uyg4o*3x1CXLPM1Pq9t0>+kaE_fScOYkg$@@6} zxykY4aK4DjbD@f@uX)~-z1JatoT-)ellZUy8djg*uY;y^nB5Dx#tsyZeQxZx*NgcD IO%)~gpX^?dRR910 literal 0 HcmV?d00001 diff --git a/zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_64.FLM b/zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_64.FLM new file mode 100644 index 0000000000000000000000000000000000000000..67c3b99692f16ccf024083f0063b2e51a0bac07b GIT binary patch literal 13188 zcmeHNYiwIbc0O}2NzsyQNtFCrJIu93XJuQKNr`&cu@g}wB{3o;MwBhZQ9@HBCDE2h zh7Ugi=Lsj9MYruPkOt{u6BzAg``91tkG4S3Zeaww=x)&#Ns$x(i;RnUU$Gm60b#r*EI`T=7r8Jod_^AGLh;LD%K4I=@Ph zgI(!YF70Uf>|=3ALC2=Y4=$~cQJm8Hc7J$e`e-C@@s)Mfd4K&IEiE4%iTvEBDBozY zeSEmaXB~HB-?a0T;xmP-_xD}Vy|HM>v)(mhJK)hg?H=vK!$*S8TzqH!pJDk&2iY6# z$Ht%Sc-Xj2NB{l9_UYC!TX6Z}+v~T%e|vqr<>e0gKp5Wd*?8!!yT-?Rc8yao7Qb!V zH7+_v#ZICN?HXN>k-{>u}_HVv!@L#c7bSb8=1g9rV;Ij0)0vGeVs%HObG@LGM#~k+K3zXPFRlY8QVehun7_w ziso-8I;4=cww-P5Fnzc~y4gD_8;>0gNB;-|M2~Qz!P=K4fMNA@O2*M{bc|tP29Ghw zz;TmC)ZdM9oalxtL<8M$|0Hw#?WVlfL|DV8=tP6vg8dunCYB@eGe9&v0L{}Kk9M5u z(4CLBNA{Sp8EGb)#L+r&%90zalT393y`E|&GU;@kG_{8bkJbsMBGH*<64BW@VG6N& ztd7=Q9Y@F>Z)UKwOdhY3O?R0Xs1qBEv=U7;Go%ragLSfH1jNuo2$~Q1$oUjD5u(XD zb*ba2jzx@e$|NatnvE&FNF8Cvo@hYP#f*s(MH$eYXWIRkoX0U^u{wd#+1=oCD$OxK z6yGB=)SObHCry;6dVa68#Cefmkbwo0Ms#kk%%=1EkWGvGWUepyr6p}gKLnpr2wp)g z5KcdBf-JCXf<(_KN$&Gmh4gnYnzT>{BNt7?G{ zW{n$O=<9aNSE8H+LhF(V5?xkow!fhev*%4E&%8VvsP0BjW12sqf!naJbqXMmJU z>B%CKC))kkGSubicQaQJGM;JudU+8GN#pz*S9zR&8Z(q=k+oU|LeTsx_S zT11Q1qC0I)yVK!pake{m{r9rYFD&cSzNoBI+$)Pw*UCH~#`{qj_FMQ8+SgHC7Jd`$ z+o=4m&e_G~Tc}agK=%tb_1Cmt!ZM<78=2 z5A|cq=8HY`U>;uPj%+Q}d^xw4&t{B`LVk^GTAff{FO(`|6VCK{s>E$gR1%JUs!10^ z*(6Y*~U|7w#*mjqql%a-Cf7!pNJ#T`6FkYm)soW8qS& zY$|?B=s(t6&k1o?CwCcfM-H9$u7^W}?cOa7~H4u0LQLdq? zc~TJ=NI!sClD*;6)%iOLyoipQ`i_^@9!TGu*yE`8X2{k&u-WXne1$4q&&97)hX%>@ zO%mKM6RC9%tM?1%P$67F~`m`nu2^W=JmGsVI~7H+ffgoQix{}2$w z(%=lpmab$oK63plG~1!j+{S3s;u*=|9l6Sc0=>gw}h|9h{k(PsZk~J`D>G zPFe(yNr*?I0gKXCqfA(oe%W0tIAh^n{rB`O-3^iJyXej@CC?=$%m|F>f45c8Pp*$3 zct-!3n1a1`MV*} z$%Mj-79O|w6%(HeTKF~nO*=cWzwX2cxqbmo+>nxsanq9Cd&ivf#kkqC-usE5IA;NG z1flFIxxPnYKtJ|#d%Ig%C%5v$=2i|nDZUt5sB8VLCZ_dc?>jo(lS-J}lgfh4Jy}z9 zPtIFjw^KYEo^0s4OBV_KF!J-T>$gxRu()`?w$_;Qfv)eOvd;Tw=Y9>pFLvT$O4sQy zp9cmAmLGO0`JmQ1`l3%ze;3tS&7Z&Q54(Pm9{Y(9e<LXU@L>G`82?vu~0Hu%9g7e73!*rcwEq9f1rtf6!vp@WsXhpIr;>fGZpXL zqc|uotd>gD`42LX6N&#l-iUB7PMKDBg)0n{w_dI*NyV?lv}AH=iikcHGA`f zc&f-po*WHbkdscGFXFH+LHhz{E_J>N^fflj%(8{PU#j{OdF>v%}&Jc6$iBiJu>_uK6~c0+%OUFfkNgseFVjH_m! zM`U*xcCkkj4mn?(?C+x5=mmP~ErvMtHF|;X5VEMn1ezkrmCf`Lm15&BlVrI|&OPpNG~hBoSO%2+taQ-fLc;apsKSJxXG5 z3qP?S`IF2a1AnN-mqup7PceUJl=;392>5FPvAIMr5sudF5Bk9$Wj^0tlEFkm@`hC3 zV~wn2ED)JZ2BR}|efIBEO(s4cP9%MGE*n3?+yvjScxL2;aU ze3QUuYe)hOJZrqeUVq3h{pOg=@NI!rL!n4RpT1%6&dXZ>E(^&?r5oV!%2+JcnSuE! z9?B$&3iVQ*8;pfat_s!DO}yk(cp+q98oeZzn>mYdru#@dvy~oY#vqAjn;BtKV~9lZ z9)?u$leoBr6JS%rBvM=Gaj7suVr45sYK)RdH!~8^2{tuGBGb$Wnv7E)hwbqg2-=}<{>19*WEH7`x_XgVT{XlRLso z3u6eTfr;t_>>FVOE20a?&>$n2D;JPNJYpd4dlKQ`!rXjv_FT*u_Cag6>^K%!GDe1n zhp+$+S`y(|UZ=dux%4-{_+?`H9GX9$ln%;$+3P*d$WeCQjeT6BH*hU`15gfC-E#O| z&xKDZjrh&pgZsm;0h4#!p8&9~yCb-R)UT{-3bXE`?*VVTVM31%plalI61@rNdDPm4 z4DkI5j5HJ>#PZB636}6Dmw8yyDB#N^e&HE70e%bfV4xN4>ldX9aBuS zEI*8v?cM5RzE0x}{7&uDyYB<%?)a>A;cES-X!$VbcQwZU675$Qw(!3}`>UwjAM@{^ zeFv4_)foRNTIEldrqRCvSN(TsxHWq!ojY z%!i*G^YHOH<_QNTB3A~@EV44Fo;?z>GN&NSUnrW z<6`#OiI^AoD)2;MwQ_zk4s0V=uACiMo~u@@=gLHK#6MtKE>tVU>V3GWYpc*Kr&E%z%8}TP)%d45HsmcBQ&zoJboIE@tx?Ygjdd8F01+ zBUMb7&*DWbTe?~(T|RlTR4C?7maZ0a#)$~tcxSS?jb%*Baxj*NB$gxj^hPz4-NK8^ z2A2bs&FqGJ_dREv2w8usjYtA9ceGeIhVBcStI3s8;c7X%)wy(O)f{>Tng2gJbT;^Z zcIfOJ51qH%wO}EWH%b+&D|r|w(*PDvCAEUKQj%@HP=S8hOh=H{Er#4Hd2dvO_cpHB$GyC!dHseg zn%ehx?*-3b{ueE5hbxXRS-8*oIbrU<%)oydNjZLxU_Sq@#_?1us?RP^*dC5T=`Z`p zeyO75_JhE3s@#F%w{gmW3RdIZXfj-4uZAZLKddpQ5p zkvTB)Jppa{I`D%tIzM(KvO!*?t|QC4UQ-t``p;C$BX%8 J1*<5z{{;4rkwO3f literal 0 HcmV?d00001 diff --git a/zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_GPNVM.FLM b/zephyr/ports/asf/sam3s/keil/Flash/ATSAM3S_GPNVM.FLM new file mode 100644 index 0000000000000000000000000000000000000000..fd598909edaff46e5a538524c2ce5b6317be11e8 GIT binary patch literal 13980 zcmeHOeQaCTbwBq#lA6Iwlh}?dlM-bsjvSMsD2b*%7*Up#LLzLHcFEeU0h$Hf))hg!w%Hb7`(ycI=mG>Sy0yVJctwI?NLplA{wTUEUG~og zq^S2h_r1$U$}Z9Y%PCDUK-U+(fW@afLj^@twK-mGl?$Ckga{uX4k9@|)Vurv5oNPM%b_bMILmYbLD(LFWa zf4DA|i{my9WAnaXuxnqC!c+0rZ2N+u?Tpw<^iYdN56LLwBSdH}5t)%60P+FqP+@b;e84rYEz)4yWJwO zaK~N5Eppk=G~Lj(}-?E1v;$wemtez zZb&fL&2$FtXdy1#d!adcU}z7~Ck&9tqiBIvq9Y1vY1!M-3e`v3q?_g47ZTGd^+on6uw?+>bu{qsHHi%~|;G!u<9 zGNcla!xq_80^;Z$2$~<`k;hZSK#0aH>SEi2Z3}4SxIt3r1S?bZq87rAU8qB0B4(gO zlMLw2;nn~;=RA6B$|5j2y&rrYN;3=)#Sh34YIG^l0|v@nJ$q1U;&G8+kbyaaMs)F@ z98L3wFq#$)$+5l|keakTy%2m*A$SEfK{)-e0kXi70TMl;B-!Sp3h8ZQG-;v^MwSi4 z;G_(M=_>)4H>{>52tyeL*i4oIqE)*r*0|t_zHT>tCCZr~YF#owqRWcS`Zp9}Sl(3f z%*(Svo{t3yKu1xvfP?**ft+t022wJR?gQ*sSs_G~K{_ zvS>*y%>rV)7nxyx3uk;0dA<&3K0kyjKI4y?co#}eE67hEhdQ6Urv0`c9$B2;Mh+r} zIzM$y{~U8H8{I%y?hjGo2^-1Q+}F1>wvj5Y&m{ULC^S3e37-nzbB`xn*evEYvZY>6 zpwI7lc%+)!$av292OhzXBH^=37t7gFd1*6MTC3)L{-w<;o_MKnDVwg8m*k`U(30_b zPhIGfr`eFLshTh6*7DhmXQPl`Bb#Os%Ik$vg>1r^UQd;{tcgm(@eefV;%Ig&m(J3Q zN8IzUPOfXD^^pFiaJ@j{DRP57o!ZQj>u*5U7@fOP1bU71p3exzLzxnFl=Yr#!d-p> zxI~^|B%WH!O6-fmJ)12{@Hye$N^L|oiFA6&T4PCY%VbYy2X~0m0Mz}+nOsS5*9gnn)tolhspfCL~ z^pdoOPe=QoDsTyg8*Il*Yafeko&Z7Qn@7mbabUCAbNLEYIv$H}RR{XX^?M{*d*Tds zJSO&fN0Vq>5%??ZHFc}J1n%GZg)5~KAW7HF>QKGJUnI+yapjY zIT*{0V#PgF=9kuNdNIp!2r45fZ(wHACjXP zL5hcCZl6tvVp3IWF)HMv2HM@On)~dI+jp)(Zu5> zzhdAsVH4lhpSQCUw^>e{Cf66>#8oM|5H~dGJ?|QQz7RJo>pede6z5UE3&Ci1m0Yiq z=+jU9(%$M;+R3f_u(_4PPKqy#&RMnI(!_**;=7J^_m~nU_n6XPbC1<3y2oZsuUjb| ziHy~m?$AX-KZ@~r)b&Rg?$?mb`Q`jr=XOzP=e4u_HVyZTy*QxK6*|g$gVUPlb}9LB z&2!kI04)9)N^>TE^prp9`YpQu=R*92ut)Q`3W<&?>*3Aw+sL^Tujp5&(5PH`<1)ar z46f$W0PhC)Xfj#Kma7{T>Zpo%T+sb5Y2sgm{bF9JV^zHOewo!76}xV#sG;JAn)qGK zKC+R@Uk+=1Dv#)fAybGq0U+}*!9-#08Zzhb%>wnj#5Vc z!2k(1!~>2~PP*o!_9t;3`MVmyZxFsCWr&_b*)S(RuDNj2z%Q=g9FdeGDCgYE+rK$I zX;}K?#}`d;?8Vq-HkuWu%6a91|Q4NPlE~qm93^KA$~x>cRJB`!`vHy&}YP zIs$o&f?N4pvxhelh~TU1-w_Vs=yV)#bm|VrosQ0Gl*qg|5N zkWBC3yHAo52El0PyFi3=M^d@%hT57ROk!(w>MJ0w2RUlP*b8 zO+Ayia-Dh(_;Mpj#kS6(MXKpy5?>cYJ7&Qh+ByVEKDghG9J2)X$HAo`0gC3U^ zPLo*K$&fY9kVrQ&5|bmWYKTOpkr6f+_mapqGR6%?h{S3mBQYMAx<*K>HFClxCro0! zkuz>`MoHuvIf=Q8QT8lC;?fRI+~ACn*fcm8e`7qrAda}_Eh2g`!c+vkU{NP$!ZArk zU`qxWV`(fjWesgPSjrY}!5C$=k+LO^PRWtzoR9Tm6g*y|_)R~yYm|P|htCNf*dw6? zTMzhr5g$GzJ}-DU*OC2!L6Cn#uzg=W!xv)tZ?YQCv11Yrix+6DGcPweRbQ!mT*8!>{JG9g7$Qm8O8}aji_=U4} zGzNTgg66s;WZ$S$KW}19;Lg>AG>I?OaGm(~9hGeK!3~a$O6X(q0$GGSZ+<#FJE52; zS$+^D>wB@C`8oyb`0d&UH@*v;&GDA&!X56fQSw2A^)b$u5x%)8{2u{7T!;TN;A9=n zU64lR$Z-7+QT`Y?XyPCdUx)aem-&2bQvP>n8u4#i%HIwRo$IZTH-mqDrEF>=ld7bQ z!C)NI`zqP(3iVlJyqe;+(U&gd%N0qLFTzu%hx6pch8es6TaJG&5%dY??p#lo>s@5MwUF@FZ=#H4p75f6nU-q{)O zBO{?9Z(=SqJsO%Fos5onXCn^`d3nno@;<>8w537tey+wK|H&Ca>@sM6?mesTA3e<1KY@zE9d%_W~vqQ zi9L~&3v!>KyilzatG53#X5lt*b^XZLhCcA?doenRBDx292`HRIx&&g5qKO7{n@&Yp!Q5jo! zP}p2eu9OOom$N(lOP5xS)@Lv^{zqHS3jZ&+p8ez2^V+@^E@ZM?j`9kERbsT9E@9!| z?oFmvR!aD_#l%+e`jk}&k2?ipB-ZE~1*|eg?afrWUaDAK$wNVz`Y@3ysTGu!k}UIu z3hJkgK?(A@$&l-Bz?`>S@cPFYdxMYXH_zqgOqyC7c|8Zu!~9=2u^!IYHf3U)*4|^R z@yx*HCgrgDO8zsbRJ(P9rfhbYa@ZoJzw9IXrIM1n4FtBUlFxq*%j~q76fX!|!OZ%~QEVsdteF&V61aky^_O0vdJv>sWH$0{&9mXlf6hiURNeopmc|GSVF2|3<`6M#;g-ZX~N90jT xKvdx80b|V6(jgxnAZnP^Z(jsW)nRr3a{SJ&lH&ai2z6u{9zg#pA(Tq)zW|{v4sHMd literal 0 HcmV?d00001 diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S1A.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S1A.svd new file mode 100644 index 0000000..642f2fb --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S1A.svd @@ -0,0 +1,45860 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S1A + SAM3S + 0 + Atmel ATSAM3S1A Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S1B.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S1B.svd new file mode 100644 index 0000000..d0111e4 --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S1B.svd @@ -0,0 +1,49672 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S1B + SAM3S + 0 + Atmel ATSAM3S1B Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449K + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S1C.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S1C.svd new file mode 100644 index 0000000..6927d42 --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S1C.svd @@ -0,0 +1,64309 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S1C + SAM3S + 0 + Atmel ATSAM3S1C Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449K + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TC1 + 6082R + Timer Counter 1 + TC + TC1_ + 0x40014000 + + 0 + 0x4000 + registers + + + TC3 + 26 + + + TC4 + 27 + + + TC5 + 28 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + SMC + 6498F + Static Memory Controller + EBI + SMC_ + 0x400E0000 + + 0 + 0x200 + registers + + + + SETUP0 + SMC Setup Register (CS_number = 0) + 0x00000000 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE0 + SMC Pulse Register (CS_number = 0) + 0x00000004 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE0 + SMC Cycle Register (CS_number = 0) + 0x00000008 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE0 + SMC Mode Register (CS_number = 0) + 0x0000000C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP1 + SMC Setup Register (CS_number = 1) + 0x00000010 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE1 + SMC Pulse Register (CS_number = 1) + 0x00000014 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE1 + SMC Cycle Register (CS_number = 1) + 0x00000018 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE1 + SMC Mode Register (CS_number = 1) + 0x0000001C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP2 + SMC Setup Register (CS_number = 2) + 0x00000020 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE2 + SMC Pulse Register (CS_number = 2) + 0x00000024 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE2 + SMC Cycle Register (CS_number = 2) + 0x00000028 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE2 + SMC Mode Register (CS_number = 2) + 0x0000002C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP3 + SMC Setup Register (CS_number = 3) + 0x00000030 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE3 + SMC Pulse Register (CS_number = 3) + 0x00000034 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE3 + SMC Cycle Register (CS_number = 3) + 0x00000038 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE3 + SMC Mode Register (CS_number = 3) + 0x0000003C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + OCMS + SMC OCMS MODE Register + 0x00000080 + 32 + read-write + 0x00000000 + + + SMSE + Static Memory Controller Scrambling Enable + 0 + 1 + read-write + + + CS0SE + Chip Select (x = 0 to 3) Scrambling Enable + 16 + 1 + read-write + + + CS1SE + Chip Select (x = 0 to 3) Scrambling Enable + 17 + 1 + read-write + + + CS2SE + Chip Select (x = 0 to 3) Scrambling Enable + 18 + 1 + read-write + + + CS3SE + Chip Select (x = 0 to 3) Scrambling Enable + 19 + 1 + read-write + + + + + KEY1 + SMC OCMS KEY1 Register + 0x00000084 + 32 + write-only + 0x00000000 + + + KEY1 + Off Chip Memory Scrambling (OCMS) Key Part 1 + 0 + 32 + write-only + + + + + KEY2 + SMC OCMS KEY2 Register + 0x00000088 + 32 + write-only + 0x00000000 + + + KEY2 + Off Chip Memory Scrambling (OCMS) Key Part 2 + 0 + 32 + write-only + + + + + WPMR + SMC Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + SMC Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Enable + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + PIOC + 11004J + Parallel Input/Output Controller C + PIO + PIOC_ + 0x400E1200 + + 0 + 0x200 + registers + + + PIOC + 13 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S2A.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S2A.svd new file mode 100644 index 0000000..c528ec8 --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S2A.svd @@ -0,0 +1,45860 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S2A + SAM3S + 0 + Atmel ATSAM3S2A Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S2B.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S2B.svd new file mode 100644 index 0000000..caef2ca --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S2B.svd @@ -0,0 +1,49672 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S2B + SAM3S + 0 + Atmel ATSAM3S2B Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449K + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S2C.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S2C.svd new file mode 100644 index 0000000..3030582 --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S2C.svd @@ -0,0 +1,64309 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S2C + SAM3S + 0 + Atmel ATSAM3S2C Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449K + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TC1 + 6082R + Timer Counter 1 + TC + TC1_ + 0x40014000 + + 0 + 0x4000 + registers + + + TC3 + 26 + + + TC4 + 27 + + + TC5 + 28 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + SMC + 6498F + Static Memory Controller + EBI + SMC_ + 0x400E0000 + + 0 + 0x200 + registers + + + + SETUP0 + SMC Setup Register (CS_number = 0) + 0x00000000 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE0 + SMC Pulse Register (CS_number = 0) + 0x00000004 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE0 + SMC Cycle Register (CS_number = 0) + 0x00000008 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE0 + SMC Mode Register (CS_number = 0) + 0x0000000C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP1 + SMC Setup Register (CS_number = 1) + 0x00000010 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE1 + SMC Pulse Register (CS_number = 1) + 0x00000014 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE1 + SMC Cycle Register (CS_number = 1) + 0x00000018 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE1 + SMC Mode Register (CS_number = 1) + 0x0000001C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP2 + SMC Setup Register (CS_number = 2) + 0x00000020 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE2 + SMC Pulse Register (CS_number = 2) + 0x00000024 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE2 + SMC Cycle Register (CS_number = 2) + 0x00000028 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE2 + SMC Mode Register (CS_number = 2) + 0x0000002C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP3 + SMC Setup Register (CS_number = 3) + 0x00000030 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE3 + SMC Pulse Register (CS_number = 3) + 0x00000034 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE3 + SMC Cycle Register (CS_number = 3) + 0x00000038 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE3 + SMC Mode Register (CS_number = 3) + 0x0000003C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + OCMS + SMC OCMS MODE Register + 0x00000080 + 32 + read-write + 0x00000000 + + + SMSE + Static Memory Controller Scrambling Enable + 0 + 1 + read-write + + + CS0SE + Chip Select (x = 0 to 3) Scrambling Enable + 16 + 1 + read-write + + + CS1SE + Chip Select (x = 0 to 3) Scrambling Enable + 17 + 1 + read-write + + + CS2SE + Chip Select (x = 0 to 3) Scrambling Enable + 18 + 1 + read-write + + + CS3SE + Chip Select (x = 0 to 3) Scrambling Enable + 19 + 1 + read-write + + + + + KEY1 + SMC OCMS KEY1 Register + 0x00000084 + 32 + write-only + 0x00000000 + + + KEY1 + Off Chip Memory Scrambling (OCMS) Key Part 1 + 0 + 32 + write-only + + + + + KEY2 + SMC OCMS KEY2 Register + 0x00000088 + 32 + write-only + 0x00000000 + + + KEY2 + Off Chip Memory Scrambling (OCMS) Key Part 2 + 0 + 32 + write-only + + + + + WPMR + SMC Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + SMC Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Enable + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + PIOC + 11004J + Parallel Input/Output Controller C + PIO + PIOC_ + 0x400E1200 + + 0 + 0x200 + registers + + + PIOC + 13 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S4A.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S4A.svd new file mode 100644 index 0000000..1cecf21 --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S4A.svd @@ -0,0 +1,45860 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S4A + SAM3S + 0 + Atmel ATSAM3S4A Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S4B.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S4B.svd new file mode 100644 index 0000000..2cd46cd --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S4B.svd @@ -0,0 +1,49672 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S4B + SAM3S + 0 + Atmel ATSAM3S4B Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449K + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/svd/ATSAM3S4C.svd b/zephyr/ports/asf/sam3s/svd/ATSAM3S4C.svd new file mode 100644 index 0000000..682f697 --- /dev/null +++ b/zephyr/ports/asf/sam3s/svd/ATSAM3S4C.svd @@ -0,0 +1,64309 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S4C + SAM3S + 0 + Atmel ATSAM3S4C Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449K + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + Read Proof Enable + 11 + 1 + read-write + + + WRPROOF + Write Proof Enable + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SD Card Single Block + 0x0 + + + MULTIPLE + MMC/SD Card Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078M + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, RK pin is an input + 0x0 + + + CONTINUOUS + Continuous Receive Clock, RK pin is an output + 0x1 + + + TRANSFER + Receive Clock only during data transfers, RK pin is an output + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_RF_LOW + Receive Clock enabled only if RF Low + 0x1 + + + EN_RF_HIGH + Receive Clock enabled only if RF High + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer, RF pin is an output + 0x3 + + + HIGH + Driven High during data transfer, RF pin is an output + 0x4 + + + TOGGLING + Toggling at each start of data transfer, RF pin is an output + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + RK + RK Clock signal + 0x1 + + + TK + TK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None, TK pin is an input + 0x0 + + + CONTINUOUS + Continuous Transmit Clock, TK pin is an output + 0x1 + + + TRANSFER + Transmit Clock only during data transfers, TK pin is an output + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + CONTINUOUS + None + 0x0 + + + EN_TF_LOW + Transmit Clock enabled only if TF Low + 0x1 + + + EN_TF_HIGH + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data + 0x0 + + + RECEIVE + Receive start + 0x1 + + + TF_LOW + Detection of a low level on TF signal + 0x2 + + + TF_HIGH + Detection of a high level on TF signal + 0x3 + + + TF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + TF_RISING + Detection of a rising edge on TF signal + 0x5 + + + TF_LEVEL + Detection of any level change on TF signal + 0x6 + + + TF_EDGE + Detection of any edge on TF signal + 0x7 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None, RF pin is an input + 0x0 + + + NEGATIVE + Negative Pulse, RF pin is an output + 0x1 + + + POSITIVE + Positive Pulse, RF pin is an output + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535343 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088W + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect Key + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x535049 + + + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082R + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TC1 + 6082R + Timer Counter 1 + TC + TC1_ + 0x40014000 + + 0 + 0x4000 + registers + + + TC3 + 26 + + + TC4 + 27 + + + TC5 + 28 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x54494D + + + + + + + + + TWI0 + 6212O + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212O + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343J + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + SMMR + PWM Stepper Motor Mode Register + 0x000000B0 + 32 + read-write + 0x00000000 + + + GCEN0 + Gray Count ENable + 0 + 1 + read-write + + + GCEN1 + Gray Count ENable + 1 + 1 + read-write + + + DOWN0 + DOWN Count + 16 + 1 + read-write + + + DOWN1 + DOWN Count + 17 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089ZC + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + Inverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max Number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + ENDRX + 3 + 1 + write-only + + + ENDTX + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + 11 + 1 + write-only + + + RXBUFF + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max Number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + 3 + 1 + read-only + + + ENDTX + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + TXBUFE + 11 + 1 + read-only + + + RXBUFF + 12 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be Transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 16 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift Compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x555341 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Hardware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489Q + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The wake-up time can be modified by programming FWUP bit + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + If SLEEP is 1 then both ADC Core and reference voltage circuitry are OFF between conversions + 0 + + + ON + If SLEEP is 1 then Fast Wake-up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers and can be used to convert several times the same channel. + 1 + + + + + + + 2 + 4 + 0-1 + SEQR[%s] + Channel Sequence Register + 0x00000008 + 32 + read-write + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + TAG + TAG of the ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for Channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for Channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for Channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for Channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for Channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for Channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for Channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for Channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for Channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for Channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for Channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for Channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for Channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for Channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for Channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for Channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 + 0x414443 + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461G + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + TRGSEL0 + External trigger + 0x0 + + + TRGSEL1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + TRGSEL2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + TRGSEL3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + TRGSEL4 + PWM Event Line 0 + 0x4 + + + TRGSEL5 + PWM Event Line 1 + 0x5 + + + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + DISABLED + Normal Mode: The DAC Core and reference voltage circuitry are kept ON between conversions. + 0 + + + ENABLED + Sleep Mode: The DAC Core and/or reference voltage circuitry are OFF between conversions. + 1 + + + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + STAMODE + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit. Voltage reference is OFF between conversions. + 0 + + + FASTWAKEUP + Fast Wake up after Sleep Mode: the voltage reference is kept ON between conversions but DAC Core is OFF + 1 + + + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. + 0x444143 + + + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + SMC + 6498F + Static Memory Controller + EBI + SMC_ + 0x400E0000 + + 0 + 0x200 + registers + + + + SETUP0 + SMC Setup Register (CS_number = 0) + 0x00000000 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE0 + SMC Pulse Register (CS_number = 0) + 0x00000004 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE0 + SMC Cycle Register (CS_number = 0) + 0x00000008 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE0 + SMC Mode Register (CS_number = 0) + 0x0000000C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP1 + SMC Setup Register (CS_number = 1) + 0x00000010 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE1 + SMC Pulse Register (CS_number = 1) + 0x00000014 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE1 + SMC Cycle Register (CS_number = 1) + 0x00000018 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE1 + SMC Mode Register (CS_number = 1) + 0x0000001C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP2 + SMC Setup Register (CS_number = 2) + 0x00000020 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE2 + SMC Pulse Register (CS_number = 2) + 0x00000024 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE2 + SMC Cycle Register (CS_number = 2) + 0x00000028 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE2 + SMC Mode Register (CS_number = 2) + 0x0000002C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP3 + SMC Setup Register (CS_number = 3) + 0x00000030 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE3 + SMC Pulse Register (CS_number = 3) + 0x00000034 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE3 + SMC Cycle Register (CS_number = 3) + 0x00000038 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE3 + SMC Mode Register (CS_number = 3) + 0x0000003C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + OCMS + SMC OCMS MODE Register + 0x00000080 + 32 + read-write + 0x00000000 + + + SMSE + Static Memory Controller Scrambling Enable + 0 + 1 + read-write + + + CS0SE + Chip Select (x = 0 to 3) Scrambling Enable + 16 + 1 + read-write + + + CS1SE + Chip Select (x = 0 to 3) Scrambling Enable + 17 + 1 + read-write + + + CS2SE + Chip Select (x = 0 to 3) Scrambling Enable + 18 + 1 + read-write + + + CS3SE + Chip Select (x = 0 to 3) Scrambling Enable + 19 + 1 + read-write + + + + + KEY1 + SMC OCMS KEY1 Register + 0x00000084 + 32 + write-only + 0x00000000 + + + KEY1 + Off Chip Memory Scrambling (OCMS) Key Part 1 + 0 + 32 + write-only + + + + + KEY2 + SMC OCMS KEY2 Register + 0x00000088 + 32 + write-only + 0x00000000 + + + KEY2 + Off Chip Memory Scrambling (OCMS) Key Part 2 + 0 + 32 + write-only + + + + + WPMR + SMC Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + SMC Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Enable + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116I + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000008 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Write Access Password + 16 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation.Always reads as 0. + 0x37 + + + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-only + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-only + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-only + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Start-up Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Start-up Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Start-up Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Start-up Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Start-up Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Start-up Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Start-up Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Start-up Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Start-up Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Start-up Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Start-up Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Start-up Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Start-up Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Start-up Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Start-up Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Start-up Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Start-up Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Start-up Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Start-up Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Start-up Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Start-up Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Start-up Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Start-up Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Start-up Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Start-up Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Start-up Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Start-up Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Start-up Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Start-up Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Start-up Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Start-up Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Start-up Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Start-up Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Start-up Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x504D43 + + + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 MHz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 MHz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 MHz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 MHz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 MHz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 MHz + 23 + 1 + read-write + + + + + + + UART0 + 6418H + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417P + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8 Kbytes + 0x1 + + + 16K + 16 Kbytes + 0x2 + + + 32K + 32 Kbytes + 0x3 + + + 64K + 64 Kbytes + 0x5 + + + 128K + 128 Kbytes + 0x7 + + + 256K + 256 Kbytes + 0x9 + + + 512K + 512 Kbytes + 0xA + + + 1024K + 1024 Kbytes + 0xC + + + 2048K + 2048 Kbytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48 Kbytes + 0x0 + + + 192K + 192 Kbytes + 0x1 + + + 2K + 2 Kbytes + 0x2 + + + 6K + 6 Kbytes + 0x3 + + + 24K + 24 Kbytes + 0x4 + + + 4K + 4 Kbytes + 0x5 + + + 80K + 80 Kbytes + 0x6 + + + 160K + 160 Kbytes + 0x7 + + + 8K + 8 Kbytes + 0x8 + + + 16K + 16 Kbytes + 0x9 + + + 32K + 32 Kbytes + 0xA + + + 64K + 64 Kbytes + 0xB + + + 128K + 128 Kbytes + 0xC + + + 256K + 256 Kbytes + 0xD + + + 96K + 96 Kbytes + 0xE + + + 512K + 512 Kbytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91SAM4SH2 + AT91SAM4SH2 Series + 0x45 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + SAM4CxxC + SAM4CxC Series (100-pin version) + 0x64 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + SAM4LxA + SAM4LxA Series (48-pin version) + 0xB0 + + + SAM4LxB + SAM4LxB Series (64-pin version) + 0xB1 + + + SAM4LxC + SAM4LxC Series (100-pin version) + 0xB2 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418H + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even Parity + 0x0 + + + ODD + Odd Parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No Parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450J + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + GCALB + Get CALIB Bit + 0x10 + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004J + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + RPR + Receive Pointer Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000108 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000118 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000124 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000128 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004J + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + PIOC + 11004J + Parallel Input/Output Controller C + PIO + PIOC_ + 0x400E1200 + + 0 + 0x200 + registers + + + PIOC + 13 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable + 0 + 1 + write-only + + + P1 + Multi Drive Enable + 1 + 1 + write-only + + + P2 + Multi Drive Enable + 2 + 1 + write-only + + + P3 + Multi Drive Enable + 3 + 1 + write-only + + + P4 + Multi Drive Enable + 4 + 1 + write-only + + + P5 + Multi Drive Enable + 5 + 1 + write-only + + + P6 + Multi Drive Enable + 6 + 1 + write-only + + + P7 + Multi Drive Enable + 7 + 1 + write-only + + + P8 + Multi Drive Enable + 8 + 1 + write-only + + + P9 + Multi Drive Enable + 9 + 1 + write-only + + + P10 + Multi Drive Enable + 10 + 1 + write-only + + + P11 + Multi Drive Enable + 11 + 1 + write-only + + + P12 + Multi Drive Enable + 12 + 1 + write-only + + + P13 + Multi Drive Enable + 13 + 1 + write-only + + + P14 + Multi Drive Enable + 14 + 1 + write-only + + + P15 + Multi Drive Enable + 15 + 1 + write-only + + + P16 + Multi Drive Enable + 16 + 1 + write-only + + + P17 + Multi Drive Enable + 17 + 1 + write-only + + + P18 + Multi Drive Enable + 18 + 1 + write-only + + + P19 + Multi Drive Enable + 19 + 1 + write-only + + + P20 + Multi Drive Enable + 20 + 1 + write-only + + + P21 + Multi Drive Enable + 21 + 1 + write-only + + + P22 + Multi Drive Enable + 22 + 1 + write-only + + + P23 + Multi Drive Enable + 23 + 1 + write-only + + + P24 + Multi Drive Enable + 24 + 1 + write-only + + + P25 + Multi Drive Enable + 25 + 1 + write-only + + + P26 + Multi Drive Enable + 26 + 1 + write-only + + + P27 + Multi Drive Enable + 27 + 1 + write-only + + + P28 + Multi Drive Enable + 28 + 1 + write-only + + + P29 + Multi Drive Enable + 29 + 1 + write-only + + + P30 + Multi Drive Enable + 30 + 1 + write-only + + + P31 + Multi Drive Enable + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + Slow Clock Divider Selection for Debouncing + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable + 0 + 1 + write-only + + + P1 + Pull Down Disable + 1 + 1 + write-only + + + P2 + Pull Down Disable + 2 + 1 + write-only + + + P3 + Pull Down Disable + 3 + 1 + write-only + + + P4 + Pull Down Disable + 4 + 1 + write-only + + + P5 + Pull Down Disable + 5 + 1 + write-only + + + P6 + Pull Down Disable + 6 + 1 + write-only + + + P7 + Pull Down Disable + 7 + 1 + write-only + + + P8 + Pull Down Disable + 8 + 1 + write-only + + + P9 + Pull Down Disable + 9 + 1 + write-only + + + P10 + Pull Down Disable + 10 + 1 + write-only + + + P11 + Pull Down Disable + 11 + 1 + write-only + + + P12 + Pull Down Disable + 12 + 1 + write-only + + + P13 + Pull Down Disable + 13 + 1 + write-only + + + P14 + Pull Down Disable + 14 + 1 + write-only + + + P15 + Pull Down Disable + 15 + 1 + write-only + + + P16 + Pull Down Disable + 16 + 1 + write-only + + + P17 + Pull Down Disable + 17 + 1 + write-only + + + P18 + Pull Down Disable + 18 + 1 + write-only + + + P19 + Pull Down Disable + 19 + 1 + write-only + + + P20 + Pull Down Disable + 20 + 1 + write-only + + + P21 + Pull Down Disable + 21 + 1 + write-only + + + P22 + Pull Down Disable + 22 + 1 + write-only + + + P23 + Pull Down Disable + 23 + 1 + write-only + + + P24 + Pull Down Disable + 24 + 1 + write-only + + + P25 + Pull Down Disable + 25 + 1 + write-only + + + P26 + Pull Down Disable + 26 + 1 + write-only + + + P27 + Pull Down Disable + 27 + 1 + write-only + + + P28 + Pull Down Disable + 28 + 1 + write-only + + + P29 + Pull Down Disable + 29 + 1 + write-only + + + P30 + Pull Down Disable + 30 + 1 + write-only + + + P31 + Pull Down Disable + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable + 0 + 1 + write-only + + + P1 + Pull Down Enable + 1 + 1 + write-only + + + P2 + Pull Down Enable + 2 + 1 + write-only + + + P3 + Pull Down Enable + 3 + 1 + write-only + + + P4 + Pull Down Enable + 4 + 1 + write-only + + + P5 + Pull Down Enable + 5 + 1 + write-only + + + P6 + Pull Down Enable + 6 + 1 + write-only + + + P7 + Pull Down Enable + 7 + 1 + write-only + + + P8 + Pull Down Enable + 8 + 1 + write-only + + + P9 + Pull Down Enable + 9 + 1 + write-only + + + P10 + Pull Down Enable + 10 + 1 + write-only + + + P11 + Pull Down Enable + 11 + 1 + write-only + + + P12 + Pull Down Enable + 12 + 1 + write-only + + + P13 + Pull Down Enable + 13 + 1 + write-only + + + P14 + Pull Down Enable + 14 + 1 + write-only + + + P15 + Pull Down Enable + 15 + 1 + write-only + + + P16 + Pull Down Enable + 16 + 1 + write-only + + + P17 + Pull Down Enable + 17 + 1 + write-only + + + P18 + Pull Down Enable + 18 + 1 + write-only + + + P19 + Pull Down Enable + 19 + 1 + write-only + + + P20 + Pull Down Enable + 20 + 1 + write-only + + + P21 + Pull Down Enable + 21 + 1 + write-only + + + P22 + Pull Down Enable + 22 + 1 + write-only + + + P23 + Pull Down Enable + 23 + 1 + write-only + + + P24 + Pull Down Enable + 24 + 1 + write-only + + + P25 + Pull Down Enable + 25 + 1 + write-only + + + P26 + Pull Down Enable + 26 + 1 + write-only + + + P27 + Pull Down Enable + 27 + 1 + write-only + + + P28 + Pull Down Enable + 28 + 1 + write-only + + + P29 + Pull Down Enable + 29 + 1 + write-only + + + P30 + Pull Down Enable + 30 + 1 + write-only + + + P31 + Pull Down Enable + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status + 0 + 1 + read-only + + + P1 + Pull Down Status + 1 + 1 + read-only + + + P2 + Pull Down Status + 2 + 1 + read-only + + + P3 + Pull Down Status + 3 + 1 + read-only + + + P4 + Pull Down Status + 4 + 1 + read-only + + + P5 + Pull Down Status + 5 + 1 + read-only + + + P6 + Pull Down Status + 6 + 1 + read-only + + + P7 + Pull Down Status + 7 + 1 + read-only + + + P8 + Pull Down Status + 8 + 1 + read-only + + + P9 + Pull Down Status + 9 + 1 + read-only + + + P10 + Pull Down Status + 10 + 1 + read-only + + + P11 + Pull Down Status + 11 + 1 + read-only + + + P12 + Pull Down Status + 12 + 1 + read-only + + + P13 + Pull Down Status + 13 + 1 + read-only + + + P14 + Pull Down Status + 14 + 1 + read-only + + + P15 + Pull Down Status + 15 + 1 + read-only + + + P16 + Pull Down Status + 16 + 1 + read-only + + + P17 + Pull Down Status + 17 + 1 + read-only + + + P18 + Pull Down Status + 18 + 1 + read-only + + + P19 + Pull Down Status + 19 + 1 + read-only + + + P20 + Pull Down Status + 20 + 1 + read-only + + + P21 + Pull Down Status + 21 + 1 + read-only + + + P22 + Pull Down Status + 22 + 1 + read-only + + + P23 + Pull Down Status + 23 + 1 + read-only + + + P24 + Pull Down Status + 24 + 1 + read-only + + + P25 + Pull Down Status + 25 + 1 + read-only + + + P26 + Pull Down Status + 26 + 1 + read-only + + + P27 + Pull Down Status + 27 + 1 + read-only + + + P28 + Pull Down Status + 28 + 1 + read-only + + + P29 + Pull Down Status + 29 + 1 + read-only + + + P30 + Pull Down Status + 30 + 1 + read-only + + + P31 + Pull Down Status + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable + 0 + 1 + write-only + + + P1 + Output Write Enable + 1 + 1 + write-only + + + P2 + Output Write Enable + 2 + 1 + write-only + + + P3 + Output Write Enable + 3 + 1 + write-only + + + P4 + Output Write Enable + 4 + 1 + write-only + + + P5 + Output Write Enable + 5 + 1 + write-only + + + P6 + Output Write Enable + 6 + 1 + write-only + + + P7 + Output Write Enable + 7 + 1 + write-only + + + P8 + Output Write Enable + 8 + 1 + write-only + + + P9 + Output Write Enable + 9 + 1 + write-only + + + P10 + Output Write Enable + 10 + 1 + write-only + + + P11 + Output Write Enable + 11 + 1 + write-only + + + P12 + Output Write Enable + 12 + 1 + write-only + + + P13 + Output Write Enable + 13 + 1 + write-only + + + P14 + Output Write Enable + 14 + 1 + write-only + + + P15 + Output Write Enable + 15 + 1 + write-only + + + P16 + Output Write Enable + 16 + 1 + write-only + + + P17 + Output Write Enable + 17 + 1 + write-only + + + P18 + Output Write Enable + 18 + 1 + write-only + + + P19 + Output Write Enable + 19 + 1 + write-only + + + P20 + Output Write Enable + 20 + 1 + write-only + + + P21 + Output Write Enable + 21 + 1 + write-only + + + P22 + Output Write Enable + 22 + 1 + write-only + + + P23 + Output Write Enable + 23 + 1 + write-only + + + P24 + Output Write Enable + 24 + 1 + write-only + + + P25 + Output Write Enable + 25 + 1 + write-only + + + P26 + Output Write Enable + 26 + 1 + write-only + + + P27 + Output Write Enable + 27 + 1 + write-only + + + P28 + Output Write Enable + 28 + 1 + write-only + + + P29 + Output Write Enable + 29 + 1 + write-only + + + P30 + Output Write Enable + 30 + 1 + write-only + + + P31 + Output Write Enable + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable + 0 + 1 + write-only + + + P1 + Output Write Disable + 1 + 1 + write-only + + + P2 + Output Write Disable + 2 + 1 + write-only + + + P3 + Output Write Disable + 3 + 1 + write-only + + + P4 + Output Write Disable + 4 + 1 + write-only + + + P5 + Output Write Disable + 5 + 1 + write-only + + + P6 + Output Write Disable + 6 + 1 + write-only + + + P7 + Output Write Disable + 7 + 1 + write-only + + + P8 + Output Write Disable + 8 + 1 + write-only + + + P9 + Output Write Disable + 9 + 1 + write-only + + + P10 + Output Write Disable + 10 + 1 + write-only + + + P11 + Output Write Disable + 11 + 1 + write-only + + + P12 + Output Write Disable + 12 + 1 + write-only + + + P13 + Output Write Disable + 13 + 1 + write-only + + + P14 + Output Write Disable + 14 + 1 + write-only + + + P15 + Output Write Disable + 15 + 1 + write-only + + + P16 + Output Write Disable + 16 + 1 + write-only + + + P17 + Output Write Disable + 17 + 1 + write-only + + + P18 + Output Write Disable + 18 + 1 + write-only + + + P19 + Output Write Disable + 19 + 1 + write-only + + + P20 + Output Write Disable + 20 + 1 + write-only + + + P21 + Output Write Disable + 21 + 1 + write-only + + + P22 + Output Write Disable + 22 + 1 + write-only + + + P23 + Output Write Disable + 23 + 1 + write-only + + + P24 + Output Write Disable + 24 + 1 + write-only + + + P25 + Output Write Disable + 25 + 1 + write-only + + + P26 + Output Write Disable + 26 + 1 + write-only + + + P27 + Output Write Disable + 27 + 1 + write-only + + + P28 + Output Write Disable + 28 + 1 + write-only + + + P29 + Output Write Disable + 29 + 1 + write-only + + + P30 + Output Write Disable + 30 + 1 + write-only + + + P31 + Output Write Disable + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status + 0 + 1 + read-only + + + P1 + Output Write Status + 1 + 1 + read-only + + + P2 + Output Write Status + 2 + 1 + read-only + + + P3 + Output Write Status + 3 + 1 + read-only + + + P4 + Output Write Status + 4 + 1 + read-only + + + P5 + Output Write Status + 5 + 1 + read-only + + + P6 + Output Write Status + 6 + 1 + read-only + + + P7 + Output Write Status + 7 + 1 + read-only + + + P8 + Output Write Status + 8 + 1 + read-only + + + P9 + Output Write Status + 9 + 1 + read-only + + + P10 + Output Write Status + 10 + 1 + read-only + + + P11 + Output Write Status + 11 + 1 + read-only + + + P12 + Output Write Status + 12 + 1 + read-only + + + P13 + Output Write Status + 13 + 1 + read-only + + + P14 + Output Write Status + 14 + 1 + read-only + + + P15 + Output Write Status + 15 + 1 + read-only + + + P16 + Output Write Status + 16 + 1 + read-only + + + P17 + Output Write Status + 17 + 1 + read-only + + + P18 + Output Write Status + 18 + 1 + read-only + + + P19 + Output Write Status + 19 + 1 + read-only + + + P20 + Output Write Status + 20 + 1 + read-only + + + P21 + Output Write Status + 21 + 1 + read-only + + + P22 + Output Write Status + 22 + 1 + read-only + + + P23 + Output Write Status + 23 + 1 + read-only + + + P24 + Output Write Status + 24 + 1 + read-only + + + P25 + Output Write Status + 25 + 1 + read-only + + + P26 + Output Write Status + 26 + 1 + read-only + + + P27 + Output Write Status + 27 + 1 + read-only + + + P28 + Output Write Status + 28 + 1 + read-only + + + P29 + Output Write Status + 29 + 1 + read-only + + + P30 + Output Write Status + 30 + 1 + read-only + + + P31 + Output Write Status + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status + 0 + 1 + read-only + + + P1 + Peripheral CD Status + 1 + 1 + read-only + + + P2 + Peripheral CD Status + 2 + 1 + read-only + + + P3 + Peripheral CD Status + 3 + 1 + read-only + + + P4 + Peripheral CD Status + 4 + 1 + read-only + + + P5 + Peripheral CD Status + 5 + 1 + read-only + + + P6 + Peripheral CD Status + 6 + 1 + read-only + + + P7 + Peripheral CD Status + 7 + 1 + read-only + + + P8 + Peripheral CD Status + 8 + 1 + read-only + + + P9 + Peripheral CD Status + 9 + 1 + read-only + + + P10 + Peripheral CD Status + 10 + 1 + read-only + + + P11 + Peripheral CD Status + 11 + 1 + read-only + + + P12 + Peripheral CD Status + 12 + 1 + read-only + + + P13 + Peripheral CD Status + 13 + 1 + read-only + + + P14 + Peripheral CD Status + 14 + 1 + read-only + + + P15 + Peripheral CD Status + 15 + 1 + read-only + + + P16 + Peripheral CD Status + 16 + 1 + read-only + + + P17 + Peripheral CD Status + 17 + 1 + read-only + + + P18 + Peripheral CD Status + 18 + 1 + read-only + + + P19 + Peripheral CD Status + 19 + 1 + read-only + + + P20 + Peripheral CD Status + 20 + 1 + read-only + + + P21 + Peripheral CD Status + 21 + 1 + read-only + + + P22 + Peripheral CD Status + 22 + 1 + read-only + + + P23 + Peripheral CD Status + 23 + 1 + read-only + + + P24 + Peripheral CD Status + 24 + 1 + read-only + + + P25 + Peripheral CD Status + 25 + 1 + read-only + + + P26 + Peripheral CD Status + 26 + 1 + read-only + + + P27 + Peripheral CD Status + 27 + 1 + read-only + + + P28 + Peripheral CD Status + 28 + 1 + read-only + + + P29 + Peripheral CD Status + 29 + 1 + read-only + + + P30 + Peripheral CD Status + 30 + 1 + read-only + + + P31 + Peripheral CD Status + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Level Interrupt Selection + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt Source Selection + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY. + 8 + 24 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. + 0x50494F + + + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + Schmitt Trigger Control + 0 + 1 + read-write + + + SCHMITT1 + Schmitt Trigger Control + 1 + 1 + read-write + + + SCHMITT2 + Schmitt Trigger Control + 2 + 1 + read-write + + + SCHMITT3 + Schmitt Trigger Control + 3 + 1 + read-write + + + SCHMITT4 + Schmitt Trigger Control + 4 + 1 + read-write + + + SCHMITT5 + Schmitt Trigger Control + 5 + 1 + read-write + + + SCHMITT6 + Schmitt Trigger Control + 6 + 1 + read-write + + + SCHMITT7 + Schmitt Trigger Control + 7 + 1 + read-write + + + SCHMITT8 + Schmitt Trigger Control + 8 + 1 + read-write + + + SCHMITT9 + Schmitt Trigger Control + 9 + 1 + read-write + + + SCHMITT10 + Schmitt Trigger Control + 10 + 1 + read-write + + + SCHMITT11 + Schmitt Trigger Control + 11 + 1 + read-write + + + SCHMITT12 + Schmitt Trigger Control + 12 + 1 + read-write + + + SCHMITT13 + Schmitt Trigger Control + 13 + 1 + read-write + + + SCHMITT14 + Schmitt Trigger Control + 14 + 1 + read-write + + + SCHMITT15 + Schmitt Trigger Control + 15 + 1 + read-write + + + SCHMITT16 + Schmitt Trigger Control + 16 + 1 + read-write + + + SCHMITT17 + Schmitt Trigger Control + 17 + 1 + read-write + + + SCHMITT18 + Schmitt Trigger Control + 18 + 1 + read-write + + + SCHMITT19 + Schmitt Trigger Control + 19 + 1 + read-write + + + SCHMITT20 + Schmitt Trigger Control + 20 + 1 + read-write + + + SCHMITT21 + Schmitt Trigger Control + 21 + 1 + read-write + + + SCHMITT22 + Schmitt Trigger Control + 22 + 1 + read-write + + + SCHMITT23 + Schmitt Trigger Control + 23 + 1 + read-write + + + SCHMITT24 + Schmitt Trigger Control + 24 + 1 + read-write + + + SCHMITT25 + Schmitt Trigger Control + 25 + 1 + read-write + + + SCHMITT26 + Schmitt Trigger Control + 26 + 1 + read-write + + + SCHMITT27 + Schmitt Trigger Control + 27 + 1 + read-write + + + SCHMITT28 + Schmitt Trigger Control + 28 + 1 + read-write + + + SCHMITT29 + Schmitt Trigger Control + 29 + 1 + read-write + + + SCHMITT30 + Schmitt Trigger Control + 30 + 1 + read-write + + + SCHMITT31 + Schmitt Trigger Control + 31 + 1 + read-write + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452S + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts the vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Internal voltage regulator is not used (external power supply is used) + 0 + + + ONREG_USED + internal voltage regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + WUMR + Supply Controller Wake-up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake-up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake-up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake-up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake-up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake-up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake-up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake-up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake-up of the core power supply. + 1 + + + + + WKUPDBC + Wake-up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + + + WUIR + Supply Controller Wake-up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake-up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN1 + Wake-up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN2 + Wake-up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN3 + Wake-up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN4 + Wake-up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN5 + Wake-up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN6 + Wake-up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN7 + Wake-up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN8 + Wake-up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN9 + Wake-up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN10 + Wake-up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN11 + Wake-up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN12 + Wake-up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN13 + Wake-up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN14 + Wake-up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPEN15 + Wake-up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake-up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT0 + Wake-up Input Type 0 + 16 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT1 + Wake-up Input Type 1 + 17 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT2 + Wake-up Input Type 2 + 18 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT3 + Wake-up Input Type 3 + 19 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT4 + Wake-up Input Type 4 + 20 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT5 + Wake-up Input Type 5 + 21 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT6 + Wake-up Input Type 6 + 22 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT7 + Wake-up Input Type 7 + 23 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT8 + Wake-up Input Type 8 + 24 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT9 + Wake-up Input Type 9 + 25 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT10 + Wake-up Input Type 10 + 26 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT11 + Wake-up Input Type 11 + 27 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT12 + Wake-up Input Type 12 + 28 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT13 + Wake-up Input Type 13 + 29 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT14 + Wake-up Input Type 14 + 30 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + WKUPT15 + Wake-up Input Type 15 + 31 + 1 + read-write + + + HIGH_TO_LOW + a high to low level transition for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply. + 0 + + + LOW_TO_HIGH + a low to high level transition for a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake-up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000000 + + + WKUPS + WKUP Wake-up Status + 1 + 1 + read-only + + + NO + no wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake-up Status + 2 + 1 + read-only + + + NO + no wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake-up event. + 1 + + + + + + + + + RTT + 6081H + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080F + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password. + 24 + 8 + write-only + + + PASSWD + Writing any other value in this field aborts the write operation. + 0xA5 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056N + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Registers + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3s/templates/library.c b/zephyr/ports/asf/sam3s/templates/library.c new file mode 100644 index 0000000..369a571 --- /dev/null +++ b/zephyr/ports/asf/sam3s/templates/library.c @@ -0,0 +1,15 @@ +/* + * $projectname$.c + * + * Created: $date$ + * Author : $user$ + */ + +#include "sam.h" + + +/* Replace with your library code */ +int myfunc(void) +{ + return 0; +} diff --git a/zephyr/ports/asf/sam3s/templates/library.cpp b/zephyr/ports/asf/sam3s/templates/library.cpp new file mode 100644 index 0000000..e4a6991 --- /dev/null +++ b/zephyr/ports/asf/sam3s/templates/library.cpp @@ -0,0 +1,15 @@ +/* + * $projectname$.cpp + * + * Created: $date$ + * Author : $user$ + */ + +#include "sam.h" + + +/* Replace with your library code */ +int myfunc(void) +{ + return 0; +} diff --git a/zephyr/ports/asf/sam3s/templates/main.c b/zephyr/ports/asf/sam3s/templates/main.c new file mode 100644 index 0000000..95f1b43 --- /dev/null +++ b/zephyr/ports/asf/sam3s/templates/main.c @@ -0,0 +1,21 @@ +/* + * $projectname$.c + * + * Created: $date$ + * Author : $user$ + */ + + +#include "sam.h" + + +int main(void) +{ + /* Initialize the SAM system */ + SystemInit(); + + /* Replace with your application code */ + while (1) + { + } +} diff --git a/zephyr/ports/asf/sam3s/templates/main.cpp b/zephyr/ports/asf/sam3s/templates/main.cpp new file mode 100644 index 0000000..fd8a7b8 --- /dev/null +++ b/zephyr/ports/asf/sam3s/templates/main.cpp @@ -0,0 +1,21 @@ +/* + * $projectname$.cpp + * + * Created: $date$ + * Author : $user$ + */ + + +#include "sam.h" + + +int main(void) +{ + /* Initialize the SAM system */ + SystemInit(); + + /* Replace with your application code */ + while (1) + { + } +} diff --git a/zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/ARM/startup_SAM3SD8.s b/zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/ARM/startup_SAM3SD8.s new file mode 100644 index 0000000..797effb --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/ARM/startup_SAM3SD8.s @@ -0,0 +1,271 @@ +;/***************************************************************************** +; * @file: startup_SAM3SD8.s +; * @purpose: CMSIS Cortex-M3 Core Device Startup File +; * for the Atmel SAM3SD8 Device Series +; * @version: V1.20 +; * @date: 14. December 2015 +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; * Copyright (C) 2011-213 ARM Limited. All rights reserved. +; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; *****************************************************************************/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + +__Vectors DCD __initial_sp ; 0: Top of Stack + DCD Reset_Handler ; 1: Reset Handler + DCD NMI_Handler ; 2: NMI Handler + DCD HardFault_Handler ; 3: Hard Fault Handler + DCD MemManage_Handler ; 4: MPU Fault Handler + DCD BusFault_Handler ; 5: Bus Fault Handler + DCD UsageFault_Handler ; 6: Usage Fault Handler + DCD 0 ; 7: Reserved + DCD 0 ; 8: Reserved + DCD 0 ; 9: Reserved + DCD 0 ; 10: Reserved + DCD SVC_Handler ; 11: SVCall Handler + DCD DebugMon_Handler ; 12: Debug Monitor Handler + DCD 0 ; 13: Reserved + DCD PendSV_Handler ; 14: PendSV Handler + DCD SysTick_Handler ; 15: SysTick Handler + + ; External Interrupts + DCD SUPC_IRQHandler ; 0: Supply Controller + DCD RSTC_IRQHandler ; 1: Reset Controller + DCD RTC_IRQHandler ; 2: Real Time Clock + DCD RTT_IRQHandler ; 3: Real Time Timer + DCD WDT_IRQHandler ; 4: Watchdog Timer + DCD PMC_IRQHandler ; 5: Power Management Controller + DCD EEFC_IRQHandler ; 6: Enhanced Embedded Flash Controller + DCD 0 ; 7: Reserved + DCD UART0_IRQHandler ; 8: UART0 + DCD UART1_IRQHandler ; 9: UART1 + DCD 0 ; 10: Reserved + DCD PIOA_IRQHandler ; 11: Parallel I/O Controller A + DCD PIOB_IRQHandler ; 12: Parallel I/O Controller B + DCD PIOC_IRQHandler ; 13: Parallel I/O Controller C + DCD USART0_IRQHandler ; 14: USART 0 + DCD USART1_IRQHandler ; 15: USART 1 + DCD USART2_IRQHandler ; 16: USART 2 + DCD 0 ; 17: Reserved + DCD HSMCI_IRQHandler ; 18: Multimedia Card Interface + DCD TWI0_IRQHandler ; 19: Two Wire Interface 0 + DCD TWI1_IRQHandler ; 20: Two Wire Interface 1 + DCD SPI_IRQHandler ; 21: Serial Peripheral Interface + DCD SSC_IRQHandler ; 22: Synchronous Serial Controller + DCD TC0_IRQHandler ; 23: Timer/Counter 0 + DCD TC1_IRQHandler ; 24: Timer/Counter 1 + DCD TC2_IRQHandler ; 25: Timer/Counter 2 + DCD TC3_IRQHandler ; 26: Timer/Counter 3 + DCD TC4_IRQHandler ; 27: Timer/Counter 4 + DCD TC5_IRQHandler ; 28: Timer/Counter 5 + DCD ADC_IRQHandler ; 29: Analog-to-Digital Converter + DCD DACC_IRQHandler ; 30: Digital-to-Analog Converter + DCD PWM_IRQHandler ; 31: Pulse Width Modulation + DCD CRCCU_IRQHandler ; 32: CRC Calculation Unit + DCD ACC_IRQHandler ; 33: Analog Comparator + DCD UDP_IRQHandler ; 34: USB Device Port + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT SUPC_IRQHandler [WEAK] + EXPORT RSTC_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTT_IRQHandler [WEAK] + EXPORT WDT_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT EEFC_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT SMC_IRQHandler [WEAK] + EXPORT PIOA_IRQHandler [WEAK] + EXPORT PIOB_IRQHandler [WEAK] + EXPORT PIOC_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT HSMCI_IRQHandler [WEAK] + EXPORT TWI0_IRQHandler [WEAK] + EXPORT TWI1_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT SSC_IRQHandler [WEAK] + EXPORT TC0_IRQHandler [WEAK] + EXPORT TC1_IRQHandler [WEAK] + EXPORT TC2_IRQHandler [WEAK] + EXPORT TC3_IRQHandler [WEAK] + EXPORT TC4_IRQHandler [WEAK] + EXPORT TC5_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT DACC_IRQHandler [WEAK] + EXPORT PWM_IRQHandler [WEAK] + EXPORT CRCCU_IRQHandler [WEAK] + EXPORT ACC_IRQHandler [WEAK] + EXPORT UDP_IRQHandler [WEAK] + +SUPC_IRQHandler +RSTC_IRQHandler +RTC_IRQHandler +RTT_IRQHandler +WDT_IRQHandler +PMC_IRQHandler +EEFC_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +SMC_IRQHandler +PIOA_IRQHandler +PIOB_IRQHandler +PIOC_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +HSMCI_IRQHandler +TWI0_IRQHandler +TWI1_IRQHandler +SPI_IRQHandler +SSC_IRQHandler +TC0_IRQHandler +TC1_IRQHandler +TC2_IRQHandler +TC3_IRQHandler +TC4_IRQHandler +TC5_IRQHandler +ADC_IRQHandler +DACC_IRQHandler +PWM_IRQHandler +CRCCU_IRQHandler +ACC_IRQHandler +UDP_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/system_SAM3SD8.c b/zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/system_SAM3SD8.c new file mode 100644 index 0000000..93dbd36 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/armcc/Device/SAM3SD8/Source/system_SAM3SD8.c @@ -0,0 +1,570 @@ +/**************************************************************************//** + * @file system_SAM3SD8.c + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File + * for the Atmel SAM3SD8 Device Series + * @version V1.10 + * @date 16. April 2013 + * + * @note + * Copyright (C) 2011-2013 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#include + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + +/*--------------------- Embedded Flash Controllers Configuration ------------- +// +// Embedded Flash Controller (EEFC) +// FWS: Flash Wait State <1-16><#-1> +// FAM: Flash Access Mode +// <0=> 128-bit in read mode (enhance speed) +// <1=> 64-bit in read mode (enhance power consumption) +// +*/ +#define EEFC_SETUP 1 // Reset values: +#define EEFC_FMR_Val 0x00000200 // 0x00000000 + + +/*--------------------- Power Management Controller Configuration ------------ +// +// Power Management Controller (PMC) +// System Clock Enable Register (PMC_SCER) +// UDP: USB Device Port Clock Enable +// PCK0: Programmable Clock 0 Output Enable +// PCK1: Programmable Clock 1 Output Enable +// PCK2: Programmable Clock 2 Output Enable +// +// +// Peripheral Clock Enable Register 0 (PMC_PCER0) +// PID2: Real Time Clock Clock Enable +// PID3: Real Time Timer Clock Enable +// PID4: Watchdog Timer Clock Enable +// PID5: Power Management Controller Clock Enable +// PID6: Enhanced Embedded Flash Controller Clock Enable +// PID8: UART 0 Clock Enable +// PID9: UART 1 Clock Enable Clock Enable +// PID10: Static Memory Controller Clock Enable +// PID11: Parallel I/O Controller A Clock Enable +// PID12: Parallel I/O Controller B Clock Enable +// PID13: Parallel I/O Controller C Clock Enable +// PID14: USART 0 Clock Enable +// PID15: USART 1 Clock Enable +// PID16: USART 2 Clock Enable +// PID18: Multimedia Card Interface Clock Enable +// PID19: Two-wire Interface 0 Clock Enable +// PID20: Two-wire Interface 1 Clock Enable +// PID21: Serial Peripheral Interface Clock Enable +// PID22: Synchronous Serial Controller Clock Enable +// PID23: Timer Counter 0 Clock Enable +// PID24: Timer Counter 1 Clock Enable +// PID25: Timer Counter 2 Clock Enable +// PID26: Timer Counter 3 Clock Enable +// PID27: Timer Counter 4 Clock Enable +// PID28: Timer Counter 5 Clock Enable +// PID29: Analog-to-Digital Converter Clock Enable +// PID30: Digital-to-Analog Converter Clock Enable +// PID31: Pulse Width Modulation Clock Enable +// +// +// Peripheral Clock Enable Register 1 (PMC_PCER1) +// PID32: CRC Calculation Unit Clock Enable +// PID33: Analog Comparator Clock Enable +// PID34: USB Device Port Clock Enable +// +// +// Main Oscillator Register (CKGR_MOR) +// MOSCXTEN: Main Crystal Oscillator Enable +// MOSCXTBY: Main Crystal Oscillator Bypass +// WAITMODE: Wait Mode Command +// MOSCRCEN: Main On-chip RC Oscillator Enable +// MOSCRCF: Main On-chip RC Oscillator Frequency Selection +// <0=> 4MHz <1=> 8 MHz <2=> 12 MHz <3=> Reserved +// MOSCXTST: Main Crystal Oscillator Startup Time <0-255> +// MOSCSEL: Main Oscillator Selection +// <0=> Main On-chip RC Oscillator <1=> Main Crystal Oscillator +// CFDEN: Clock Failure Detector Enable +// +// +// Clock Generator Phase Locked Loop A Register (CKGR_PLLAR) +// PLL A Freq = (Main CLOCK Freq / DIVA) * (MULA + 1) +// Example: XTAL = 12 MHz, DIVA = 1, MULA = 14 => PLLA = 168 MHz +// DIVA: PLL Divider A <0-255> +// 0 - Divider output is 0 +// 1 - Divider is bypassed +// 2 .. 255 - Divider output is the Main Clock divided by DIVA +// PLLACOUNT: PLL A Counter <0-63> +// Number of Slow Clocks before the LOCKA bit is set in +// PMC_SR after CKGR_PLLAR is written +// MULA: PLL A Multiplier <0-2047> +// 0 - The PLL A is deactivated +// 1 .. 2047 - The PLL A Clock frequency is the PLLA input +// frequency multiplied by MULA + 1 +// +// +// Clock Generator Phase Locked Loop B Register (CKGR_PLLBR) +// PLL B Freq = (Main CLOCK Freq / DIVB) * (MULB + 1) +// Example: XTAL = 12 MHz, DIVB = 1, MULB = 14 => PLLB = 168 MHz +// DIVB: PLL Divider B <0-255> +// 0 - Divider output is 0 +// 1 - Divider is bypassed +// 2 .. 255 - Divider output is the Main Clock divided by DIVB +// PLLBCOUNT: PLL B Counter <0-63> +// Number of Slow Clocks before the LOCKB bit is set in +// PMC_SR after CKGR_PLLBR is written +// MULB: PLL B Multiplier <0-2047> +// 0 - The PLL B is deactivated +// 1 .. 2047 - The PLL B Clock frequency is the PLLB input +// frequency multiplied by MULB + 1 +// +// +// Master Clock Register (PMC_MCKR) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLL A Clock +// <3=> PLL B Clock +// PRES: Master Clock Prescaler +// <0=> Clock <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Clock / 3 +// PLLADIV2: PLLA Divisor by 2 +// PLLBDIV2: PLLB Divisor by 2 +// +// +// USB Clock Register (PMC_USB) +// USBS: USB Input Clock Selection +// <0=> PLLA Clock +// <1=> PLLB Clock +// USBDIV: USB Input Clock Devider <0-15> +// USB Clock is Input clock divided by USBDIV+1 +// +// +// Programmable Clock Register 0 (PMC_PCK0) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLLA Clock +// <3=> PLLB Clock +// <4=> Master Clock +// <5=> Master Clock +// <6=> Master Clock +// <7=> Master Clock +// PRES: Programmable Clock Prescaler +// <0=> Clock <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Reserved +// +// +// Programmable Clock Register 1 (PMC_PCK1) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLLA Clock +// <3=> PLLB Clock +// <4=> Master Clock +// <5=> Master Clock +// <6=> Master Clock +// <7=> Master Clock +// PRES: Programmable Clock Prescaler +// <0=> None <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Reserved +// +// +// Programmable Clock Register 2 (PMC_PCK2) +// CSS: Master Clock Selection +// <0=> Slow Clock +// <1=> Main Clock +// <2=> PLLA Clock +// <3=> PLLB Clock +// <4=> Master Clock +// <5=> Master Clock +// <6=> Master Clock +// <7=> Master Clock +// PRES: Programmable Clock Prescaler +// <0=> None <1=> Clock / 2 +// <2=> Clock / 4 <3=> Clock / 8 +// <4=> Clock / 16 <5=> Clock / 32 +// <6=> Clock / 64 <7=> Reserved +// +// +*/ +#define PMC_SETUP 1 // Reset values: +#define PMC_SCER_Val 0x00000000 // WO register (0x00000001) +#define PMC_PCER0_Val 0x00000000 // WO register (0x00000000) +#define PMC_PCER1_Val 0x00001C00 // WO register (0x00000000) +#define CKGR_MOR_Val 0x01370F01 // 0x00000001 +#define CKGR_PLLAR_Val 0x201F0603 // 0x00003F00 +#define CKGR_PLLBR_Val 0x20170603 // 0x00003F00 +#define PMC_MCKR_Val 0x00000012 // 0x00000001 +#define PMC_USB_Val 0x00000101 // 0x00000000 +#define PMC_PCK0_Val 0x00000000 // 0x00000000 +#define PMC_PCK1_Val 0x00000000 // 0x00000000 +#define PMC_PCK2_Val 0x00000000 // 0x00000000 + + +/*--------------------- Watchdog Configuration ------------------------------- +// +// Watchdog Disable +// +*/ +#define WDT_SETUP 1 // Reset values: + + +/* +//-------- <<< end of configuration section >>> ------------------------------ +*/ + +/*---------------------------------------------------------------------------- + Check the register settings + *----------------------------------------------------------------------------*/ +#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) +#define CHECK_RSVD(val, mask) (val & mask) + +/* Embedded Flash Controllers Configuration ----------------------------------*/ +#if (CHECK_RSVD((EEFC_FMR_Val), ~0x01000F01)) + #error "EEFC_FMR: Invalid values of reserved bits!" +#endif + +/* Power Management Controller Configuration ---------------------------------*/ +#if (CHECK_RSVD((PMC_SCER_Val), ~0x00000780)) + #error "PMC_SCER: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCER0_Val), ~0xFFFFFFFC)) + #error "PMC_PCER0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCER1_Val), ~0xFFFFFFFF)) + #error "PMC_PCER1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CKGR_MOR_Val), ~0x03FFFF7F)) + #error "CKGR_MOR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CKGR_PLLAR_Val), ~0x27FFFFFF)) + #error "CKGR_PLLAR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((CKGR_PLLBR_Val), ~0x27FF3FFF)) + #error "CKGR_PLLBR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_MCKR_Val), ~0x00003073)) + #error "PMC_MCKR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_USB_Val), ~0x00000F01)) + #error "PMC_USB: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCK0_Val), ~0x00000077)) + #error "PMC_PCK0: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCK1_Val), ~0x00000077)) + #error "PMC_PCK1: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((PMC_PCK2_Val), ~0x00000077)) + #error "PMC_PCK2: Invalid values of reserved bits!" +#endif + + +/*---------------------------------------------------------------------------- + DEFINES + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (12000000UL) /* Crystal frequency */ +#define XTAL32 ( 32768UL) /* 32k crystal frequency */ +#define OSC_CLK ( XTAL) /* Main oscillator frequency */ +#define OSC32_CLK ( XTAL32) /* 32k oscillator frequency */ +#define ERC_OSC ( 32000UL) /* Embedded RC oscillator freqquency */ +#define EFRC_OSC ( 4000000UL) /* Embedded fast RC oscillator freq */ + + + +#if (PMC_SETUP) + /* Determine clock frequency according to clock register values */ + #if ((PMC_MCKR_Val & 3) == 0) /* Slow Clock is selected */ + #if (1 /* PMC_SR & (1 << 7) */) /* MUST be checked with correct register */ + #define __CORE_CLK_PRE (OSC32_CLK) + #else + #define __CORE_CLK_PRE (ERC_OSC) + #endif + #elif ((PMC_MCKR_Val & 3) == 1) /* Main Clock is selected */ + #if (CKGR_MOR_Val & (1 << 24)) + #if ((CKGR_MOR_Val & (1<< 0)) == 0) + #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!" + #endif + #define __CORE_CLK_PRE (OSC_CLK) + #else + #if ((CKGR_MOR_Val & (1<< 3)) == 0) + #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!" + #endif + #if (((CKGR_MOR_Val >> 4) & 3) == 0) + #define __CORE_CLK_PRE (EFRC_OSC) + #elif (((CKGR_MOR_Val >> 4) & 3) == 1) + #define __CORE_CLK_PRE (EFRC_OSC * 2) + #elif (((CKGR_MOR_Val >> 4) & 3) == 2) + #define __CORE_CLK_PRE (EFRC_OSC * 3) + #else + #define __CORE_CLK_PRE (EFRC_OSC) + #endif + #endif + #elif ((PMC_MCKR_Val & 3) == 2) /* PLLA Clock is selected */ + #if (CKGR_MOR_Val & (1 << 24)) + #if ((CKGR_MOR_Val & (1<< 0)) == 0) + #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!" + #endif + #define __PLLA_CLK (OSC_CLK) + #else + #if ((CKGR_MOR_Val & (1<< 3)) == 0) + #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!" + #endif + #if (((CKGR_MOR_Val >> 4) & 3) == 0) + #define __PLLA_CLK (EFRC_OSC) + #elif (((CKGR_MOR_Val >> 4) & 3) == 1) + #define __PLLA_CLK (EFRC_OSC * 2) + #elif (((CKGR_MOR_Val >> 4) & 3) == 2) + #define __PLLA_CLK (EFRC_OSC * 3) + #else + #define __PLLA_CLK (EFRC_OSC) + #endif + #endif + + #define __PLLA_MUL ((((CKGR_PLLAR_Val) >> 16) & 0x7FF) + 1) + #define __PLLA_DIV ((((CKGR_PLLAR_Val) >> 0) & 0x0FF)) + #define __CORE_CLK_PRE (__PLLA_CLK * __PLLA_MUL / __PLLA_DIV) + #else /* PLLB Clock is selected */ + #if (CKGR_MOR_Val & (1 << 24)) + #if ((CKGR_MOR_Val & (1<< 0)) == 0) + #error "CKGR_MOR: Main Crystal Oscillator selected but not enabled!" + #endif + #define __PLLB_CLK (OSC_CLK) + #else + #if ((CKGR_MOR_Val & (1<< 3)) == 0) + #error "CKGR_MOR: Main On-Chip RC Oscillator selected but not enabled!" + #endif + #if (((CKGR_MOR_Val >> 4) & 3) == 0) + #define __PLLB_CLK (EFRC_OSC) + #elif (((CKGR_MOR_Val >> 4) & 3) == 1) + #define __PLLB_CLK (EFRC_OSC * 2) + #elif (((CKGR_MOR_Val >> 4) & 3) == 2) + #define __PLLB_CLK (EFRC_OSC * 3) + #else + #define __PLLB_CLK (EFRC_OSC) + #endif + #endif + + #define __PLLB_MUL ((((CKGR_PLLBR_Val) >> 16) & 0x7FF) + 1) + #define __PLLB_DIV ((((CKGR_PLLBR_Val) >> 0) & 0x0FF)) + #define __CORE_CLK_PRE (__PLLB_CLK * __PLLB_MUL / __PLLB_DIV) + #endif + + #if (((PMC_MCKR_Val >> 4) & 7) == 7) + #define __CORE_CLK (__CORE_CLK_PRE / 3) + #else + #define __CORE_CLK (__CORE_CLK_PRE >> ((PMC_MCKR_Val >> 4) & 7)) + #endif + +#else + #define __CORE_CLK (EFRC_OSC) +#endif + +#if (__CORE_CLK > 64000000UL) + #error "Core Clock > 64MHz!" +#endif + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ + + +/*---------------------------------------------------------------------------- + Clock functions + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & 3) { + case 0: /* Slow clock */ + if (SUPC->SUPC_SR & (1 << 7)) + SystemCoreClock = OSC32_CLK; + else + SystemCoreClock = ERC_OSC; + break; + case 1: /* Main clock */ + if (PMC->CKGR_MOR & (1 << 24)) + SystemCoreClock = OSC_CLK; + else { + SystemCoreClock = EFRC_OSC; + switch ((PMC->CKGR_MOR >> 4) & 3) { + case 0: + break; + case 1: + SystemCoreClock *= 2; + break; + case 2: + SystemCoreClock *= 3; + break; + case 3: + break; + } + } + break; + case 2: /* PLLA clock */ + if (PMC->CKGR_MOR & (1 << 24)) + SystemCoreClock = OSC_CLK; + else { + SystemCoreClock = EFRC_OSC; + switch ((PMC->CKGR_MOR >> 4) & 3) { + case 0: + break; + case 1: + SystemCoreClock *= 2; + break; + case 2: + SystemCoreClock *= 3; + break; + case 3: + break; + } + } + SystemCoreClock *= ((((PMC->CKGR_PLLAR) >> 16) & 0x7FF) + 1); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) >> 0) & 0x0FF)); + break; + case 3: /* PLLB clock */ + if (PMC->CKGR_MOR & (1 << 24)) + SystemCoreClock = OSC_CLK; + else { + SystemCoreClock = EFRC_OSC; + switch ((PMC->CKGR_MOR >> 4) & 3) { + case 0: + break; + case 1: + SystemCoreClock *= 2; + break; + case 2: + SystemCoreClock *= 3; + break; + case 3: + break; + } + } + SystemCoreClock *= ((((PMC->CKGR_PLLBR) >> 16) & 0x7FF) + 1); + SystemCoreClock /= ((((PMC->CKGR_PLLBR) >> 0) & 0x0FF)); + break; + } + + if (((PMC->PMC_MCKR >> 4) & 7) == 7) + SystemCoreClock /= 3; + else + SystemCoreClock >>= ((PMC->PMC_MCKR >> 4) & 7); + +} + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +void SystemInit (void) +{ +#if (EEFC_SETUP == 1) /* Embedded Flash Controller 0 Setup */ + EFC->EEFC_FMR = EEFC_FMR_Val; +#endif + +PMC->PMC_WPMR = 0x504D4300; /* Disable write protect */ + +#if (PMC_SETUP == 1) /* Power Management Controller Setup */ + +#if (CKGR_MOR_Val & ((1<<3)|(1<<0))) /* If MOSCRCEN or MOSCXTEN set */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & (1<<24)) | /* Keep the current MOSCSEL */ + (CKGR_MOR_Val & ~(1<<24)) | /* Set value except MOSCSEL */ + ((1<<3)|(1<<0)); /* and enable bothe OSC */ +#if (CKGR_MOR_Val & ((1 << 3))) + while (!(PMC->PMC_SR & (1 << 17))); /* Wait for MOSCRCS */ +#endif +#if (CKGR_MOR_Val & ((1 << 0))) + while (!(PMC->PMC_SR & (1 << 0))); /* Wait for MOSCXTS */ +#endif + PMC->CKGR_MOR = CKGR_MOR_Val; /* set the desired selection */ + while (!(PMC->PMC_SR & (1 << 16))); /* Wait for MOSCSELS */ +#endif + +#if (CKGR_PLLAR_Val & ((0x7FF<<16))) /* If MULA != 0 */ + PMC->CKGR_PLLAR = CKGR_PLLAR_Val | (1 << 29); + while (!(PMC->PMC_SR & (1 << 1))); /* Wait for LOCKA */ +#endif + +#if (CKGR_PLLBR_Val & ((0x7FF<<16))) /* If MULB != 0 */ + PMC->CKGR_PLLBR = CKGR_PLLBR_Val; + while (!(PMC->PMC_SR & (1 << 2))); /* Wait for LOCKB */ +#endif + + if ((PMC_MCKR_Val & 0x03) >= 2) { + /* Write PRES field only */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x70) | (PMC_MCKR_Val & 0x70); + } else { + /* Write CSS field only */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~0x03) | (PMC_MCKR_Val & 0x03); + } + while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */ + PMC->PMC_MCKR = PMC_MCKR_Val; /* Write all MCKR */ + while (!(PMC->PMC_SR & (1 << 3))); /* Wait for MCKRDY */ + +#if (PMC_PCK0_Val) + PMC->PMC_PCK[0] = PMC_PCK0_Val; /* Write PCK0 */ + while (!(PMC->PMC_SR & (1 << 8))); /* Wait for PCKRDY0 */ +#endif +#if (PMC_PCK1_Val) + PMC->PMC_PCK[1] = PMC_PCK1_Val; /* Write PCK1 */ + while (!(PMC->PMC_SR & (1 << 9))); /* Wait for PCKRDY1 */ +#endif +#if (PMC_PCK2_Val) + PMC->PMC_PCK[2] = PMC_PCK2_Val; /* Write PCK2 */ + while (!(PMC->PMC_SR & (1 << 10))); /* Wait for PCKRDY2 */ +#endif + + PMC->PMC_USB = PMC_USB_Val; + PMC->PMC_SCER = PMC_SCER_Val; + PMC->PMC_PCER0 = PMC_PCER0_Val; + PMC->PMC_PCER1 = PMC_PCER1_Val; +#endif + +PMC->PMC_WPMR = 0x504D4301; /* Enable write protect */ + +#if (WDT_SETUP == 1) /* Watchdog Setup */ + WDT->WDT_MR = WDT_MR_WDDIS; +#endif +} diff --git a/zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8B.atdf b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8B.atdf new file mode 100644 index 0000000..67694bb --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8B.atdf @@ -0,0 +1,7868 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8C.atdf b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8C.atdf new file mode 100644 index 0000000..b296c95 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3S8C.atdf @@ -0,0 +1,8074 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8B.atdf b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8B.atdf new file mode 100644 index 0000000..f5a34dd --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8B.atdf @@ -0,0 +1,7870 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8C.atdf b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8C.atdf new file mode 100644 index 0000000..e839a01 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/atdf/ATSAM3SD8C.atdf @@ -0,0 +1,8076 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_flash.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_flash.ld new file mode 100644 index 0000000..5e17100 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_flash.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S8B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_flash.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_sram.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_sram.ld new file mode 100644 index 0000000..f14170c --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8b_sram.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S8B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_sram.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_flash.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_flash.ld new file mode 100644 index 0000000..bd0b295 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_flash.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3S8C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_flash.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_sram.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_sram.ld new file mode 100644 index 0000000..d9d1b3f --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3s8c_sram.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3S8C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_sram.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_flash.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_flash.ld new file mode 100644 index 0000000..0b42920 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_flash.ld @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_sram.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_sram.ld new file mode 100644 index 0000000..a2e4d02 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8_sram.ld @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; +} diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_flash.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_flash.ld new file mode 100644 index 0000000..e9c5f9d --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_flash.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3SD8B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_flash.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_sram.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_sram.ld new file mode 100644 index 0000000..5b9e375 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8b_sram.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3SD8B + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_sram.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_flash.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_flash.ld new file mode 100644 index 0000000..c478bfe --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_flash.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAM3SD8C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_flash.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_sram.ld b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_sram.ld new file mode 100644 index 0000000..af092a8 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/sam3sd8c_sram.ld @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAM3SD8C + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x3000; + +INCLUDE sam3sd8_sram.ld diff --git a/zephyr/ports/asf/sam3sd8/gcc/gcc/startup_sam3sd8.c b/zephyr/ports/asf/sam3sd8/gcc/gcc/startup_sam3sd8.c new file mode 100644 index 0000000..dcc8942 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/gcc/startup_sam3sd8.c @@ -0,0 +1,232 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#include "sam3sd8.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M3 core handlers */ +void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void MemManage_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void BusFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UsageFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DebugMon_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void SUPC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RSTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void RTT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PMC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void EFC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOA_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PIOB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3SD8_PIOC_INSTANCE_ +void PIOC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3SD8_PIOC_INSTANCE_ */ +void USART0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void USART1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3SD8_USART2_INSTANCE_ +void USART2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3SD8_USART2_INSTANCE_ */ +void HSMCI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWI0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TWI1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SPI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void SSC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#ifdef _SAM3SD8_TC1_INSTANCE_ +void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3SD8_TC1_INSTANCE_ */ +#ifdef _SAM3SD8_TC1_INSTANCE_ +void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3SD8_TC1_INSTANCE_ */ +#ifdef _SAM3SD8_TC1_INSTANCE_ +void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +#endif /* _SAM3SD8_TC1_INSTANCE_ */ +void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void DACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void PWM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void CRCCU_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void ACC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); +void UDP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNMI_Handler = (void*) NMI_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManage_Handler = (void*) MemManage_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pfnReserved1_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved2_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved3_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved4_Handler = (void*) (0UL), /* Reserved */ + .pfnSVC_Handler = (void*) SVC_Handler, + .pfnDebugMon_Handler = (void*) DebugMon_Handler, + .pfnReserved5_Handler = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */ + .pvReserved7 = (void*) (0UL), /* 7 Reserved */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 8 UART 0 */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 9 UART 1 */ + .pvReserved10 = (void*) (0UL), /* 10 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 11 Parallel I/O Controller A */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 12 Parallel I/O Controller B */ +#ifdef _SAM3SD8_PIOC_INSTANCE_ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 13 Parallel I/O Controller C */ +#else + .pvReserved13 = (void*) (0UL), /* 13 Reserved */ +#endif /* _SAM3SD8_PIOC_INSTANCE_ */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 14 USART 0 */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 15 USART 1 */ +#ifdef _SAM3SD8_USART2_INSTANCE_ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 16 USART 2 (SAM3SD8 100 pins only) */ +#else + .pvReserved16 = (void*) (0UL), /* 16 Reserved */ +#endif /* _SAM3SD8_USART2_INSTANCE_ */ + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */ + .pfnTWI0_Handler = (void*) TWI0_Handler, /* 19 Two Wire Interface 0 */ + .pfnTWI1_Handler = (void*) TWI1_Handler, /* 20 Two Wire Interface 1 */ + .pfnSPI_Handler = (void*) SPI_Handler, /* 21 Serial Peripheral Interface */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controler */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */ +#ifdef _SAM3SD8_TC1_INSTANCE_ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif /* _SAM3SD8_TC1_INSTANCE_ */ +#ifdef _SAM3SD8_TC1_INSTANCE_ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif /* _SAM3SD8_TC1_INSTANCE_ */ +#ifdef _SAM3SD8_TC1_INSTANCE_ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif /* _SAM3SD8_TC1_INSTANCE_ */ + .pfnADC_Handler = (void*) ADC_Handler, /* 29 Analog To Digital Converter */ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */ + .pfnPWM_Handler = (void*) PWM_Handler, /* 31 Pulse Width Modulation */ + .pfnCRCCU_Handler = (void*) CRCCU_Handler, /* 32 CRC Calculation Unit */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */ + .pfnUDP_Handler = (void*) UDP_Handler /* 34 USB Device Port */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/zephyr/ports/asf/sam3sd8/gcc/system_sam3sd8.c b/zephyr/ports/asf/sam3sd8/gcc/system_sam3sd8.c new file mode 100644 index 0000000..27404fb --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/gcc/system_sam3sd8.c @@ -0,0 +1,237 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#include "sam3sd8.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* Clock settings (64MHz) */ +#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8UL)) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x1fUL) | CKGR_PLLAR_PLLACOUNT(0x3fUL) | CKGR_PLLAR_DIVA(0x3UL)) +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK) + +uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + +#ifndef CKGR_MOR_KEY_PASSWD +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) +#endif +/** + * \brief Setup the microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ +void SystemInit( void ) +{ + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC->EEFC_FMR = EEFC_FMR_FWS(3); + + /* Initialize main oscillator */ + if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) + { + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) + { + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) + { + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) + { + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) + { + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; + + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +} + +void SystemCoreClockUpdate( void ) +{ + /* Determine clock frequency according to clock register values */ + switch ( PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk ) + { + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_32K; + } + else + { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + } + break; + + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + break; + + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + case PMC_MCKR_CSS_PLLB_CLK: /* PLLB clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + + if ( (uint32_t)(PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) == PMC_MCKR_CSS_PLLA_CLK ) + { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos)); + } + else + { + SystemCoreClock *= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_MULB_Msk) >> CKGR_PLLBR_MULB_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLBR) & CKGR_PLLBR_DIVB_Msk) >> CKGR_PLLBR_DIVB_Pos)); + } + break; + + default: + break; + } + + if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 ) + { + SystemCoreClock /= 3U; + } + else + { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) >> PMC_MCKR_PRES_Pos); + } +} + +/** + * Initialize flash. + */ +void system_init_flash( uint32_t dw_clk ) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if ( dw_clk < CHIP_FREQ_FWS_0 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 0 ); + } + else + { + if ( dw_clk < CHIP_FREQ_FWS_1 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 1 ); + } + else + { + if ( dw_clk < CHIP_FREQ_FWS_2 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 2 ); + } + else + { + EFC->EEFC_FMR = EEFC_FMR_FWS( 3 ) ; + } + } + } +} + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/zephyr/ports/asf/sam3sd8/include/component-version.h b/zephyr/ports/asf/sam3sd8/include/component-version.h new file mode 100644 index 0000000..d54b32d --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component-version.h @@ -0,0 +1,72 @@ +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 0 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION +// is at least 8 digits long. +// +#define COMPONENT_VERSION 00010000 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 70 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.0" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2016-09-15 13:24:33" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/zephyr/ports/asf/sam3sd8/include/component/acc.h b/zephyr/ports/asf/sam3sd8/include/component/acc.h new file mode 100644 index 0000000..805bd8a --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/acc.h @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_ACC_COMPONENT_ +#define _SAM3SD8_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protect Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) SoftWare ReSeT */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) SELection for MINUS comparator input */ +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) SelectTS */ +#define ACC_MR_SELMINUS_ADVREF (0x1u << 0) /**< \brief (ACC_MR) Select ADVREF */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AD0 */ +#define ACC_MR_SELMINUS_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AD1 */ +#define ACC_MR_SELMINUS_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AD2 */ +#define ACC_MR_SELMINUS_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) SELection for PLUS comparator input */ +#define ACC_MR_SELPLUS_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AD0 */ +#define ACC_MR_SELPLUS_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AD1 */ +#define ACC_MR_SELPLUS_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AD2 */ +#define ACC_MR_SELPLUS_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AD3 */ +#define ACC_MR_SELPLUS_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AD4 */ +#define ACC_MR_SELPLUS_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AD5 */ +#define ACC_MR_SELPLUS_AD6 (0x6u << 4) /**< \brief (ACC_MR) Select AD6 */ +#define ACC_MR_SELPLUS_AD7 (0x7u << 4) /**< \brief (ACC_MR) Select AD7 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator ENable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog Comparator Disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) EDGE TYPe */ +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) INVert comparator output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog Comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog Comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) SELection of Fault Source */ +#define ACC_MR_SELFS_CF (0x0u << 13) /**< \brief (ACC_MR) the CF flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) the output of the Analog Comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) the FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) the FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current SELection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) low power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) high speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) HYSTeresis selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protect Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protect KEY */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protect Status Register -------- */ +#define ACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (ACC_WPSR) Write PROTection ERRor */ + +/*@}*/ + + +#endif /* _SAM3SD8_ACC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/adc.h b/zephyr/ports/asf/sam3sd8/include/component/adc.h new file mode 100644 index 0000000..c96b6c3 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/adc.h @@ -0,0 +1,509 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_ADC_COMPONENT_ +#define _SAM3SD8_ADC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog-to-Digital Converter */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_ADC Analog-to-Digital Converter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Adc hardware registers */ +typedef struct { + __O uint32_t ADC_CR; /**< \brief (Adc Offset: 0x00) Control Register */ + __IO uint32_t ADC_MR; /**< \brief (Adc Offset: 0x04) Mode Register */ + __IO uint32_t ADC_SEQR1; /**< \brief (Adc Offset: 0x08) Channel Sequence Register 1 */ + __IO uint32_t ADC_SEQR2; /**< \brief (Adc Offset: 0x0C) Channel Sequence Register 2 */ + __O uint32_t ADC_CHER; /**< \brief (Adc Offset: 0x10) Channel Enable Register */ + __O uint32_t ADC_CHDR; /**< \brief (Adc Offset: 0x14) Channel Disable Register */ + __I uint32_t ADC_CHSR; /**< \brief (Adc Offset: 0x18) Channel Status Register */ + __I uint32_t Reserved1[1]; + __I uint32_t ADC_LCDR; /**< \brief (Adc Offset: 0x20) Last Converted Data Register */ + __O uint32_t ADC_IER; /**< \brief (Adc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ADC_IDR; /**< \brief (Adc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ADC_IMR; /**< \brief (Adc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ADC_ISR; /**< \brief (Adc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[2]; + __I uint32_t ADC_OVER; /**< \brief (Adc Offset: 0x3C) Overrun Status Register */ + __IO uint32_t ADC_EMR; /**< \brief (Adc Offset: 0x40) Extended Mode Register */ + __IO uint32_t ADC_CWR; /**< \brief (Adc Offset: 0x44) Compare Window Register */ + __IO uint32_t ADC_CGR; /**< \brief (Adc Offset: 0x48) Channel Gain Register */ + __IO uint32_t ADC_COR; /**< \brief (Adc Offset: 0x4C) Channel Offset Register */ + __I uint32_t ADC_CDR[15]; /**< \brief (Adc Offset: 0x50) Channel Data Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t ADC_ACR; /**< \brief (Adc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved4[19]; + __IO uint32_t ADC_WPMR; /**< \brief (Adc Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t ADC_WPSR; /**< \brief (Adc Offset: 0xE8) Write Protect Status Register */ + __I uint32_t Reserved5[5]; + __IO uint32_t ADC_RPR; /**< \brief (Adc Offset: 0x100) Receive Pointer Register */ + __IO uint32_t ADC_RCR; /**< \brief (Adc Offset: 0x104) Receive Counter Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t ADC_RNPR; /**< \brief (Adc Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t ADC_RNCR; /**< \brief (Adc Offset: 0x114) Receive Next Counter Register */ + __I uint32_t Reserved7[2]; + __O uint32_t ADC_PTCR; /**< \brief (Adc Offset: 0x120) Transfer Control Register */ + __I uint32_t ADC_PTSR; /**< \brief (Adc Offset: 0x124) Transfer Status Register */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ +#define ADC_CR_SWRST (0x1u << 0) /**< \brief (ADC_CR) Software Reset */ +#define ADC_CR_START (0x1u << 1) /**< \brief (ADC_CR) Start Conversion */ +#define ADC_CR_AUTOCAL (0x1u << 3) /**< \brief (ADC_CR) Automatic Calibration of ADC */ +/* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ +#define ADC_MR_TRGEN (0x1u << 0) /**< \brief (ADC_MR) Trigger Enable */ +#define ADC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define ADC_MR_TRGEN_EN (0x1u << 0) /**< \brief (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define ADC_MR_TRGSEL_Pos 1 +#define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /**< \brief (ADC_MR) Trigger Selection */ +#define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /**< \brief (ADC_MR) External trigger */ +#define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 1 */ +#define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /**< \brief (ADC_MR) TIO Output of the Timer Counter Channel 2 */ +#define ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) /**< \brief (ADC_MR) PWM Event Line 0 */ +#define ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) /**< \brief (ADC_MR) PWM Event Line 1 */ +#define ADC_MR_LOWRES (0x1u << 4) /**< \brief (ADC_MR) Resolution */ +#define ADC_MR_LOWRES_BITS_12 (0x0u << 4) /**< \brief (ADC_MR) 12-bit resolution */ +#define ADC_MR_LOWRES_BITS_10 (0x1u << 4) /**< \brief (ADC_MR) 10-bit resolution */ +#define ADC_MR_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode */ +#define ADC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ +#define ADC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */ +#define ADC_MR_FWUP (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up */ +#define ADC_MR_FWUP_OFF (0x0u << 6) /**< \brief (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */ +#define ADC_MR_FWUP_ON (0x1u << 6) /**< \brief (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */ +#define ADC_MR_FREERUN (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode */ +#define ADC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (ADC_MR) Normal Mode */ +#define ADC_MR_FREERUN_ON (0x1u << 7) /**< \brief (ADC_MR) Free Run Mode: Never wait for any trigger. */ +#define ADC_MR_PRESCAL_Pos 8 +#define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /**< \brief (ADC_MR) Prescaler Rate Selection */ +#define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) +#define ADC_MR_STARTUP_Pos 16 +#define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /**< \brief (ADC_MR) Start Up Time */ +#define ADC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (ADC_MR) 0 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (ADC_MR) 8 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (ADC_MR) 16 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (ADC_MR) 24 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (ADC_MR) 64 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (ADC_MR) 80 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (ADC_MR) 96 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (ADC_MR) 112 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (ADC_MR) 512 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (ADC_MR) 576 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (ADC_MR) 640 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (ADC_MR) 704 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (ADC_MR) 768 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (ADC_MR) 832 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (ADC_MR) 896 periods of ADCClock */ +#define ADC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (ADC_MR) 960 periods of ADCClock */ +#define ADC_MR_SETTLING_Pos 20 +#define ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) /**< \brief (ADC_MR) Analog Settling Time */ +#define ADC_MR_SETTLING_AST3 (0x0u << 20) /**< \brief (ADC_MR) 3 periods of ADCClock */ +#define ADC_MR_SETTLING_AST5 (0x1u << 20) /**< \brief (ADC_MR) 5 periods of ADCClock */ +#define ADC_MR_SETTLING_AST9 (0x2u << 20) /**< \brief (ADC_MR) 9 periods of ADCClock */ +#define ADC_MR_SETTLING_AST17 (0x3u << 20) /**< \brief (ADC_MR) 17 periods of ADCClock */ +#define ADC_MR_ANACH (0x1u << 23) /**< \brief (ADC_MR) Analog Change */ +#define ADC_MR_ANACH_NONE (0x0u << 23) /**< \brief (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels */ +#define ADC_MR_ANACH_ALLOWED (0x1u << 23) /**< \brief (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers */ +#define ADC_MR_TRACKTIM_Pos 24 +#define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /**< \brief (ADC_MR) Tracking Time */ +#define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) +#define ADC_MR_TRANSFER_Pos 28 +#define ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) /**< \brief (ADC_MR) Transfer Period */ +#define ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos))) +#define ADC_MR_USEQ (0x1u << 31) /**< \brief (ADC_MR) Use Sequence Enable */ +#define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */ +#define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */ +/* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */ +#define ADC_SEQR1_USCH1_Pos 0 +#define ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 1 */ +#define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) +#define ADC_SEQR1_USCH2_Pos 4 +#define ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 2 */ +#define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) +#define ADC_SEQR1_USCH3_Pos 8 +#define ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 3 */ +#define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) +#define ADC_SEQR1_USCH4_Pos 12 +#define ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 4 */ +#define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) +#define ADC_SEQR1_USCH5_Pos 16 +#define ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 5 */ +#define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) +#define ADC_SEQR1_USCH6_Pos 20 +#define ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 6 */ +#define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) +#define ADC_SEQR1_USCH7_Pos 24 +#define ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 7 */ +#define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) +#define ADC_SEQR1_USCH8_Pos 28 +#define ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) /**< \brief (ADC_SEQR1) User Sequence Number 8 */ +#define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos))) +/* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */ +#define ADC_SEQR2_USCH9_Pos 0 +#define ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 9 */ +#define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos))) +#define ADC_SEQR2_USCH10_Pos 4 +#define ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 10 */ +#define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos))) +#define ADC_SEQR2_USCH11_Pos 8 +#define ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 11 */ +#define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos))) +#define ADC_SEQR2_USCH12_Pos 12 +#define ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 12 */ +#define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos))) +#define ADC_SEQR2_USCH13_Pos 16 +#define ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 13 */ +#define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos))) +#define ADC_SEQR2_USCH14_Pos 20 +#define ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 14 */ +#define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos))) +#define ADC_SEQR2_USCH15_Pos 24 +#define ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 15 */ +#define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos))) +#define ADC_SEQR2_USCH16_Pos 28 +#define ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) /**< \brief (ADC_SEQR2) User Sequence Number 16 */ +#define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos))) +/* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ +#define ADC_CHER_CH0 (0x1u << 0) /**< \brief (ADC_CHER) Channel 0 Enable */ +#define ADC_CHER_CH1 (0x1u << 1) /**< \brief (ADC_CHER) Channel 1 Enable */ +#define ADC_CHER_CH2 (0x1u << 2) /**< \brief (ADC_CHER) Channel 2 Enable */ +#define ADC_CHER_CH3 (0x1u << 3) /**< \brief (ADC_CHER) Channel 3 Enable */ +#define ADC_CHER_CH4 (0x1u << 4) /**< \brief (ADC_CHER) Channel 4 Enable */ +#define ADC_CHER_CH5 (0x1u << 5) /**< \brief (ADC_CHER) Channel 5 Enable */ +#define ADC_CHER_CH6 (0x1u << 6) /**< \brief (ADC_CHER) Channel 6 Enable */ +#define ADC_CHER_CH7 (0x1u << 7) /**< \brief (ADC_CHER) Channel 7 Enable */ +#define ADC_CHER_CH8 (0x1u << 8) /**< \brief (ADC_CHER) Channel 8 Enable */ +#define ADC_CHER_CH9 (0x1u << 9) /**< \brief (ADC_CHER) Channel 9 Enable */ +#define ADC_CHER_CH10 (0x1u << 10) /**< \brief (ADC_CHER) Channel 10 Enable */ +#define ADC_CHER_CH11 (0x1u << 11) /**< \brief (ADC_CHER) Channel 11 Enable */ +#define ADC_CHER_CH12 (0x1u << 12) /**< \brief (ADC_CHER) Channel 12 Enable */ +#define ADC_CHER_CH13 (0x1u << 13) /**< \brief (ADC_CHER) Channel 13 Enable */ +#define ADC_CHER_CH14 (0x1u << 14) /**< \brief (ADC_CHER) Channel 14 Enable */ +#define ADC_CHER_CH15 (0x1u << 15) /**< \brief (ADC_CHER) Channel 15 Enable */ +/* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ +#define ADC_CHDR_CH0 (0x1u << 0) /**< \brief (ADC_CHDR) Channel 0 Disable */ +#define ADC_CHDR_CH1 (0x1u << 1) /**< \brief (ADC_CHDR) Channel 1 Disable */ +#define ADC_CHDR_CH2 (0x1u << 2) /**< \brief (ADC_CHDR) Channel 2 Disable */ +#define ADC_CHDR_CH3 (0x1u << 3) /**< \brief (ADC_CHDR) Channel 3 Disable */ +#define ADC_CHDR_CH4 (0x1u << 4) /**< \brief (ADC_CHDR) Channel 4 Disable */ +#define ADC_CHDR_CH5 (0x1u << 5) /**< \brief (ADC_CHDR) Channel 5 Disable */ +#define ADC_CHDR_CH6 (0x1u << 6) /**< \brief (ADC_CHDR) Channel 6 Disable */ +#define ADC_CHDR_CH7 (0x1u << 7) /**< \brief (ADC_CHDR) Channel 7 Disable */ +#define ADC_CHDR_CH8 (0x1u << 8) /**< \brief (ADC_CHDR) Channel 8 Disable */ +#define ADC_CHDR_CH9 (0x1u << 9) /**< \brief (ADC_CHDR) Channel 9 Disable */ +#define ADC_CHDR_CH10 (0x1u << 10) /**< \brief (ADC_CHDR) Channel 10 Disable */ +#define ADC_CHDR_CH11 (0x1u << 11) /**< \brief (ADC_CHDR) Channel 11 Disable */ +#define ADC_CHDR_CH12 (0x1u << 12) /**< \brief (ADC_CHDR) Channel 12 Disable */ +#define ADC_CHDR_CH13 (0x1u << 13) /**< \brief (ADC_CHDR) Channel 13 Disable */ +#define ADC_CHDR_CH14 (0x1u << 14) /**< \brief (ADC_CHDR) Channel 14 Disable */ +#define ADC_CHDR_CH15 (0x1u << 15) /**< \brief (ADC_CHDR) Channel 15 Disable */ +/* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ +#define ADC_CHSR_CH0 (0x1u << 0) /**< \brief (ADC_CHSR) Channel 0 Status */ +#define ADC_CHSR_CH1 (0x1u << 1) /**< \brief (ADC_CHSR) Channel 1 Status */ +#define ADC_CHSR_CH2 (0x1u << 2) /**< \brief (ADC_CHSR) Channel 2 Status */ +#define ADC_CHSR_CH3 (0x1u << 3) /**< \brief (ADC_CHSR) Channel 3 Status */ +#define ADC_CHSR_CH4 (0x1u << 4) /**< \brief (ADC_CHSR) Channel 4 Status */ +#define ADC_CHSR_CH5 (0x1u << 5) /**< \brief (ADC_CHSR) Channel 5 Status */ +#define ADC_CHSR_CH6 (0x1u << 6) /**< \brief (ADC_CHSR) Channel 6 Status */ +#define ADC_CHSR_CH7 (0x1u << 7) /**< \brief (ADC_CHSR) Channel 7 Status */ +#define ADC_CHSR_CH8 (0x1u << 8) /**< \brief (ADC_CHSR) Channel 8 Status */ +#define ADC_CHSR_CH9 (0x1u << 9) /**< \brief (ADC_CHSR) Channel 9 Status */ +#define ADC_CHSR_CH10 (0x1u << 10) /**< \brief (ADC_CHSR) Channel 10 Status */ +#define ADC_CHSR_CH11 (0x1u << 11) /**< \brief (ADC_CHSR) Channel 11 Status */ +#define ADC_CHSR_CH12 (0x1u << 12) /**< \brief (ADC_CHSR) Channel 12 Status */ +#define ADC_CHSR_CH13 (0x1u << 13) /**< \brief (ADC_CHSR) Channel 13 Status */ +#define ADC_CHSR_CH14 (0x1u << 14) /**< \brief (ADC_CHSR) Channel 14 Status */ +#define ADC_CHSR_CH15 (0x1u << 15) /**< \brief (ADC_CHSR) Channel 15 Status */ +/* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ +#define ADC_LCDR_LDATA_Pos 0 +#define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /**< \brief (ADC_LCDR) Last Data Converted */ +#define ADC_LCDR_CHNB_Pos 12 +#define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /**< \brief (ADC_LCDR) Channel Number */ +/* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ +#define ADC_IER_EOC0 (0x1u << 0) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 0 */ +#define ADC_IER_EOC1 (0x1u << 1) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 1 */ +#define ADC_IER_EOC2 (0x1u << 2) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 2 */ +#define ADC_IER_EOC3 (0x1u << 3) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 3 */ +#define ADC_IER_EOC4 (0x1u << 4) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 4 */ +#define ADC_IER_EOC5 (0x1u << 5) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 5 */ +#define ADC_IER_EOC6 (0x1u << 6) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 6 */ +#define ADC_IER_EOC7 (0x1u << 7) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 7 */ +#define ADC_IER_EOC8 (0x1u << 8) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 8 */ +#define ADC_IER_EOC9 (0x1u << 9) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 9 */ +#define ADC_IER_EOC10 (0x1u << 10) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 10 */ +#define ADC_IER_EOC11 (0x1u << 11) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 11 */ +#define ADC_IER_EOC12 (0x1u << 12) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 12 */ +#define ADC_IER_EOC13 (0x1u << 13) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 13 */ +#define ADC_IER_EOC14 (0x1u << 14) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 14 */ +#define ADC_IER_EOC15 (0x1u << 15) /**< \brief (ADC_IER) End of Conversion Interrupt Enable 15 */ +#define ADC_IER_EOCAL (0x1u << 23) /**< \brief (ADC_IER) End of Calibration Sequence */ +#define ADC_IER_DRDY (0x1u << 24) /**< \brief (ADC_IER) Data Ready Interrupt Enable */ +#define ADC_IER_GOVRE (0x1u << 25) /**< \brief (ADC_IER) General Overrun Error Interrupt Enable */ +#define ADC_IER_COMPE (0x1u << 26) /**< \brief (ADC_IER) Comparison Event Interrupt Enable */ +#define ADC_IER_ENDRX (0x1u << 27) /**< \brief (ADC_IER) End of Receive Buffer Interrupt Enable */ +#define ADC_IER_RXBUFF (0x1u << 28) /**< \brief (ADC_IER) Receive Buffer Full Interrupt Enable */ +/* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ +#define ADC_IDR_EOC0 (0x1u << 0) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 0 */ +#define ADC_IDR_EOC1 (0x1u << 1) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 1 */ +#define ADC_IDR_EOC2 (0x1u << 2) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 2 */ +#define ADC_IDR_EOC3 (0x1u << 3) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 3 */ +#define ADC_IDR_EOC4 (0x1u << 4) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 4 */ +#define ADC_IDR_EOC5 (0x1u << 5) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 5 */ +#define ADC_IDR_EOC6 (0x1u << 6) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 6 */ +#define ADC_IDR_EOC7 (0x1u << 7) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 7 */ +#define ADC_IDR_EOC8 (0x1u << 8) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 8 */ +#define ADC_IDR_EOC9 (0x1u << 9) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 9 */ +#define ADC_IDR_EOC10 (0x1u << 10) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 10 */ +#define ADC_IDR_EOC11 (0x1u << 11) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 11 */ +#define ADC_IDR_EOC12 (0x1u << 12) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 12 */ +#define ADC_IDR_EOC13 (0x1u << 13) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 13 */ +#define ADC_IDR_EOC14 (0x1u << 14) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 14 */ +#define ADC_IDR_EOC15 (0x1u << 15) /**< \brief (ADC_IDR) End of Conversion Interrupt Disable 15 */ +#define ADC_IDR_EOCAL (0x1u << 23) /**< \brief (ADC_IDR) End of Calibration Sequence */ +#define ADC_IDR_DRDY (0x1u << 24) /**< \brief (ADC_IDR) Data Ready Interrupt Disable */ +#define ADC_IDR_GOVRE (0x1u << 25) /**< \brief (ADC_IDR) General Overrun Error Interrupt Disable */ +#define ADC_IDR_COMPE (0x1u << 26) /**< \brief (ADC_IDR) Comparison Event Interrupt Disable */ +#define ADC_IDR_ENDRX (0x1u << 27) /**< \brief (ADC_IDR) End of Receive Buffer Interrupt Disable */ +#define ADC_IDR_RXBUFF (0x1u << 28) /**< \brief (ADC_IDR) Receive Buffer Full Interrupt Disable */ +/* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ADC_IMR_EOC0 (0x1u << 0) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 0 */ +#define ADC_IMR_EOC1 (0x1u << 1) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 1 */ +#define ADC_IMR_EOC2 (0x1u << 2) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 2 */ +#define ADC_IMR_EOC3 (0x1u << 3) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 3 */ +#define ADC_IMR_EOC4 (0x1u << 4) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 4 */ +#define ADC_IMR_EOC5 (0x1u << 5) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 5 */ +#define ADC_IMR_EOC6 (0x1u << 6) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 6 */ +#define ADC_IMR_EOC7 (0x1u << 7) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 7 */ +#define ADC_IMR_EOC8 (0x1u << 8) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 8 */ +#define ADC_IMR_EOC9 (0x1u << 9) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 9 */ +#define ADC_IMR_EOC10 (0x1u << 10) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 10 */ +#define ADC_IMR_EOC11 (0x1u << 11) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 11 */ +#define ADC_IMR_EOC12 (0x1u << 12) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 12 */ +#define ADC_IMR_EOC13 (0x1u << 13) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 13 */ +#define ADC_IMR_EOC14 (0x1u << 14) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 14 */ +#define ADC_IMR_EOC15 (0x1u << 15) /**< \brief (ADC_IMR) End of Conversion Interrupt Mask 15 */ +#define ADC_IMR_EOCAL (0x1u << 23) /**< \brief (ADC_IMR) End of Calibration Sequence */ +#define ADC_IMR_DRDY (0x1u << 24) /**< \brief (ADC_IMR) Data Ready Interrupt Mask */ +#define ADC_IMR_GOVRE (0x1u << 25) /**< \brief (ADC_IMR) General Overrun Error Interrupt Mask */ +#define ADC_IMR_COMPE (0x1u << 26) /**< \brief (ADC_IMR) Comparison Event Interrupt Mask */ +#define ADC_IMR_ENDRX (0x1u << 27) /**< \brief (ADC_IMR) End of Receive Buffer Interrupt Mask */ +#define ADC_IMR_RXBUFF (0x1u << 28) /**< \brief (ADC_IMR) Receive Buffer Full Interrupt Mask */ +/* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ +#define ADC_ISR_EOC0 (0x1u << 0) /**< \brief (ADC_ISR) End of Conversion 0 */ +#define ADC_ISR_EOC1 (0x1u << 1) /**< \brief (ADC_ISR) End of Conversion 1 */ +#define ADC_ISR_EOC2 (0x1u << 2) /**< \brief (ADC_ISR) End of Conversion 2 */ +#define ADC_ISR_EOC3 (0x1u << 3) /**< \brief (ADC_ISR) End of Conversion 3 */ +#define ADC_ISR_EOC4 (0x1u << 4) /**< \brief (ADC_ISR) End of Conversion 4 */ +#define ADC_ISR_EOC5 (0x1u << 5) /**< \brief (ADC_ISR) End of Conversion 5 */ +#define ADC_ISR_EOC6 (0x1u << 6) /**< \brief (ADC_ISR) End of Conversion 6 */ +#define ADC_ISR_EOC7 (0x1u << 7) /**< \brief (ADC_ISR) End of Conversion 7 */ +#define ADC_ISR_EOC8 (0x1u << 8) /**< \brief (ADC_ISR) End of Conversion 8 */ +#define ADC_ISR_EOC9 (0x1u << 9) /**< \brief (ADC_ISR) End of Conversion 9 */ +#define ADC_ISR_EOC10 (0x1u << 10) /**< \brief (ADC_ISR) End of Conversion 10 */ +#define ADC_ISR_EOC11 (0x1u << 11) /**< \brief (ADC_ISR) End of Conversion 11 */ +#define ADC_ISR_EOC12 (0x1u << 12) /**< \brief (ADC_ISR) End of Conversion 12 */ +#define ADC_ISR_EOC13 (0x1u << 13) /**< \brief (ADC_ISR) End of Conversion 13 */ +#define ADC_ISR_EOC14 (0x1u << 14) /**< \brief (ADC_ISR) End of Conversion 14 */ +#define ADC_ISR_EOC15 (0x1u << 15) /**< \brief (ADC_ISR) End of Conversion 15 */ +#define ADC_ISR_EOCAL (0x1u << 23) /**< \brief (ADC_ISR) End of Calibration Sequence */ +#define ADC_ISR_DRDY (0x1u << 24) /**< \brief (ADC_ISR) Data Ready */ +#define ADC_ISR_GOVRE (0x1u << 25) /**< \brief (ADC_ISR) General Overrun Error */ +#define ADC_ISR_COMPE (0x1u << 26) /**< \brief (ADC_ISR) Comparison Error */ +#define ADC_ISR_ENDRX (0x1u << 27) /**< \brief (ADC_ISR) End of RX Buffer */ +#define ADC_ISR_RXBUFF (0x1u << 28) /**< \brief (ADC_ISR) RX Buffer Full */ +/* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ +#define ADC_OVER_OVRE0 (0x1u << 0) /**< \brief (ADC_OVER) Overrun Error 0 */ +#define ADC_OVER_OVRE1 (0x1u << 1) /**< \brief (ADC_OVER) Overrun Error 1 */ +#define ADC_OVER_OVRE2 (0x1u << 2) /**< \brief (ADC_OVER) Overrun Error 2 */ +#define ADC_OVER_OVRE3 (0x1u << 3) /**< \brief (ADC_OVER) Overrun Error 3 */ +#define ADC_OVER_OVRE4 (0x1u << 4) /**< \brief (ADC_OVER) Overrun Error 4 */ +#define ADC_OVER_OVRE5 (0x1u << 5) /**< \brief (ADC_OVER) Overrun Error 5 */ +#define ADC_OVER_OVRE6 (0x1u << 6) /**< \brief (ADC_OVER) Overrun Error 6 */ +#define ADC_OVER_OVRE7 (0x1u << 7) /**< \brief (ADC_OVER) Overrun Error 7 */ +#define ADC_OVER_OVRE8 (0x1u << 8) /**< \brief (ADC_OVER) Overrun Error 8 */ +#define ADC_OVER_OVRE9 (0x1u << 9) /**< \brief (ADC_OVER) Overrun Error 9 */ +#define ADC_OVER_OVRE10 (0x1u << 10) /**< \brief (ADC_OVER) Overrun Error 10 */ +#define ADC_OVER_OVRE11 (0x1u << 11) /**< \brief (ADC_OVER) Overrun Error 11 */ +#define ADC_OVER_OVRE12 (0x1u << 12) /**< \brief (ADC_OVER) Overrun Error 12 */ +#define ADC_OVER_OVRE13 (0x1u << 13) /**< \brief (ADC_OVER) Overrun Error 13 */ +#define ADC_OVER_OVRE14 (0x1u << 14) /**< \brief (ADC_OVER) Overrun Error 14 */ +#define ADC_OVER_OVRE15 (0x1u << 15) /**< \brief (ADC_OVER) Overrun Error 15 */ +/* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ +#define ADC_EMR_CMPMODE_Pos 0 +#define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /**< \brief (ADC_EMR) Comparison Mode */ +#define ADC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define ADC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is in the comparison window. */ +#define ADC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define ADC_EMR_CMPSEL_Pos 4 +#define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /**< \brief (ADC_EMR) Comparison Selected Channel */ +#define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) +#define ADC_EMR_CMPALL (0x1u << 9) /**< \brief (ADC_EMR) Compare All Channels */ +#define ADC_EMR_CMPFILTER_Pos 12 +#define ADC_EMR_CMPFILTER_Msk (0x3u << ADC_EMR_CMPFILTER_Pos) /**< \brief (ADC_EMR) Compare Event Filtering */ +#define ADC_EMR_CMPFILTER(value) ((ADC_EMR_CMPFILTER_Msk & ((value) << ADC_EMR_CMPFILTER_Pos))) +#define ADC_EMR_TAG (0x1u << 24) /**< \brief (ADC_EMR) TAG of ADC_LDCR register */ +/* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ +#define ADC_CWR_LOWTHRES_Pos 0 +#define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /**< \brief (ADC_CWR) Low Threshold */ +#define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) +#define ADC_CWR_HIGHTHRES_Pos 16 +#define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /**< \brief (ADC_CWR) High Threshold */ +#define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) +/* -------- ADC_CGR : (ADC Offset: 0x48) Channel Gain Register -------- */ +#define ADC_CGR_GAIN0_Pos 0 +#define ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) /**< \brief (ADC_CGR) Gain for channel 0 */ +#define ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos))) +#define ADC_CGR_GAIN1_Pos 2 +#define ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) /**< \brief (ADC_CGR) Gain for channel 1 */ +#define ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos))) +#define ADC_CGR_GAIN2_Pos 4 +#define ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) /**< \brief (ADC_CGR) Gain for channel 2 */ +#define ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos))) +#define ADC_CGR_GAIN3_Pos 6 +#define ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) /**< \brief (ADC_CGR) Gain for channel 3 */ +#define ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos))) +#define ADC_CGR_GAIN4_Pos 8 +#define ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) /**< \brief (ADC_CGR) Gain for channel 4 */ +#define ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos))) +#define ADC_CGR_GAIN5_Pos 10 +#define ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) /**< \brief (ADC_CGR) Gain for channel 5 */ +#define ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos))) +#define ADC_CGR_GAIN6_Pos 12 +#define ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) /**< \brief (ADC_CGR) Gain for channel 6 */ +#define ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos))) +#define ADC_CGR_GAIN7_Pos 14 +#define ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) /**< \brief (ADC_CGR) Gain for channel 7 */ +#define ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos))) +#define ADC_CGR_GAIN8_Pos 16 +#define ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) /**< \brief (ADC_CGR) Gain for channel 8 */ +#define ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos))) +#define ADC_CGR_GAIN9_Pos 18 +#define ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) /**< \brief (ADC_CGR) Gain for channel 9 */ +#define ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos))) +#define ADC_CGR_GAIN10_Pos 20 +#define ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) /**< \brief (ADC_CGR) Gain for channel 10 */ +#define ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos))) +#define ADC_CGR_GAIN11_Pos 22 +#define ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) /**< \brief (ADC_CGR) Gain for channel 11 */ +#define ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos))) +#define ADC_CGR_GAIN12_Pos 24 +#define ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) /**< \brief (ADC_CGR) Gain for channel 12 */ +#define ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos))) +#define ADC_CGR_GAIN13_Pos 26 +#define ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) /**< \brief (ADC_CGR) Gain for channel 13 */ +#define ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos))) +#define ADC_CGR_GAIN14_Pos 28 +#define ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) /**< \brief (ADC_CGR) Gain for channel 14 */ +#define ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos))) +#define ADC_CGR_GAIN15_Pos 30 +#define ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) /**< \brief (ADC_CGR) Gain for channel 15 */ +#define ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos))) +/* -------- ADC_COR : (ADC Offset: 0x4C) Channel Offset Register -------- */ +#define ADC_COR_OFF0 (0x1u << 0) /**< \brief (ADC_COR) Offset for channel 0 */ +#define ADC_COR_OFF1 (0x1u << 1) /**< \brief (ADC_COR) Offset for channel 1 */ +#define ADC_COR_OFF2 (0x1u << 2) /**< \brief (ADC_COR) Offset for channel 2 */ +#define ADC_COR_OFF3 (0x1u << 3) /**< \brief (ADC_COR) Offset for channel 3 */ +#define ADC_COR_OFF4 (0x1u << 4) /**< \brief (ADC_COR) Offset for channel 4 */ +#define ADC_COR_OFF5 (0x1u << 5) /**< \brief (ADC_COR) Offset for channel 5 */ +#define ADC_COR_OFF6 (0x1u << 6) /**< \brief (ADC_COR) Offset for channel 6 */ +#define ADC_COR_OFF7 (0x1u << 7) /**< \brief (ADC_COR) Offset for channel 7 */ +#define ADC_COR_OFF8 (0x1u << 8) /**< \brief (ADC_COR) Offset for channel 8 */ +#define ADC_COR_OFF9 (0x1u << 9) /**< \brief (ADC_COR) Offset for channel 9 */ +#define ADC_COR_OFF10 (0x1u << 10) /**< \brief (ADC_COR) Offset for channel 10 */ +#define ADC_COR_OFF11 (0x1u << 11) /**< \brief (ADC_COR) Offset for channel 11 */ +#define ADC_COR_OFF12 (0x1u << 12) /**< \brief (ADC_COR) Offset for channel 12 */ +#define ADC_COR_OFF13 (0x1u << 13) /**< \brief (ADC_COR) Offset for channel 13 */ +#define ADC_COR_OFF14 (0x1u << 14) /**< \brief (ADC_COR) Offset for channel 14 */ +#define ADC_COR_OFF15 (0x1u << 15) /**< \brief (ADC_COR) Offset for channel 15 */ +#define ADC_COR_DIFF0 (0x1u << 16) /**< \brief (ADC_COR) Differential inputs for channel 0 */ +#define ADC_COR_DIFF1 (0x1u << 17) /**< \brief (ADC_COR) Differential inputs for channel 1 */ +#define ADC_COR_DIFF2 (0x1u << 18) /**< \brief (ADC_COR) Differential inputs for channel 2 */ +#define ADC_COR_DIFF3 (0x1u << 19) /**< \brief (ADC_COR) Differential inputs for channel 3 */ +#define ADC_COR_DIFF4 (0x1u << 20) /**< \brief (ADC_COR) Differential inputs for channel 4 */ +#define ADC_COR_DIFF5 (0x1u << 21) /**< \brief (ADC_COR) Differential inputs for channel 5 */ +#define ADC_COR_DIFF6 (0x1u << 22) /**< \brief (ADC_COR) Differential inputs for channel 6 */ +#define ADC_COR_DIFF7 (0x1u << 23) /**< \brief (ADC_COR) Differential inputs for channel 7 */ +#define ADC_COR_DIFF8 (0x1u << 24) /**< \brief (ADC_COR) Differential inputs for channel 8 */ +#define ADC_COR_DIFF9 (0x1u << 25) /**< \brief (ADC_COR) Differential inputs for channel 9 */ +#define ADC_COR_DIFF10 (0x1u << 26) /**< \brief (ADC_COR) Differential inputs for channel 10 */ +#define ADC_COR_DIFF11 (0x1u << 27) /**< \brief (ADC_COR) Differential inputs for channel 11 */ +#define ADC_COR_DIFF12 (0x1u << 28) /**< \brief (ADC_COR) Differential inputs for channel 12 */ +#define ADC_COR_DIFF13 (0x1u << 29) /**< \brief (ADC_COR) Differential inputs for channel 13 */ +#define ADC_COR_DIFF14 (0x1u << 30) /**< \brief (ADC_COR) Differential inputs for channel 14 */ +#define ADC_COR_DIFF15 (0x1u << 31) /**< \brief (ADC_COR) Differential inputs for channel 15 */ +/* -------- ADC_CDR[15] : (ADC Offset: 0x50) Channel Data Register -------- */ +#define ADC_CDR_DATA_Pos 0 +#define ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) /**< \brief (ADC_CDR[15]) Converted Data */ +/* -------- ADC_ACR : (ADC Offset: 0x94) Analog Control Register -------- */ +#define ADC_ACR_TSON (0x1u << 4) /**< \brief (ADC_ACR) Temperature Sensor On */ +#define ADC_ACR_IBCTL_Pos 8 +#define ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) /**< \brief (ADC_ACR) ADC Bias Current Control */ +#define ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) +/* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ +#define ADC_WPMR_WPEN (0x1u << 0) /**< \brief (ADC_WPMR) Write Protect Enable */ +#define ADC_WPMR_WPKEY_Pos 8 +#define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /**< \brief (ADC_WPMR) Write Protect KEY */ +#define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) +/* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ +#define ADC_WPSR_WPVS (0x1u << 0) /**< \brief (ADC_WPSR) Write Protect Violation Status */ +#define ADC_WPSR_WPVSRC_Pos 8 +#define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /**< \brief (ADC_WPSR) Write Protect Violation Source */ +/* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ +#define ADC_RPR_RXPTR_Pos 0 +#define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /**< \brief (ADC_RPR) Receive Pointer Register */ +#define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) +/* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ +#define ADC_RCR_RXCTR_Pos 0 +#define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /**< \brief (ADC_RCR) Receive Counter Register */ +#define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) +/* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ +#define ADC_RNPR_RXNPTR_Pos 0 +#define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /**< \brief (ADC_RNPR) Receive Next Pointer */ +#define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) +/* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ +#define ADC_RNCR_RXNCTR_Pos 0 +#define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /**< \brief (ADC_RNCR) Receive Next Counter */ +#define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) +/* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ +#define ADC_PTCR_RXTEN (0x1u << 0) /**< \brief (ADC_PTCR) Receiver Transfer Enable */ +#define ADC_PTCR_RXTDIS (0x1u << 1) /**< \brief (ADC_PTCR) Receiver Transfer Disable */ +#define ADC_PTCR_TXTEN (0x1u << 8) /**< \brief (ADC_PTCR) Transmitter Transfer Enable */ +#define ADC_PTCR_TXTDIS (0x1u << 9) /**< \brief (ADC_PTCR) Transmitter Transfer Disable */ +/* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ +#define ADC_PTSR_RXTEN (0x1u << 0) /**< \brief (ADC_PTSR) Receiver Transfer Enable */ +#define ADC_PTSR_TXTEN (0x1u << 8) /**< \brief (ADC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_ADC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/chipid.h b/zephyr/ports/asf/sam3sd8/include/component/chipid.h new file mode 100644 index 0000000..72f2fd8 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/chipid.h @@ -0,0 +1,159 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_CHIPID_COMPONENT_ +#define _SAM3SD8_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8K bytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16K bytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32K bytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64K bytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128K bytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256K bytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512K bytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024K bytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048K bytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8K bytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16K bytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32K bytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64K bytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128K bytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256K bytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512K bytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024K bytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048K bytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48K bytes */ +#define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /**< \brief (CHIPID_CIDR) 1K bytes */ +#define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /**< \brief (CHIPID_CIDR) 2K bytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6K bytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24K bytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4K bytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80K bytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160K bytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8K bytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16K bytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32K bytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64K bytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128K bytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256K bytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96K bytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512K bytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9xx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /**< \brief (CHIPID_CIDR) AT91SAM9XExx Series */ +#define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /**< \brief (CHIPID_CIDR) AT91x34 Series */ +#define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /**< \brief (CHIPID_CIDR) CAP7 Series */ +#define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /**< \brief (CHIPID_CIDR) CAP9 Series */ +#define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /**< \brief (CHIPID_CIDR) CAP11 Series */ +#define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /**< \brief (CHIPID_CIDR) AT91x40 Series */ +#define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /**< \brief (CHIPID_CIDR) AT91x42 Series */ +#define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /**< \brief (CHIPID_CIDR) AT91x55 Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Axx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7AQxx Series */ +#define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /**< \brief (CHIPID_CIDR) AT91x63 Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Sxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7XCxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SExx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Lxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7Xxx Series */ +#define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /**< \brief (CHIPID_CIDR) AT91SAM7SLxx Series */ +#define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /**< \brief (CHIPID_CIDR) SAM3UxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /**< \brief (CHIPID_CIDR) SAM3UxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM3AxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4AxC (0x83u << 20) /**< \brief (CHIPID_CIDR) SAM4AxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM3XxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4XxC (0x84u << 20) /**< \brief (CHIPID_CIDR) SAM4XxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM3XxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4XxE (0x85u << 20) /**< \brief (CHIPID_CIDR) SAM4XxE Series (144-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4XxG (0x86u << 20) /**< \brief (CHIPID_CIDR) SAM4XxG Series (208/217-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM3SxASeries (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4SxA (0x88u << 20) /**< \brief (CHIPID_CIDR) SAM4SxA Series (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM3SxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4SxB (0x89u << 20) /**< \brief (CHIPID_CIDR) SAM4SxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM3SxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM4SxC (0x8Au << 20) /**< \brief (CHIPID_CIDR) SAM4SxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /**< \brief (CHIPID_CIDR) AT91x92 Series */ +#define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /**< \brief (CHIPID_CIDR) SAM3NxA Series (48-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /**< \brief (CHIPID_CIDR) SAM3NxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /**< \brief (CHIPID_CIDR) SAM3NxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /**< \brief (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */ +#define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /**< \brief (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */ +#define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /**< \brief (CHIPID_CIDR) SAM5A */ +#define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /**< \brief (CHIPID_CIDR) AT75Cxx Series */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAM3SD8_CHIPID_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/crccu.h b/zephyr/ports/asf/sam3sd8/include/component/crccu.h new file mode 100644 index 0000000..3632058 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/crccu.h @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_CRCCU_COMPONENT_ +#define _SAM3SD8_CRCCU_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_CRCCU Cyclic Redundancy Check Calculation Unit */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Crccu hardware registers */ +typedef struct { + __IO uint32_t CRCCU_DSCR; /**< \brief (Crccu Offset: 0x00000000) CRCCU Descriptor Base Register */ + __I uint32_t Reserved1[1]; + __O uint32_t CRCCU_DMA_EN; /**< \brief (Crccu Offset: 0x00000008) CRCCU DMA Enable Register */ + __O uint32_t CRCCU_DMA_DIS; /**< \brief (Crccu Offset: 0x0000000C) CRCCU DMA Disable Register */ + __I uint32_t CRCCU_DMA_SR; /**< \brief (Crccu Offset: 0x00000010) CRCCU DMA Status Register */ + __O uint32_t CRCCU_DMA_IER; /**< \brief (Crccu Offset: 0x00000014) CRCCU DMA Interrupt Enable Register */ + __O uint32_t CRCCU_DMA_IDR; /**< \brief (Crccu Offset: 0x00000018) CRCCU DMA Interrupt Disable Register */ + __I uint32_t CRCCU_DMA_IMR; /**< \brief (Crccu Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register */ + __I uint32_t CRCCU_DMA_ISR; /**< \brief (Crccu Offset: 0x00000020) CRCCU DMA Interrupt Status Register */ + __I uint32_t Reserved2[4]; + __O uint32_t CRCCU_CR; /**< \brief (Crccu Offset: 0x00000034) CRCCU Control Register */ + __IO uint32_t CRCCU_MR; /**< \brief (Crccu Offset: 0x00000038) CRCCU Mode Register */ + __I uint32_t CRCCU_SR; /**< \brief (Crccu Offset: 0x0000003C) CRCCU Status Register */ + __O uint32_t CRCCU_IER; /**< \brief (Crccu Offset: 0x00000040) CRCCU Interrupt Enable Register */ + __O uint32_t CRCCU_IDR; /**< \brief (Crccu Offset: 0x00000044) CRCCU Interrupt Disable Register */ + __I uint32_t CRCCU_IMR; /**< \brief (Crccu Offset: 0x00000048) CRCCU Interrupt Mask Register */ + __I uint32_t CRCCU_ISR; /**< \brief (Crccu Offset: 0x0000004C) CRCCU Interrupt Status Register */ +} Crccu; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CRCCU_DSCR : (CRCCU Offset: 0x00000000) CRCCU Descriptor Base Register -------- */ +#define CRCCU_DSCR_DSCR_Pos 9 +#define CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) /**< \brief (CRCCU_DSCR) Descriptor Base Address */ +#define CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) +/* -------- CRCCU_DMA_EN : (CRCCU Offset: 0x00000008) CRCCU DMA Enable Register -------- */ +#define CRCCU_DMA_EN_DMAEN (0x1u << 0) /**< \brief (CRCCU_DMA_EN) DMA Enable Register */ +/* -------- CRCCU_DMA_DIS : (CRCCU Offset: 0x0000000C) CRCCU DMA Disable Register -------- */ +#define CRCCU_DMA_DIS_DMADIS (0x1u << 0) /**< \brief (CRCCU_DMA_DIS) DMA Disable Register */ +/* -------- CRCCU_DMA_SR : (CRCCU Offset: 0x00000010) CRCCU DMA Status Register -------- */ +#define CRCCU_DMA_SR_DMASR (0x1u << 0) /**< \brief (CRCCU_DMA_SR) DMA Status Register */ +/* -------- CRCCU_DMA_IER : (CRCCU Offset: 0x00000014) CRCCU DMA Interrupt Enable Register -------- */ +#define CRCCU_DMA_IER_DMAIER (0x1u << 0) /**< \brief (CRCCU_DMA_IER) Interrupt Enable register */ +/* -------- CRCCU_DMA_IDR : (CRCCU Offset: 0x00000018) CRCCU DMA Interrupt Disable Register -------- */ +#define CRCCU_DMA_IDR_DMAIDR (0x1u << 0) /**< \brief (CRCCU_DMA_IDR) Interrupt Disable register */ +/* -------- CRCCU_DMA_IMR : (CRCCU Offset: 0x0000001C) CRCCU DMA Interrupt Mask Register -------- */ +#define CRCCU_DMA_IMR_DMAIMR (0x1u << 0) /**< \brief (CRCCU_DMA_IMR) Interrupt Mask Register */ +/* -------- CRCCU_DMA_ISR : (CRCCU Offset: 0x00000020) CRCCU DMA Interrupt Status Register -------- */ +#define CRCCU_DMA_ISR_DMAISR (0x1u << 0) /**< \brief (CRCCU_DMA_ISR) Interrupt Status register */ +/* -------- CRCCU_CR : (CRCCU Offset: 0x00000034) CRCCU Control Register -------- */ +#define CRCCU_CR_RESET (0x1u << 0) /**< \brief (CRCCU_CR) CRC Computation Reset */ +/* -------- CRCCU_MR : (CRCCU Offset: 0x00000038) CRCCU Mode Register -------- */ +#define CRCCU_MR_ENABLE (0x1u << 0) /**< \brief (CRCCU_MR) CRC Enable */ +#define CRCCU_MR_COMPARE (0x1u << 1) /**< \brief (CRCCU_MR) CRC Compare */ +#define CRCCU_MR_PTYPE_Pos 2 +#define CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) /**< \brief (CRCCU_MR) Primitive Polynomial */ +#define CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) /**< \brief (CRCCU_MR) Polynom 0x04C11DB7 */ +#define CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) /**< \brief (CRCCU_MR) Polynom 0x1EDC6F41 */ +#define CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) /**< \brief (CRCCU_MR) Polynom 0x1021 */ +#define CRCCU_MR_DIVIDER_Pos 4 +#define CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) /**< \brief (CRCCU_MR) Request Divider */ +#define CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) +/* -------- CRCCU_SR : (CRCCU Offset: 0x0000003C) CRCCU Status Register -------- */ +#define CRCCU_SR_CRC_Pos 0 +#define CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) /**< \brief (CRCCU_SR) Cyclic Redundancy Check Value */ +/* -------- CRCCU_IER : (CRCCU Offset: 0x00000040) CRCCU Interrupt Enable Register -------- */ +#define CRCCU_IER_ERRIER (0x1u << 0) /**< \brief (CRCCU_IER) CRC Error Interrupt Enable */ +/* -------- CRCCU_IDR : (CRCCU Offset: 0x00000044) CRCCU Interrupt Disable Register -------- */ +#define CRCCU_IDR_ERRIDR (0x1u << 0) /**< \brief (CRCCU_IDR) CRC Error Interrupt Disable */ +/* -------- CRCCU_IMR : (CRCCU Offset: 0x00000048) CRCCU Interrupt Mask Register -------- */ +#define CRCCU_IMR_ERRIMR (0x1u << 0) /**< \brief (CRCCU_IMR) CRC Error Interrupt Mask */ +/* -------- CRCCU_ISR : (CRCCU Offset: 0x0000004C) CRCCU Interrupt Status Register -------- */ +#define CRCCU_ISR_ERRISR (0x1u << 0) /**< \brief (CRCCU_ISR) CRC Error Interrupt Status */ + +/*@}*/ + + +#endif /* _SAM3SD8_CRCCU_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/dacc.h b/zephyr/ports/asf/sam3sd8/include/component/dacc.h new file mode 100644 index 0000000..379c316 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/dacc.h @@ -0,0 +1,210 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_DACC_COMPONENT_ +#define _SAM3SD8_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t DACC_CDR; /**< \brief (Dacc Offset: 0x20) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved3[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved4[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protect Mode register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protect Status register */ + __I uint32_t Reserved5[7]; + __IO uint32_t DACC_TPR; /**< \brief (Dacc Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t DACC_TCR; /**< \brief (Dacc Offset: 0x10C) Transmit Counter Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t DACC_TNPR; /**< \brief (Dacc Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t DACC_TNCR; /**< \brief (Dacc Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t DACC_PTCR; /**< \brief (Dacc Offset: 0x120) Transfer Control Register */ + __I uint32_t DACC_PTSR; /**< \brief (Dacc Offset: 0x124) Transfer Status Register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_TRGEN (0x1u << 0) /**< \brief (DACC_MR) Trigger Enable */ +#define DACC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (DACC_MR) External trigger mode disabled. DACC in free running mode. */ +#define DACC_MR_TRGEN_EN (0x1u << 0) /**< \brief (DACC_MR) External trigger mode enabled. */ +#define DACC_MR_TRGSEL_Pos 1 +#define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /**< \brief (DACC_MR) Trigger Selection */ +#define DACC_MR_TRGSEL(value) ((DACC_MR_TRGSEL_Msk & ((value) << DACC_MR_TRGSEL_Pos))) +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_WORD_HALF (0x0u << 4) /**< \brief (DACC_MR) Half-Word transfer */ +#define DACC_MR_WORD_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer */ +#define DACC_MR_SLEEP (0x1u << 5) /**< \brief (DACC_MR) Sleep Mode */ +#define DACC_MR_FASTWKUP (0x1u << 6) /**< \brief (DACC_MR) Fast Wake up Mode */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_USER_SEL_Pos 16 +#define DACC_MR_USER_SEL_Msk (0x3u << DACC_MR_USER_SEL_Pos) /**< \brief (DACC_MR) User Channel Selection */ +#define DACC_MR_USER_SEL_CHANNEL0 (0x0u << 16) /**< \brief (DACC_MR) Channel 0 */ +#define DACC_MR_USER_SEL_CHANNEL1 (0x1u << 16) /**< \brief (DACC_MR) Channel 1 */ +#define DACC_MR_TAG (0x1u << 20) /**< \brief (DACC_MR) Tag Selection Mode */ +#define DACC_MR_TAG_DIS (0x0u << 20) /**< \brief (DACC_MR) Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. */ +#define DACC_MR_TAG_EN (0x1u << 20) /**< \brief (DACC_MR) Tag selection mode enabled */ +#define DACC_MR_MAXS (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode */ +#define DACC_MR_MAXS_NORMAL (0x0u << 21) /**< \brief (DACC_MR) Normal Mode */ +#define DACC_MR_MAXS_MAXIMUM (0x1u << 21) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_STARTUP_Pos 24 +#define DACC_MR_STARTUP_Msk (0x3fu << DACC_MR_STARTUP_Pos) /**< \brief (DACC_MR) Startup Time Selection */ +#define DACC_MR_STARTUP_0 (0x0u << 24) /**< \brief (DACC_MR) 0 periods of DACClock */ +#define DACC_MR_STARTUP_8 (0x1u << 24) /**< \brief (DACC_MR) 8 periods of DACClock */ +#define DACC_MR_STARTUP_16 (0x2u << 24) /**< \brief (DACC_MR) 16 periods of DACClock */ +#define DACC_MR_STARTUP_24 (0x3u << 24) /**< \brief (DACC_MR) 24 periods of DACClock */ +#define DACC_MR_STARTUP_64 (0x4u << 24) /**< \brief (DACC_MR) 64 periods of DACClock */ +#define DACC_MR_STARTUP_80 (0x5u << 24) /**< \brief (DACC_MR) 80 periods of DACClock */ +#define DACC_MR_STARTUP_96 (0x6u << 24) /**< \brief (DACC_MR) 96 periods of DACClock */ +#define DACC_MR_STARTUP_112 (0x7u << 24) /**< \brief (DACC_MR) 112 periods of DACClock */ +#define DACC_MR_STARTUP_512 (0x8u << 24) /**< \brief (DACC_MR) 512 periods of DACClock */ +#define DACC_MR_STARTUP_576 (0x9u << 24) /**< \brief (DACC_MR) 576 periods of DACClock */ +#define DACC_MR_STARTUP_640 (0xAu << 24) /**< \brief (DACC_MR) 640 periods of DACClock */ +#define DACC_MR_STARTUP_704 (0xBu << 24) /**< \brief (DACC_MR) 704 periods of DACClock */ +#define DACC_MR_STARTUP_768 (0xCu << 24) /**< \brief (DACC_MR) 768 periods of DACClock */ +#define DACC_MR_STARTUP_832 (0xDu << 24) /**< \brief (DACC_MR) 832 periods of DACClock */ +#define DACC_MR_STARTUP_896 (0xEu << 24) /**< \brief (DACC_MR) 896 periods of DACClock */ +#define DACC_MR_STARTUP_960 (0xFu << 24) /**< \brief (DACC_MR) 960 periods of DACClock */ +#define DACC_MR_STARTUP_1024 (0x10u << 24) /**< \brief (DACC_MR) 1024 periods of DACClock */ +#define DACC_MR_STARTUP_1088 (0x11u << 24) /**< \brief (DACC_MR) 1088 periods of DACClock */ +#define DACC_MR_STARTUP_1152 (0x12u << 24) /**< \brief (DACC_MR) 1152 periods of DACClock */ +#define DACC_MR_STARTUP_1216 (0x13u << 24) /**< \brief (DACC_MR) 1216 periods of DACClock */ +#define DACC_MR_STARTUP_1280 (0x14u << 24) /**< \brief (DACC_MR) 1280 periods of DACClock */ +#define DACC_MR_STARTUP_1344 (0x15u << 24) /**< \brief (DACC_MR) 1344 periods of DACClock */ +#define DACC_MR_STARTUP_1408 (0x16u << 24) /**< \brief (DACC_MR) 1408 periods of DACClock */ +#define DACC_MR_STARTUP_1472 (0x17u << 24) /**< \brief (DACC_MR) 1472 periods of DACClock */ +#define DACC_MR_STARTUP_1536 (0x18u << 24) /**< \brief (DACC_MR) 1536 periods of DACClock */ +#define DACC_MR_STARTUP_1600 (0x19u << 24) /**< \brief (DACC_MR) 1600 periods of DACClock */ +#define DACC_MR_STARTUP_1664 (0x1Au << 24) /**< \brief (DACC_MR) 1664 periods of DACClock */ +#define DACC_MR_STARTUP_1728 (0x1Bu << 24) /**< \brief (DACC_MR) 1728 periods of DACClock */ +#define DACC_MR_STARTUP_1792 (0x1Cu << 24) /**< \brief (DACC_MR) 1792 periods of DACClock */ +#define DACC_MR_STARTUP_1856 (0x1Du << 24) /**< \brief (DACC_MR) 1856 periods of DACClock */ +#define DACC_MR_STARTUP_1920 (0x1Eu << 24) /**< \brief (DACC_MR) 1920 periods of DACClock */ +#define DACC_MR_STARTUP_1984 (0x1Fu << 24) /**< \brief (DACC_MR) 1984 periods of DACClock */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +/* -------- DACC_CDR : (DACC Offset: 0x20) Conversion Data Register -------- */ +#define DACC_CDR_DATA_Pos 0 +#define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /**< \brief (DACC_CDR) Data to Convert */ +#define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable */ +#define DACC_IER_EOC (0x1u << 1) /**< \brief (DACC_IER) End of Conversion Interrupt Enable */ +#define DACC_IER_ENDTX (0x1u << 2) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable */ +#define DACC_IER_TXBUFE (0x1u << 3) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable. */ +#define DACC_IDR_EOC (0x1u << 1) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable */ +#define DACC_IDR_ENDTX (0x1u << 2) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable */ +#define DACC_IDR_TXBUFE (0x1u << 3) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask */ +#define DACC_IMR_EOC (0x1u << 1) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask */ +#define DACC_IMR_ENDTX (0x1u << 2) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask */ +#define DACC_IMR_TXBUFE (0x1u << 3) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag */ +#define DACC_ISR_EOC (0x1u << 1) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag */ +#define DACC_ISR_ENDTX (0x1u << 2) /**< \brief (DACC_ISR) End of DMA Interrupt Flag */ +#define DACC_ISR_TXBUFE (0x1u << 3) /**< \brief (DACC_ISR) Transmit Buffer Empty */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +#define DACC_ACR_IBCTLDACCORE_Pos 8 +#define DACC_ACR_IBCTLDACCORE_Msk (0x3u << DACC_ACR_IBCTLDACCORE_Pos) /**< \brief (DACC_ACR) Bias Current Control for DAC Core */ +#define DACC_ACR_IBCTLDACCORE(value) ((DACC_ACR_IBCTLDACCORE_Msk & ((value) << DACC_ACR_IBCTLDACCORE_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protect Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect KEY */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status register -------- */ +#define DACC_WPSR_WPROTERR (0x1u << 0) /**< \brief (DACC_WPSR) Write protection error */ +#define DACC_WPSR_WPROTADDR_Pos 8 +#define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /**< \brief (DACC_WPSR) Write protection error address */ +/* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ +#define DACC_TPR_TXPTR_Pos 0 +#define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /**< \brief (DACC_TPR) Transmit Counter Register */ +#define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) +/* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ +#define DACC_TCR_TXCTR_Pos 0 +#define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /**< \brief (DACC_TCR) Transmit Counter Register */ +#define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) +/* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define DACC_TNPR_TXNPTR_Pos 0 +#define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /**< \brief (DACC_TNPR) Transmit Next Pointer */ +#define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) +/* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define DACC_TNCR_TXNCTR_Pos 0 +#define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /**< \brief (DACC_TNCR) Transmit Counter Next */ +#define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) +/* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ +#define DACC_PTCR_RXTEN (0x1u << 0) /**< \brief (DACC_PTCR) Receiver Transfer Enable */ +#define DACC_PTCR_RXTDIS (0x1u << 1) /**< \brief (DACC_PTCR) Receiver Transfer Disable */ +#define DACC_PTCR_TXTEN (0x1u << 8) /**< \brief (DACC_PTCR) Transmitter Transfer Enable */ +#define DACC_PTCR_TXTDIS (0x1u << 9) /**< \brief (DACC_PTCR) Transmitter Transfer Disable */ +/* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ +#define DACC_PTSR_RXTEN (0x1u << 0) /**< \brief (DACC_PTSR) Receiver Transfer Enable */ +#define DACC_PTSR_TXTEN (0x1u << 8) /**< \brief (DACC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_DACC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/efc.h b/zephyr/ports/asf/sam3sd8/include/component/efc.h new file mode 100644 index 0000000..2b66bce --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/efc.h @@ -0,0 +1,89 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_EFC_COMPONENT_ +#define _SAM3SD8_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_FAM (0x1u << 24) /**< \brief (EEFC_FMR) Flash Access Mode */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash Descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set Lock Bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear Lock Bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get Lock Bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM Bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM Bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM Bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start Read Unique Identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop Read Unique Identifier */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ + +/*@}*/ + + +#endif /* _SAM3SD8_EFC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/gpbr.h b/zephyr/ports/asf/sam3sd8/include/component/gpbr.h new file mode 100644 index 0000000..ed25fb0 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_GPBR_COMPONENT_ +#define _SAM3SD8_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Register */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_GPBR General Purpose Backup Register */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAM3SD8_GPBR_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/hsmci.h b/zephyr/ports/asf/sam3sd8/include/component/hsmci.h new file mode 100644 index 0000000..bdbd281 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/hsmci.h @@ -0,0 +1,384 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_HSMCI_COMPONENT_ +#define _SAM3SD8_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved3[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved4[5]; + __IO uint32_t HSMCI_RPR; /**< \brief (Hsmci Offset: 0x100) Receive Pointer Register */ + __IO uint32_t HSMCI_RCR; /**< \brief (Hsmci Offset: 0x104) Receive Counter Register */ + __IO uint32_t HSMCI_TPR; /**< \brief (Hsmci Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t HSMCI_TCR; /**< \brief (Hsmci Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t HSMCI_RNPR; /**< \brief (Hsmci Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t HSMCI_RNCR; /**< \brief (Hsmci Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t HSMCI_TNPR; /**< \brief (Hsmci Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t HSMCI_TNCR; /**< \brief (Hsmci Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t HSMCI_PTCR; /**< \brief (Hsmci Offset: 0x120) Transfer Control Register */ + __I uint32_t HSMCI_PTSR; /**< \brief (Hsmci Offset: 0x124) Transfer Status Register */ + __I uint32_t Reserved5[54]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_PDCMODE (0x1u << 15) /**< \brief (HSMCI_MR) PDC-oriented Mode */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCSEL_SLOTB (0x1u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTC (0x2u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCSEL_SLOTD (0x3u << 0) /**< \brief (HSMCI_SDCR) - */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bit */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bit */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response. */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response. */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response. */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SDCard Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge. */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT_MULTIPLE (0x0u << 0) /**< \brief (HSMCI_BLKR) MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. */ +#define HSMCI_BLKR_BCNT_BYTE (0x4u << 0) /**< \brief (HSMCI_BLKR) SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BCNT_BLOCK (0x5u << 0) /**< \brief (HSMCI_BLKR) SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. */ +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_ENDRX (0x1u << 6) /**< \brief (HSMCI_SR) End of RX Buffer */ +#define HSMCI_SR_ENDTX (0x1u << 7) /**< \brief (HSMCI_SR) End of TX Buffer */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received */ +#define HSMCI_SR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_SR) RX Buffer Full */ +#define HSMCI_SR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_SR) TX Buffer Empty */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_ENDRX (0x1u << 6) /**< \brief (HSMCI_IER) End of Receive Buffer Interrupt Enable */ +#define HSMCI_IER_ENDTX (0x1u << 7) /**< \brief (HSMCI_IER) End of Transmit Buffer Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IER) Receive Buffer Full Interrupt Enable */ +#define HSMCI_IER_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IER) Transmit Buffer Empty Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IDR) End of Receive Buffer Interrupt Disable */ +#define HSMCI_IDR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IDR) End of Transmit Buffer Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IDR) Receive Buffer Full Interrupt Disable */ +#define HSMCI_IDR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_ENDRX (0x1u << 6) /**< \brief (HSMCI_IMR) End of Receive Buffer Interrupt Mask */ +#define HSMCI_IMR_ENDTX (0x1u << 7) /**< \brief (HSMCI_IMR) End of Transmit Buffer Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RXBUFF (0x1u << 14) /**< \brief (HSMCI_IMR) Receive Buffer Full Interrupt Mask */ +#define HSMCI_IMR_TXBUFE (0x1u << 15) /**< \brief (HSMCI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WP_EN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protection Enable */ +#define HSMCI_WPMR_WP_KEY_Pos 8 +#define HSMCI_WPMR_WP_KEY_Msk (0xffffffu << HSMCI_WPMR_WP_KEY_Pos) /**< \brief (HSMCI_WPMR) Write Protection Key password */ +#define HSMCI_WPMR_WP_KEY(value) ((HSMCI_WPMR_WP_KEY_Msk & ((value) << HSMCI_WPMR_WP_KEY_Pos))) +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WP_VS_Pos 0 +#define HSMCI_WPSR_WP_VS_Msk (0xfu << HSMCI_WPSR_WP_VS_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WP_VS_NONE (0x0u << 0) /**< \brief (HSMCI_WPSR) No Write Protection Violation occurred since the last read of this register (WP_SR) */ +#define HSMCI_WPSR_WP_VS_WRITE (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) */ +#define HSMCI_WPSR_WP_VS_RESET (0x2u << 0) /**< \brief (HSMCI_WPSR) Software reset had been performed while Write Protection was enabled (since the last read). */ +#define HSMCI_WPSR_WP_VS_BOTH (0x3u << 0) /**< \brief (HSMCI_WPSR) Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. */ +#define HSMCI_WPSR_WP_VSRC_Pos 8 +#define HSMCI_WPSR_WP_VSRC_Msk (0xffffu << HSMCI_WPSR_WP_VSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation SouRCe */ +/* -------- HSMCI_RPR : (HSMCI Offset: 0x100) Receive Pointer Register -------- */ +#define HSMCI_RPR_RXPTR_Pos 0 +#define HSMCI_RPR_RXPTR_Msk (0xffffffffu << HSMCI_RPR_RXPTR_Pos) /**< \brief (HSMCI_RPR) Receive Pointer Register */ +#define HSMCI_RPR_RXPTR(value) ((HSMCI_RPR_RXPTR_Msk & ((value) << HSMCI_RPR_RXPTR_Pos))) +/* -------- HSMCI_RCR : (HSMCI Offset: 0x104) Receive Counter Register -------- */ +#define HSMCI_RCR_RXCTR_Pos 0 +#define HSMCI_RCR_RXCTR_Msk (0xffffu << HSMCI_RCR_RXCTR_Pos) /**< \brief (HSMCI_RCR) Receive Counter Register */ +#define HSMCI_RCR_RXCTR(value) ((HSMCI_RCR_RXCTR_Msk & ((value) << HSMCI_RCR_RXCTR_Pos))) +/* -------- HSMCI_TPR : (HSMCI Offset: 0x108) Transmit Pointer Register -------- */ +#define HSMCI_TPR_TXPTR_Pos 0 +#define HSMCI_TPR_TXPTR_Msk (0xffffffffu << HSMCI_TPR_TXPTR_Pos) /**< \brief (HSMCI_TPR) Transmit Counter Register */ +#define HSMCI_TPR_TXPTR(value) ((HSMCI_TPR_TXPTR_Msk & ((value) << HSMCI_TPR_TXPTR_Pos))) +/* -------- HSMCI_TCR : (HSMCI Offset: 0x10C) Transmit Counter Register -------- */ +#define HSMCI_TCR_TXCTR_Pos 0 +#define HSMCI_TCR_TXCTR_Msk (0xffffu << HSMCI_TCR_TXCTR_Pos) /**< \brief (HSMCI_TCR) Transmit Counter Register */ +#define HSMCI_TCR_TXCTR(value) ((HSMCI_TCR_TXCTR_Msk & ((value) << HSMCI_TCR_TXCTR_Pos))) +/* -------- HSMCI_RNPR : (HSMCI Offset: 0x110) Receive Next Pointer Register -------- */ +#define HSMCI_RNPR_RXNPTR_Pos 0 +#define HSMCI_RNPR_RXNPTR_Msk (0xffffffffu << HSMCI_RNPR_RXNPTR_Pos) /**< \brief (HSMCI_RNPR) Receive Next Pointer */ +#define HSMCI_RNPR_RXNPTR(value) ((HSMCI_RNPR_RXNPTR_Msk & ((value) << HSMCI_RNPR_RXNPTR_Pos))) +/* -------- HSMCI_RNCR : (HSMCI Offset: 0x114) Receive Next Counter Register -------- */ +#define HSMCI_RNCR_RXNCTR_Pos 0 +#define HSMCI_RNCR_RXNCTR_Msk (0xffffu << HSMCI_RNCR_RXNCTR_Pos) /**< \brief (HSMCI_RNCR) Receive Next Counter */ +#define HSMCI_RNCR_RXNCTR(value) ((HSMCI_RNCR_RXNCTR_Msk & ((value) << HSMCI_RNCR_RXNCTR_Pos))) +/* -------- HSMCI_TNPR : (HSMCI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define HSMCI_TNPR_TXNPTR_Pos 0 +#define HSMCI_TNPR_TXNPTR_Msk (0xffffffffu << HSMCI_TNPR_TXNPTR_Pos) /**< \brief (HSMCI_TNPR) Transmit Next Pointer */ +#define HSMCI_TNPR_TXNPTR(value) ((HSMCI_TNPR_TXNPTR_Msk & ((value) << HSMCI_TNPR_TXNPTR_Pos))) +/* -------- HSMCI_TNCR : (HSMCI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define HSMCI_TNCR_TXNCTR_Pos 0 +#define HSMCI_TNCR_TXNCTR_Msk (0xffffu << HSMCI_TNCR_TXNCTR_Pos) /**< \brief (HSMCI_TNCR) Transmit Counter Next */ +#define HSMCI_TNCR_TXNCTR(value) ((HSMCI_TNCR_TXNCTR_Msk & ((value) << HSMCI_TNCR_TXNCTR_Pos))) +/* -------- HSMCI_PTCR : (HSMCI Offset: 0x120) Transfer Control Register -------- */ +#define HSMCI_PTCR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTCR) Receiver Transfer Enable */ +#define HSMCI_PTCR_RXTDIS (0x1u << 1) /**< \brief (HSMCI_PTCR) Receiver Transfer Disable */ +#define HSMCI_PTCR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTCR) Transmitter Transfer Enable */ +#define HSMCI_PTCR_TXTDIS (0x1u << 9) /**< \brief (HSMCI_PTCR) Transmitter Transfer Disable */ +/* -------- HSMCI_PTSR : (HSMCI Offset: 0x124) Transfer Status Register -------- */ +#define HSMCI_PTSR_RXTEN (0x1u << 0) /**< \brief (HSMCI_PTSR) Receiver Transfer Enable */ +#define HSMCI_PTSR_TXTEN (0x1u << 8) /**< \brief (HSMCI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_HSMCI_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/matrix.h b/zephyr/ports/asf/sam3sd8/include/component/matrix.h new file mode 100644 index 0000000..448658c --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/matrix.h @@ -0,0 +1,188 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_MATRIX_COMPONENT_ +#define _SAM3SD8_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Matrix hardware registers */ +typedef struct { + __IO uint32_t MATRIX_MCFG[4]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + __I uint32_t Reserved1[12]; + __IO uint32_t MATRIX_SCFG[5]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved2[11]; + __IO uint32_t MATRIX_PRAS0; /**< \brief (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ + __I uint32_t Reserved3[1]; + __IO uint32_t MATRIX_PRAS1; /**< \brief (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ + __I uint32_t Reserved4[1]; + __IO uint32_t MATRIX_PRAS2; /**< \brief (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ + __I uint32_t Reserved5[1]; + __IO uint32_t MATRIX_PRAS3; /**< \brief (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ + __I uint32_t Reserved6[1]; + __IO uint32_t MATRIX_PRAS4; /**< \brief (Matrix Offset: 0x00A0) Priority Register A for Slave 4 */ + __I uint32_t Reserved7[1]; + __I uint32_t Reserved8[27]; + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O Configuration register */ + __I uint32_t Reserved9[1]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register */ + __I uint32_t Reserved10[49]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x1E4) Write Protect Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x1E8) Write Protect Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[4] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[4]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +/* -------- MATRIX_SCFG[5] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[5]) Maximum Number of Allowed Cycles for a Burst */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[5]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[5]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +#define MATRIX_SCFG_ARBT_Pos 24 +#define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /**< \brief (MATRIX_SCFG[5]) Arbitration Type */ +#define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) +/* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS0_M0PR_Pos 0 +#define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /**< \brief (MATRIX_PRAS0) Master 0 Priority */ +#define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) +#define MATRIX_PRAS0_M1PR_Pos 4 +#define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /**< \brief (MATRIX_PRAS0) Master 1 Priority */ +#define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) +#define MATRIX_PRAS0_M2PR_Pos 8 +#define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /**< \brief (MATRIX_PRAS0) Master 2 Priority */ +#define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) +#define MATRIX_PRAS0_M3PR_Pos 12 +#define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /**< \brief (MATRIX_PRAS0) Master 3 Priority */ +#define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) +#define MATRIX_PRAS0_M4PR_Pos 16 +#define MATRIX_PRAS0_M4PR_Msk (0x3u << MATRIX_PRAS0_M4PR_Pos) /**< \brief (MATRIX_PRAS0) Master 4 Priority */ +#define MATRIX_PRAS0_M4PR(value) ((MATRIX_PRAS0_M4PR_Msk & ((value) << MATRIX_PRAS0_M4PR_Pos))) +/* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ +#define MATRIX_PRAS1_M0PR_Pos 0 +#define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /**< \brief (MATRIX_PRAS1) Master 0 Priority */ +#define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) +#define MATRIX_PRAS1_M1PR_Pos 4 +#define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /**< \brief (MATRIX_PRAS1) Master 1 Priority */ +#define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) +#define MATRIX_PRAS1_M2PR_Pos 8 +#define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /**< \brief (MATRIX_PRAS1) Master 2 Priority */ +#define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) +#define MATRIX_PRAS1_M3PR_Pos 12 +#define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /**< \brief (MATRIX_PRAS1) Master 3 Priority */ +#define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) +#define MATRIX_PRAS1_M4PR_Pos 16 +#define MATRIX_PRAS1_M4PR_Msk (0x3u << MATRIX_PRAS1_M4PR_Pos) /**< \brief (MATRIX_PRAS1) Master 4 Priority */ +#define MATRIX_PRAS1_M4PR(value) ((MATRIX_PRAS1_M4PR_Msk & ((value) << MATRIX_PRAS1_M4PR_Pos))) +/* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ +#define MATRIX_PRAS2_M0PR_Pos 0 +#define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /**< \brief (MATRIX_PRAS2) Master 0 Priority */ +#define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) +#define MATRIX_PRAS2_M1PR_Pos 4 +#define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /**< \brief (MATRIX_PRAS2) Master 1 Priority */ +#define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) +#define MATRIX_PRAS2_M2PR_Pos 8 +#define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /**< \brief (MATRIX_PRAS2) Master 2 Priority */ +#define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) +#define MATRIX_PRAS2_M3PR_Pos 12 +#define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /**< \brief (MATRIX_PRAS2) Master 3 Priority */ +#define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) +#define MATRIX_PRAS2_M4PR_Pos 16 +#define MATRIX_PRAS2_M4PR_Msk (0x3u << MATRIX_PRAS2_M4PR_Pos) /**< \brief (MATRIX_PRAS2) Master 4 Priority */ +#define MATRIX_PRAS2_M4PR(value) ((MATRIX_PRAS2_M4PR_Msk & ((value) << MATRIX_PRAS2_M4PR_Pos))) +/* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ +#define MATRIX_PRAS3_M0PR_Pos 0 +#define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /**< \brief (MATRIX_PRAS3) Master 0 Priority */ +#define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) +#define MATRIX_PRAS3_M1PR_Pos 4 +#define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /**< \brief (MATRIX_PRAS3) Master 1 Priority */ +#define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) +#define MATRIX_PRAS3_M2PR_Pos 8 +#define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /**< \brief (MATRIX_PRAS3) Master 2 Priority */ +#define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) +#define MATRIX_PRAS3_M3PR_Pos 12 +#define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /**< \brief (MATRIX_PRAS3) Master 3 Priority */ +#define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) +#define MATRIX_PRAS3_M4PR_Pos 16 +#define MATRIX_PRAS3_M4PR_Msk (0x3u << MATRIX_PRAS3_M4PR_Pos) /**< \brief (MATRIX_PRAS3) Master 4 Priority */ +#define MATRIX_PRAS3_M4PR(value) ((MATRIX_PRAS3_M4PR_Msk & ((value) << MATRIX_PRAS3_M4PR_Pos))) +/* -------- MATRIX_PRAS4 : (MATRIX Offset: 0x00A0) Priority Register A for Slave 4 -------- */ +#define MATRIX_PRAS4_M0PR_Pos 0 +#define MATRIX_PRAS4_M0PR_Msk (0x3u << MATRIX_PRAS4_M0PR_Pos) /**< \brief (MATRIX_PRAS4) Master 0 Priority */ +#define MATRIX_PRAS4_M0PR(value) ((MATRIX_PRAS4_M0PR_Msk & ((value) << MATRIX_PRAS4_M0PR_Pos))) +#define MATRIX_PRAS4_M1PR_Pos 4 +#define MATRIX_PRAS4_M1PR_Msk (0x3u << MATRIX_PRAS4_M1PR_Pos) /**< \brief (MATRIX_PRAS4) Master 1 Priority */ +#define MATRIX_PRAS4_M1PR(value) ((MATRIX_PRAS4_M1PR_Msk & ((value) << MATRIX_PRAS4_M1PR_Pos))) +#define MATRIX_PRAS4_M2PR_Pos 8 +#define MATRIX_PRAS4_M2PR_Msk (0x3u << MATRIX_PRAS4_M2PR_Pos) /**< \brief (MATRIX_PRAS4) Master 2 Priority */ +#define MATRIX_PRAS4_M2PR(value) ((MATRIX_PRAS4_M2PR_Msk & ((value) << MATRIX_PRAS4_M2PR_Pos))) +#define MATRIX_PRAS4_M3PR_Pos 12 +#define MATRIX_PRAS4_M3PR_Msk (0x3u << MATRIX_PRAS4_M3PR_Pos) /**< \brief (MATRIX_PRAS4) Master 3 Priority */ +#define MATRIX_PRAS4_M3PR(value) ((MATRIX_PRAS4_M3PR_Msk & ((value) << MATRIX_PRAS4_M3PR_Pos))) +#define MATRIX_PRAS4_M4PR_Pos 16 +#define MATRIX_PRAS4_M4PR_Msk (0x3u << MATRIX_PRAS4_M4PR_Pos) /**< \brief (MATRIX_PRAS4) Master 4 Priority */ +#define MATRIX_PRAS4_M4PR(value) ((MATRIX_PRAS4_M4PR_Msk & ((value) << MATRIX_PRAS4_M4PR_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO10 (0x1u << 10) /**< \brief (CCFG_SYSIO) PB10 or DDM Assignment */ +#define CCFG_SYSIO_SYSIO11 (0x1u << 11) /**< \brief (CCFG_SYSIO) PB11 or DDP Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x011C) SMC Chip Select NAND Flash Assignment Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protect ENable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protect KEY (Write-only) */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protect Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3SD8_MATRIX_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/pdc.h b/zephyr/ports/asf/sam3sd8/include/component/pdc.h new file mode 100644 index 0000000..9a1c8d9 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/pdc.h @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PDC_COMPONENT_ +#define _SAM3SD8_PDC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_PDC Peripheral DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pdc hardware registers */ +typedef struct { + __IO uint32_t PERIPH_RPR; /**< \brief (Pdc Offset: 0x0) Receive Pointer Register */ + __IO uint32_t PERIPH_RCR; /**< \brief (Pdc Offset: 0x4) Receive Counter Register */ + __IO uint32_t PERIPH_TPR; /**< \brief (Pdc Offset: 0x8) Transmit Pointer Register */ + __IO uint32_t PERIPH_TCR; /**< \brief (Pdc Offset: 0xC) Transmit Counter Register */ + __IO uint32_t PERIPH_RNPR; /**< \brief (Pdc Offset: 0x10) Receive Next Pointer Register */ + __IO uint32_t PERIPH_RNCR; /**< \brief (Pdc Offset: 0x14) Receive Next Counter Register */ + __IO uint32_t PERIPH_TNPR; /**< \brief (Pdc Offset: 0x18) Transmit Next Pointer Register */ + __IO uint32_t PERIPH_TNCR; /**< \brief (Pdc Offset: 0x1C) Transmit Next Counter Register */ + __O uint32_t PERIPH_PTCR; /**< \brief (Pdc Offset: 0x20) Transfer Control Register */ + __I uint32_t PERIPH_PTSR; /**< \brief (Pdc Offset: 0x24) Transfer Status Register */ +} Pdc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PERIPH_RPR : (PDC Offset: 0x0) Receive Pointer Register -------- */ +#define PERIPH_RPR_RXPTR_Pos 0 +#define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /**< \brief (PERIPH_RPR) Receive Pointer Register */ +#define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) +/* -------- PERIPH_RCR : (PDC Offset: 0x4) Receive Counter Register -------- */ +#define PERIPH_RCR_RXCTR_Pos 0 +#define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /**< \brief (PERIPH_RCR) Receive Counter Register */ +#define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) +/* -------- PERIPH_TPR : (PDC Offset: 0x8) Transmit Pointer Register -------- */ +#define PERIPH_TPR_TXPTR_Pos 0 +#define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /**< \brief (PERIPH_TPR) Transmit Counter Register */ +#define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) +/* -------- PERIPH_TCR : (PDC Offset: 0xC) Transmit Counter Register -------- */ +#define PERIPH_TCR_TXCTR_Pos 0 +#define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /**< \brief (PERIPH_TCR) Transmit Counter Register */ +#define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) +/* -------- PERIPH_RNPR : (PDC Offset: 0x10) Receive Next Pointer Register -------- */ +#define PERIPH_RNPR_RXNPTR_Pos 0 +#define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /**< \brief (PERIPH_RNPR) Receive Next Pointer */ +#define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) +/* -------- PERIPH_RNCR : (PDC Offset: 0x14) Receive Next Counter Register -------- */ +#define PERIPH_RNCR_RXNCTR_Pos 0 +#define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /**< \brief (PERIPH_RNCR) Receive Next Counter */ +#define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) +/* -------- PERIPH_TNPR : (PDC Offset: 0x18) Transmit Next Pointer Register -------- */ +#define PERIPH_TNPR_TXNPTR_Pos 0 +#define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /**< \brief (PERIPH_TNPR) Transmit Next Pointer */ +#define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) +/* -------- PERIPH_TNCR : (PDC Offset: 0x1C) Transmit Next Counter Register -------- */ +#define PERIPH_TNCR_TXNCTR_Pos 0 +#define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /**< \brief (PERIPH_TNCR) Transmit Counter Next */ +#define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) +/* -------- PERIPH_PTCR : (PDC Offset: 0x20) Transfer Control Register -------- */ +#define PERIPH_PTCR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTCR) Receiver Transfer Enable */ +#define PERIPH_PTCR_RXTDIS (0x1u << 1) /**< \brief (PERIPH_PTCR) Receiver Transfer Disable */ +#define PERIPH_PTCR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTCR) Transmitter Transfer Enable */ +#define PERIPH_PTCR_TXTDIS (0x1u << 9) /**< \brief (PERIPH_PTCR) Transmitter Transfer Disable */ +/* -------- PERIPH_PTSR : (PDC Offset: 0x24) Transfer Status Register -------- */ +#define PERIPH_PTSR_RXTEN (0x1u << 0) /**< \brief (PERIPH_PTSR) Receiver Transfer Enable */ +#define PERIPH_PTSR_TXTEN (0x1u << 8) /**< \brief (PERIPH_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_PDC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/pio.h b/zephyr/ports/asf/sam3sd8/include/component/pio.h new file mode 100644 index 0000000..3f07b9c --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/pio.h @@ -0,0 +1,1644 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PIO_COMPONENT_ +#define _SAM3SD8_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protect Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protect Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[19]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x164) Parallel Capture Reception Holding Register */ + __IO uint32_t PIO_RPR; /**< \brief (Pio Offset: 0x168) Receive Pointer Register */ + __IO uint32_t PIO_RCR; /**< \brief (Pio Offset: 0x16C) Receive Counter Register */ + __I uint32_t Reserved14[2]; + __IO uint32_t PIO_RNPR; /**< \brief (Pio Offset: 0x178) Receive Next Pointer Register */ + __IO uint32_t PIO_RNCR; /**< \brief (Pio Offset: 0x17C) Receive Next Counter Register */ + __I uint32_t Reserved15[2]; + __O uint32_t PIO_PTCR; /**< \brief (Pio Offset: 0x188) Transfer Control Register */ + __I uint32_t PIO_PTSR; /**< \brief (Pio Offset: 0x18C) Transfer Status Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filer Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filer Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi Drive Enable. */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi Drive Enable. */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi Drive Disable. */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi Drive Status. */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi Drive Status. */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull Up Disable. */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull Up Disable. */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull Up Enable. */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull Up Enable. */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull Up Status. */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull Up Status. */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select. */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Debouncing Filtering Select. */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull Down Disable. */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull Down Enable. */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull Down Enable. */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull Down Status. */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull Down Status. */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable. */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable. */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable. */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable. */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status. */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status. */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable. */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable. */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) Peripheral CD Status. */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection. */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection. */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt source selection. */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status. */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status. */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protect Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protect KEY */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protect Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protect Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) */ +/* -------- PIO_PCMR : (PIO Offset: 0x150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a BYTE (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR register is a WORD (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x15C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error. */ +#define PIO_PCISR_ENDRX (0x1u << 2) /**< \brief (PIO_PCISR) End of Reception Transfer. */ +#define PIO_PCISR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCISR) Reception Buffer Full */ +/* -------- PIO_PCRHR : (PIO Offset: 0x164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data. */ +/* -------- PIO_RPR : (PIO Offset: 0x168) Receive Pointer Register -------- */ +#define PIO_RPR_RXPTR_Pos 0 +#define PIO_RPR_RXPTR_Msk (0xffffffffu << PIO_RPR_RXPTR_Pos) /**< \brief (PIO_RPR) Receive Pointer Register */ +#define PIO_RPR_RXPTR(value) ((PIO_RPR_RXPTR_Msk & ((value) << PIO_RPR_RXPTR_Pos))) +/* -------- PIO_RCR : (PIO Offset: 0x16C) Receive Counter Register -------- */ +#define PIO_RCR_RXCTR_Pos 0 +#define PIO_RCR_RXCTR_Msk (0xffffu << PIO_RCR_RXCTR_Pos) /**< \brief (PIO_RCR) Receive Counter Register */ +#define PIO_RCR_RXCTR(value) ((PIO_RCR_RXCTR_Msk & ((value) << PIO_RCR_RXCTR_Pos))) +/* -------- PIO_RNPR : (PIO Offset: 0x178) Receive Next Pointer Register -------- */ +#define PIO_RNPR_RXNPTR_Pos 0 +#define PIO_RNPR_RXNPTR_Msk (0xffffffffu << PIO_RNPR_RXNPTR_Pos) /**< \brief (PIO_RNPR) Receive Next Pointer */ +#define PIO_RNPR_RXNPTR(value) ((PIO_RNPR_RXNPTR_Msk & ((value) << PIO_RNPR_RXNPTR_Pos))) +/* -------- PIO_RNCR : (PIO Offset: 0x17C) Receive Next Counter Register -------- */ +#define PIO_RNCR_RXNCTR_Pos 0 +#define PIO_RNCR_RXNCTR_Msk (0xffffu << PIO_RNCR_RXNCTR_Pos) /**< \brief (PIO_RNCR) Receive Next Counter */ +#define PIO_RNCR_RXNCTR(value) ((PIO_RNCR_RXNCTR_Msk & ((value) << PIO_RNCR_RXNCTR_Pos))) +/* -------- PIO_PTCR : (PIO Offset: 0x188) Transfer Control Register -------- */ +#define PIO_PTCR_RXTEN (0x1u << 0) /**< \brief (PIO_PTCR) Receiver Transfer Enable */ +#define PIO_PTCR_RXTDIS (0x1u << 1) /**< \brief (PIO_PTCR) Receiver Transfer Disable */ +#define PIO_PTCR_TXTEN (0x1u << 8) /**< \brief (PIO_PTCR) Transmitter Transfer Enable */ +#define PIO_PTCR_TXTDIS (0x1u << 9) /**< \brief (PIO_PTCR) Transmitter Transfer Disable */ +/* -------- PIO_PTSR : (PIO Offset: 0x18C) Transfer Status Register -------- */ +#define PIO_PTSR_RXTEN (0x1u << 0) /**< \brief (PIO_PTSR) Receiver Transfer Enable */ +#define PIO_PTSR_TXTEN (0x1u << 8) /**< \brief (PIO_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_PIO_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/pmc.h b/zephyr/ports/asf/sam3sd8/include/component/pmc.h new file mode 100644 index 0000000..2256c9e --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/pmc.h @@ -0,0 +1,393 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PMC_COMPONENT_ +#define _SAM3SD8_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __I uint32_t Reserved2[1]; + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __IO uint32_t CKGR_PLLBR; /**< \brief (Pmc Offset: 0x002C) PLLB Register */ + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[3]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[5]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protect Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protect Status Register */ + __I uint32_t Reserved7[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __I uint32_t Reserved8[1]; + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_UDP (0x1u << 7) /**< \brief (PMC_SCER) USB Device Port Clock Enable */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_UDP (0x1u << 7) /**< \brief (PMC_SCDR) USB Device Port Clock Disable */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_UDP (0x1u << 7) /**< \brief (PMC_SCSR) USB Device Port Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID2 (0x1u << 2) /**< \brief (PMC_PCER0) Peripheral Clock 2 Enable */ +#define PMC_PCER0_PID3 (0x1u << 3) /**< \brief (PMC_PCER0) Peripheral Clock 3 Enable */ +#define PMC_PCER0_PID4 (0x1u << 4) /**< \brief (PMC_PCER0) Peripheral Clock 4 Enable */ +#define PMC_PCER0_PID5 (0x1u << 5) /**< \brief (PMC_PCER0) Peripheral Clock 5 Enable */ +#define PMC_PCER0_PID6 (0x1u << 6) /**< \brief (PMC_PCER0) Peripheral Clock 6 Enable */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID2 (0x1u << 2) /**< \brief (PMC_PCDR0) Peripheral Clock 2 Disable */ +#define PMC_PCDR0_PID3 (0x1u << 3) /**< \brief (PMC_PCDR0) Peripheral Clock 3 Disable */ +#define PMC_PCDR0_PID4 (0x1u << 4) /**< \brief (PMC_PCDR0) Peripheral Clock 4 Disable */ +#define PMC_PCDR0_PID5 (0x1u << 5) /**< \brief (PMC_PCDR0) Peripheral Clock 5 Disable */ +#define PMC_PCDR0_PID6 (0x1u << 6) /**< \brief (PMC_PCDR0) Peripheral Clock 6 Disable */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID2 (0x1u << 2) /**< \brief (PMC_PCSR0) Peripheral Clock 2 Status */ +#define PMC_PCSR0_PID3 (0x1u << 3) /**< \brief (PMC_PCSR0) Peripheral Clock 3 Status */ +#define PMC_PCSR0_PID4 (0x1u << 4) /**< \brief (PMC_PCSR0) Peripheral Clock 4 Status */ +#define PMC_PCSR0_PID5 (0x1u << 5) /**< \brief (PMC_PCSR0) Peripheral Clock 5 Status */ +#define PMC_PCSR0_PID6 (0x1u << 6) /**< \brief (PMC_PCSR0) Peripheral Clock 6 Status */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- CKGR_PLLBR : (PMC Offset: 0x002C) PLLB Register -------- */ +#define CKGR_PLLBR_DIVB_Pos 0 +#define CKGR_PLLBR_DIVB_Msk (0xffu << CKGR_PLLBR_DIVB_Pos) /**< \brief (CKGR_PLLBR) Divider */ +#define CKGR_PLLBR_DIVB(value) ((CKGR_PLLBR_DIVB_Msk & ((value) << CKGR_PLLBR_DIVB_Pos))) +#define CKGR_PLLBR_PLLBCOUNT_Pos 8 +#define CKGR_PLLBR_PLLBCOUNT_Msk (0x3fu << CKGR_PLLBR_PLLBCOUNT_Pos) /**< \brief (CKGR_PLLBR) PLLB Counter */ +#define CKGR_PLLBR_PLLBCOUNT(value) ((CKGR_PLLBR_PLLBCOUNT_Msk & ((value) << CKGR_PLLBR_PLLBCOUNT_Pos))) +#define CKGR_PLLBR_MULB_Pos 16 +#define CKGR_PLLBR_MULB_Msk (0x7ffu << CKGR_PLLBR_MULB_Pos) /**< \brief (CKGR_PLLBR) PLLB Multiplier */ +#define CKGR_PLLBR_MULB(value) ((CKGR_PLLBR_MULB_Msk & ((value) << CKGR_PLLBR_MULB_Pos))) +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_MCKR) PLLBClock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_PLLADIV2 (0x1u << 12) /**< \brief (PMC_MCKR) PLLA Divisor by 2 */ +#define PMC_MCKR_PLLBDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) PLLB Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock. */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[3]) Master Clock Source Selection */ +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[3]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[3]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[3]) PLLA Clock is selected */ +#define PMC_PCK_CSS_PLLB_CLK (0x3u << 0) /**< \brief (PMC_PCK[3]) PLLB Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[3]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[3]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_PCK[3]) Selected clock */ +#define PMC_PCK_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 2 */ +#define PMC_PCK_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 4 */ +#define PMC_PCK_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 8 */ +#define PMC_PCK_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 16 */ +#define PMC_PCK_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 32 */ +#define PMC_PCK_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_PCK[3]) Selected clock divided by 64 */ +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_LOCKB (0x1u << 2) /**< \brief (PMC_IER) PLLB Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_LOCKB (0x1u << 2) /**< \brief (PMC_IDR) PLLB Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main XTAL Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_LOCKB (0x1u << 2) /**< \brief (PMC_SR) PLLB Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_LOCKB (0x1u << 2) /**< \brief (PMC_IMR) PLLB Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low Power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarityx */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protect Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protect KEY */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protect Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protect Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 Mhz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 Mhz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 Mhz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 Mhz */ + +/*@}*/ + + +#endif /* _SAM3SD8_PMC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/pwm.h b/zephyr/ports/asf/sam3sd8/include/component/pwm.h new file mode 100644 index 0000000..2840a55 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/pwm.h @@ -0,0 +1,538 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PWM_COMPONENT_ +#define _SAM3SD8_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t PWM_ELMR[2]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved3[24]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protect Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protect Status Register */ + __I uint32_t Reserved4[7]; + __IO uint32_t PWM_TPR; /**< \brief (Pwm Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t PWM_TCR; /**< \brief (Pwm Offset: 0x10C) Transmit Counter Register */ + __I uint32_t Reserved5[2]; + __IO uint32_t PWM_TNPR; /**< \brief (Pwm Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t PWM_TNCR; /**< \brief (Pwm Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t PWM_PTCR; /**< \brief (Pwm Offset: 0x120) Transfer Control Register */ + __I uint32_t PWM_PTSR; /**< \brief (Pwm Offset: 0x124) Transfer Status Register */ + __I uint32_t Reserved6[2]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKA, CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) PDC Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) PDC Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_ENDTX (0x1u << 1) /**< \brief (PWM_IER2) PDC End of TX Buffer Interrupt Enable */ +#define PWM_IER2_TXBUFE (0x1u << 2) /**< \brief (PWM_IER2) PDC TX Buffer Empty Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_ENDTX (0x1u << 1) /**< \brief (PWM_IDR2) PDC End of TX Buffer Interrupt Disable */ +#define PWM_IDR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IDR2) PDC TX Buffer Empty Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_ENDTX (0x1u << 1) /**< \brief (PWM_IMR2) PDC End of TX Buffer Interrupt Mask */ +#define PWM_IMR2_TXBUFE (0x1u << 2) /**< \brief (PWM_IMR2) PDC TX Buffer Empty Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_ENDTX (0x1u << 1) /**< \brief (PWM_ISR2) PDC End of TX Buffer */ +#define PWM_ISR2_TXBUFE (0x1u << 2) /**< \brief (PWM_ISR2) PDC TX Buffer Empty */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering (fault input bit varies from 0 to 5) */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value (fault input bit varies from 0 to 5) */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status (fault input bit varies from 0 to 5) */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear (fault input bit varies from 0 to 5) */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV : (PWM Offset: 0x68) PWM Fault Protection Value Register -------- */ +#define PWM_FPV_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[2] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[2]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[2]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[2]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[2]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[2]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[2]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[2]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[2]) Comparison 7 Selection */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protect Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protect Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protect Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protect Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protect Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protect Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protect Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protect Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protect Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protect Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_TPR : (PWM Offset: 0x108) Transmit Pointer Register -------- */ +#define PWM_TPR_TXPTR_Pos 0 +#define PWM_TPR_TXPTR_Msk (0xffffffffu << PWM_TPR_TXPTR_Pos) /**< \brief (PWM_TPR) Transmit Counter Register */ +#define PWM_TPR_TXPTR(value) ((PWM_TPR_TXPTR_Msk & ((value) << PWM_TPR_TXPTR_Pos))) +/* -------- PWM_TCR : (PWM Offset: 0x10C) Transmit Counter Register -------- */ +#define PWM_TCR_TXCTR_Pos 0 +#define PWM_TCR_TXCTR_Msk (0xffffu << PWM_TCR_TXCTR_Pos) /**< \brief (PWM_TCR) Transmit Counter Register */ +#define PWM_TCR_TXCTR(value) ((PWM_TCR_TXCTR_Msk & ((value) << PWM_TCR_TXCTR_Pos))) +/* -------- PWM_TNPR : (PWM Offset: 0x118) Transmit Next Pointer Register -------- */ +#define PWM_TNPR_TXNPTR_Pos 0 +#define PWM_TNPR_TXNPTR_Msk (0xffffffffu << PWM_TNPR_TXNPTR_Pos) /**< \brief (PWM_TNPR) Transmit Next Pointer */ +#define PWM_TNPR_TXNPTR(value) ((PWM_TNPR_TXNPTR_Msk & ((value) << PWM_TNPR_TXNPTR_Pos))) +/* -------- PWM_TNCR : (PWM Offset: 0x11C) Transmit Next Counter Register -------- */ +#define PWM_TNCR_TXNCTR_Pos 0 +#define PWM_TNCR_TXNCTR_Msk (0xffffu << PWM_TNCR_TXNCTR_Pos) /**< \brief (PWM_TNCR) Transmit Counter Next */ +#define PWM_TNCR_TXNCTR(value) ((PWM_TNCR_TXNCTR_Msk & ((value) << PWM_TNCR_TXNCTR_Pos))) +/* -------- PWM_PTCR : (PWM Offset: 0x120) Transfer Control Register -------- */ +#define PWM_PTCR_RXTEN (0x1u << 0) /**< \brief (PWM_PTCR) Receiver Transfer Enable */ +#define PWM_PTCR_RXTDIS (0x1u << 1) /**< \brief (PWM_PTCR) Receiver Transfer Disable */ +#define PWM_PTCR_TXTEN (0x1u << 8) /**< \brief (PWM_PTCR) Transmitter Transfer Enable */ +#define PWM_PTCR_TXTDIS (0x1u << 9) /**< \brief (PWM_PTCR) Transmitter Transfer Disable */ +/* -------- PWM_PTSR : (PWM Offset: 0x124) Transfer Status Register -------- */ +#define PWM_PTSR_RXTEN (0x1u << 0) /**< \brief (PWM_PTSR) Receiver Transfer Enable */ +#define PWM_PTSR_TXTEN (0x1u << 8) /**< \brief (PWM_PTSR) Transmitter Transfer Enable */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Master clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Master clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Master clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Master clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Master clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Master clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Master clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Master clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Master clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Master clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Master clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) + +/*@}*/ + + +#endif /* _SAM3SD8_PWM_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/rstc.h b/zephyr/ports/asf/sam3sd8/include/component/rstc.h new file mode 100644 index 0000000..50152d3 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/rstc.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_RSTC_COMPONENT_ +#define _SAM3SD8_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_PERRST (0x1u << 2) /**< \brief (RSTC_CR) Peripheral Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) + +/*@}*/ + + +#endif /* _SAM3SD8_RSTC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/rtc.h b/zephyr/ports/asf/sam3sd8/include/component/rtc.h new file mode 100644 index 0000000..5b34b6e --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/rtc.h @@ -0,0 +1,219 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_RTC_COMPONENT_ +#define _SAM3SD8_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 Output Source Selection */ +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) no waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) no waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of RTC_SR. */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + + +#endif /* _SAM3SD8_RTC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/rtt.h b/zephyr/ports/asf/sam3sd8/include/component/rtt.h new file mode 100644 index 0000000..3f97d3a --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_RTT_COMPONENT_ +#define _SAM3SD8_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Real-time Timer Increment */ + +/*@}*/ + + +#endif /* _SAM3SD8_RTT_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/smc.h b/zephyr/ports/asf/sam3sd8/include/component/smc.h new file mode 100644 index 0000000..ec004ec --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/smc.h @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SMC_COMPONENT_ +#define _SAM3SD8_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC Mode Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protect Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protect Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC Mode Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +#define SMC_OCMS_CS0SE (0x1u << 16) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS1SE (0x1u << 17) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS2SE (0x1u << 18) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +#define SMC_OCMS_CS3SE (0x1u << 19) /**< \brief (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protect Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protect KEY */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protect Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protect Enable */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAM3SD8_SMC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/spi.h b/zephyr/ports/asf/sam3sd8/include/component/spi.h new file mode 100644 index 0000000..26b9b05 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/spi.h @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SPI_COMPONENT_ +#define _SAM3SD8_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Control Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[5]; + __IO uint32_t SPI_RPR; /**< \brief (Spi Offset: 0x100) Receive Pointer Register */ + __IO uint32_t SPI_RCR; /**< \brief (Spi Offset: 0x104) Receive Counter Register */ + __IO uint32_t SPI_TPR; /**< \brief (Spi Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t SPI_TCR; /**< \brief (Spi Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t SPI_RNPR; /**< \brief (Spi Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t SPI_RNCR; /**< \brief (Spi Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t SPI_TNPR; /**< \brief (Spi Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t SPI_TNCR; /**< \brief (Spi Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t SPI_PTCR; /**< \brief (Spi Offset: 0x120) Transfer Control Register */ + __I uint32_t SPI_PTSR; /**< \brief (Spi Offset: 0x124) Transfer Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status */ +#define SPI_SR_ENDRX (0x1u << 4) /**< \brief (SPI_SR) End of RX buffer */ +#define SPI_SR_ENDTX (0x1u << 5) /**< \brief (SPI_SR) End of TX buffer */ +#define SPI_SR_RXBUFF (0x1u << 6) /**< \brief (SPI_SR) RX Buffer Full */ +#define SPI_SR_TXBUFE (0x1u << 7) /**< \brief (SPI_SR) TX Buffer Empty */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave Mode Only) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_ENDRX (0x1u << 4) /**< \brief (SPI_IER) End of Receive Buffer Interrupt Enable */ +#define SPI_IER_ENDTX (0x1u << 5) /**< \brief (SPI_IER) End of Transmit Buffer Interrupt Enable */ +#define SPI_IER_RXBUFF (0x1u << 6) /**< \brief (SPI_IER) Receive Buffer Full Interrupt Enable */ +#define SPI_IER_TXBUFE (0x1u << 7) /**< \brief (SPI_IER) Transmit Buffer Empty Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_ENDRX (0x1u << 4) /**< \brief (SPI_IDR) End of Receive Buffer Interrupt Disable */ +#define SPI_IDR_ENDTX (0x1u << 5) /**< \brief (SPI_IDR) End of Transmit Buffer Interrupt Disable */ +#define SPI_IDR_RXBUFF (0x1u << 6) /**< \brief (SPI_IDR) Receive Buffer Full Interrupt Disable */ +#define SPI_IDR_TXBUFE (0x1u << 7) /**< \brief (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_ENDRX (0x1u << 4) /**< \brief (SPI_IMR) End of Receive Buffer Interrupt Mask */ +#define SPI_IMR_ENDTX (0x1u << 5) /**< \brief (SPI_IMR) End of Transmit Buffer Interrupt Mask */ +#define SPI_IMR_RXBUFF (0x1u << 6) /**< \brief (SPI_IMR) Receive Buffer Full Interrupt Mask */ +#define SPI_IMR_TXBUFE (0x1u << 7) /**< \brief (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Baud Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key Password */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ +/* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ +#define SPI_RPR_RXPTR_Pos 0 +#define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /**< \brief (SPI_RPR) Receive Pointer Register */ +#define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos))) +/* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ +#define SPI_RCR_RXCTR_Pos 0 +#define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /**< \brief (SPI_RCR) Receive Counter Register */ +#define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos))) +/* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ +#define SPI_TPR_TXPTR_Pos 0 +#define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /**< \brief (SPI_TPR) Transmit Counter Register */ +#define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos))) +/* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ +#define SPI_TCR_TXCTR_Pos 0 +#define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /**< \brief (SPI_TCR) Transmit Counter Register */ +#define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos))) +/* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ +#define SPI_RNPR_RXNPTR_Pos 0 +#define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /**< \brief (SPI_RNPR) Receive Next Pointer */ +#define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos))) +/* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ +#define SPI_RNCR_RXNCTR_Pos 0 +#define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /**< \brief (SPI_RNCR) Receive Next Counter */ +#define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos))) +/* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SPI_TNPR_TXNPTR_Pos 0 +#define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /**< \brief (SPI_TNPR) Transmit Next Pointer */ +#define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos))) +/* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SPI_TNCR_TXNCTR_Pos 0 +#define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /**< \brief (SPI_TNCR) Transmit Counter Next */ +#define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos))) +/* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ +#define SPI_PTCR_RXTEN (0x1u << 0) /**< \brief (SPI_PTCR) Receiver Transfer Enable */ +#define SPI_PTCR_RXTDIS (0x1u << 1) /**< \brief (SPI_PTCR) Receiver Transfer Disable */ +#define SPI_PTCR_TXTEN (0x1u << 8) /**< \brief (SPI_PTCR) Transmitter Transfer Enable */ +#define SPI_PTCR_TXTDIS (0x1u << 9) /**< \brief (SPI_PTCR) Transmitter Transfer Disable */ +/* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ +#define SPI_PTSR_RXTEN (0x1u << 0) /**< \brief (SPI_PTSR) Receiver Transfer Enable */ +#define SPI_PTSR_TXTEN (0x1u << 8) /**< \brief (SPI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_SPI_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/ssc.h b/zephyr/ports/asf/sam3sd8/include/component/ssc.h new file mode 100644 index 0000000..bb54b07 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/ssc.h @@ -0,0 +1,337 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SSC_COMPONENT_ +#define _SAM3SD8_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protect Status Register */ + __I uint32_t Reserved4[5]; + __IO uint32_t SSC_RPR; /**< \brief (Ssc Offset: 0x100) Receive Pointer Register */ + __IO uint32_t SSC_RCR; /**< \brief (Ssc Offset: 0x104) Receive Counter Register */ + __IO uint32_t SSC_TPR; /**< \brief (Ssc Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t SSC_TCR; /**< \brief (Ssc Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t SSC_RNPR; /**< \brief (Ssc Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t SSC_RNCR; /**< \brief (Ssc Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t SSC_TNPR; /**< \brief (Ssc Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t SSC_TNCR; /**< \brief (Ssc Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t SSC_PTCR; /**< \brief (Ssc Offset: 0x120) Transfer Control Register */ + __I uint32_t SSC_PTSR; /**< \brief (Ssc Offset: 0x124) Transfer Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_RCMR) Continuous Receive Clock */ +#define SSC_RCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock only during data transfers */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_TCMR) TK Clock signal */ +#define SSC_TCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_TCMR) RK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Receive Clock */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG_NONE (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_CONTINUOUS (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_TRANSFER (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_TCMR) Compare 0 */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_ENDTX (0x1u << 2) /**< \brief (SSC_SR) End of Transmission */ +#define SSC_SR_TXBUFE (0x1u << 3) /**< \brief (SSC_SR) Transmit Buffer Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_ENDRX (0x1u << 6) /**< \brief (SSC_SR) End of Reception */ +#define SSC_SR_RXBUFF (0x1u << 7) /**< \brief (SSC_SR) Receive Buffer Full */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_ENDTX (0x1u << 2) /**< \brief (SSC_IER) End of Transmission Interrupt Enable */ +#define SSC_IER_TXBUFE (0x1u << 3) /**< \brief (SSC_IER) Transmit Buffer Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_ENDRX (0x1u << 6) /**< \brief (SSC_IER) End of Reception Interrupt Enable */ +#define SSC_IER_RXBUFF (0x1u << 7) /**< \brief (SSC_IER) Receive Buffer Full Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_ENDTX (0x1u << 2) /**< \brief (SSC_IDR) End of Transmission Interrupt Disable */ +#define SSC_IDR_TXBUFE (0x1u << 3) /**< \brief (SSC_IDR) Transmit Buffer Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_ENDRX (0x1u << 6) /**< \brief (SSC_IDR) End of Reception Interrupt Disable */ +#define SSC_IDR_RXBUFF (0x1u << 7) /**< \brief (SSC_IDR) Receive Buffer Full Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_ENDTX (0x1u << 2) /**< \brief (SSC_IMR) End of Transmission Interrupt Mask */ +#define SSC_IMR_TXBUFE (0x1u << 3) /**< \brief (SSC_IMR) Transmit Buffer Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_ENDRX (0x1u << 6) /**< \brief (SSC_IMR) End of Reception Interrupt Mask */ +#define SSC_IMR_RXBUFF (0x1u << 7) /**< \brief (SSC_IMR) Receive Buffer Full Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protect Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protect Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protect KEY */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protect Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protect Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ +/* -------- SSC_RPR : (SSC Offset: 0x100) Receive Pointer Register -------- */ +#define SSC_RPR_RXPTR_Pos 0 +#define SSC_RPR_RXPTR_Msk (0xffffffffu << SSC_RPR_RXPTR_Pos) /**< \brief (SSC_RPR) Receive Pointer Register */ +#define SSC_RPR_RXPTR(value) ((SSC_RPR_RXPTR_Msk & ((value) << SSC_RPR_RXPTR_Pos))) +/* -------- SSC_RCR : (SSC Offset: 0x104) Receive Counter Register -------- */ +#define SSC_RCR_RXCTR_Pos 0 +#define SSC_RCR_RXCTR_Msk (0xffffu << SSC_RCR_RXCTR_Pos) /**< \brief (SSC_RCR) Receive Counter Register */ +#define SSC_RCR_RXCTR(value) ((SSC_RCR_RXCTR_Msk & ((value) << SSC_RCR_RXCTR_Pos))) +/* -------- SSC_TPR : (SSC Offset: 0x108) Transmit Pointer Register -------- */ +#define SSC_TPR_TXPTR_Pos 0 +#define SSC_TPR_TXPTR_Msk (0xffffffffu << SSC_TPR_TXPTR_Pos) /**< \brief (SSC_TPR) Transmit Counter Register */ +#define SSC_TPR_TXPTR(value) ((SSC_TPR_TXPTR_Msk & ((value) << SSC_TPR_TXPTR_Pos))) +/* -------- SSC_TCR : (SSC Offset: 0x10C) Transmit Counter Register -------- */ +#define SSC_TCR_TXCTR_Pos 0 +#define SSC_TCR_TXCTR_Msk (0xffffu << SSC_TCR_TXCTR_Pos) /**< \brief (SSC_TCR) Transmit Counter Register */ +#define SSC_TCR_TXCTR(value) ((SSC_TCR_TXCTR_Msk & ((value) << SSC_TCR_TXCTR_Pos))) +/* -------- SSC_RNPR : (SSC Offset: 0x110) Receive Next Pointer Register -------- */ +#define SSC_RNPR_RXNPTR_Pos 0 +#define SSC_RNPR_RXNPTR_Msk (0xffffffffu << SSC_RNPR_RXNPTR_Pos) /**< \brief (SSC_RNPR) Receive Next Pointer */ +#define SSC_RNPR_RXNPTR(value) ((SSC_RNPR_RXNPTR_Msk & ((value) << SSC_RNPR_RXNPTR_Pos))) +/* -------- SSC_RNCR : (SSC Offset: 0x114) Receive Next Counter Register -------- */ +#define SSC_RNCR_RXNCTR_Pos 0 +#define SSC_RNCR_RXNCTR_Msk (0xffffu << SSC_RNCR_RXNCTR_Pos) /**< \brief (SSC_RNCR) Receive Next Counter */ +#define SSC_RNCR_RXNCTR(value) ((SSC_RNCR_RXNCTR_Msk & ((value) << SSC_RNCR_RXNCTR_Pos))) +/* -------- SSC_TNPR : (SSC Offset: 0x118) Transmit Next Pointer Register -------- */ +#define SSC_TNPR_TXNPTR_Pos 0 +#define SSC_TNPR_TXNPTR_Msk (0xffffffffu << SSC_TNPR_TXNPTR_Pos) /**< \brief (SSC_TNPR) Transmit Next Pointer */ +#define SSC_TNPR_TXNPTR(value) ((SSC_TNPR_TXNPTR_Msk & ((value) << SSC_TNPR_TXNPTR_Pos))) +/* -------- SSC_TNCR : (SSC Offset: 0x11C) Transmit Next Counter Register -------- */ +#define SSC_TNCR_TXNCTR_Pos 0 +#define SSC_TNCR_TXNCTR_Msk (0xffffu << SSC_TNCR_TXNCTR_Pos) /**< \brief (SSC_TNCR) Transmit Counter Next */ +#define SSC_TNCR_TXNCTR(value) ((SSC_TNCR_TXNCTR_Msk & ((value) << SSC_TNCR_TXNCTR_Pos))) +/* -------- SSC_PTCR : (SSC Offset: 0x120) Transfer Control Register -------- */ +#define SSC_PTCR_RXTEN (0x1u << 0) /**< \brief (SSC_PTCR) Receiver Transfer Enable */ +#define SSC_PTCR_RXTDIS (0x1u << 1) /**< \brief (SSC_PTCR) Receiver Transfer Disable */ +#define SSC_PTCR_TXTEN (0x1u << 8) /**< \brief (SSC_PTCR) Transmitter Transfer Enable */ +#define SSC_PTCR_TXTDIS (0x1u << 9) /**< \brief (SSC_PTCR) Transmitter Transfer Disable */ +/* -------- SSC_PTSR : (SSC Offset: 0x124) Transfer Status Register -------- */ +#define SSC_PTSR_RXTEN (0x1u << 0) /**< \brief (SSC_PTSR) Receiver Transfer Enable */ +#define SSC_PTSR_TXTEN (0x1u << 8) /**< \brief (SSC_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_SSC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/supc.h b/zephyr/ports/asf/sam3sd8/include/component/supc.h new file mode 100644 index 0000000..d2b45c3 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/supc.h @@ -0,0 +1,322 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SUPC_COMPONENT_ +#define _SAM3SD8_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake Up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake Up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) no effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) if KEY is correct, switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH_1_9V (0x0u << 0) /**< \brief (SUPC_SMMR) 1.9 V */ +#define SUPC_SMMR_SMTH_2_0V (0x1u << 0) /**< \brief (SUPC_SMMR) 2.0 V */ +#define SUPC_SMMR_SMTH_2_1V (0x2u << 0) /**< \brief (SUPC_SMMR) 2.1 V */ +#define SUPC_SMMR_SMTH_2_2V (0x3u << 0) /**< \brief (SUPC_SMMR) 2.2 V */ +#define SUPC_SMMR_SMTH_2_3V (0x4u << 0) /**< \brief (SUPC_SMMR) 2.3 V */ +#define SUPC_SMMR_SMTH_2_4V (0x5u << 0) /**< \brief (SUPC_SMMR) 2.4 V */ +#define SUPC_SMMR_SMTH_2_5V (0x6u << 0) /**< \brief (SUPC_SMMR) 2.5 V */ +#define SUPC_SMMR_SMTH_2_6V (0x7u << 0) /**< \brief (SUPC_SMMR) 2.6 V */ +#define SUPC_SMMR_SMTH_2_7V (0x8u << 0) /**< \brief (SUPC_SMMR) 2.7 V */ +#define SUPC_SMMR_SMTH_2_8V (0x9u << 0) /**< \brief (SUPC_SMMR) 2.8 V */ +#define SUPC_SMMR_SMTH_2_9V (0xAu << 0) /**< \brief (SUPC_SMMR) 2.9 V */ +#define SUPC_SMMR_SMTH_3_0V (0xBu << 0) /**< \brief (SUPC_SMMR) 3.0 V */ +#define SUPC_SMMR_SMTH_3_1V (0xCu << 0) /**< \brief (SUPC_SMMR) 3.1 V */ +#define SUPC_SMMR_SMTH_3_2V (0xDu << 0) /**< \brief (SUPC_SMMR) 3.2 V */ +#define SUPC_SMMR_SMTH_3_3V (0xEu << 0) /**< \brief (SUPC_SMMR) 3.3 V */ +#define SUPC_SMMR_SMTH_3_4V (0xFu << 0) /**< \brief (SUPC_SMMR) 3.4 V */ +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) the SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) the core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) the core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Voltage Regulator is not used */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator is used */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) no effect. Clock selection depends on XTALSEL value. */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) the 32-KHz XTAL oscillator is selected and is put in bypass mode. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake Up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection has no wake up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) the supply monitor detection forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real Time Timer Wake Up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) the RTT alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real Time Clock Wake Up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal has no wake up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) the RTC alarm signal forces the wake up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is not connected with low power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) the WKUP0 input pin is connected with low power debouncer and can force a core wake up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low power Debouncer ENable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) the WKUP1input pin is not connected with low power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) the WKUP1 input pin is connected with low power debouncer and can force a core wake up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) a low power debounce event does not create an immediate clear on first half GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake Up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SCLK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SCLK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SCLK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SCLK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SCLK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low Power DeBounCer Period */ +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low power debouncer. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT0 (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 2 RTCOUT0 periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT0 (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 3 RTCOUT0 periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT0 (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 4 RTCOUT0 periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT0 (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 5 RTCOUT0 periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT0 (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 6 RTCOUT0 periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT0 (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 7 RTCOUT0 periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT0 (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in its active state for at least 8 RTCOUT0 periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake Up Input Enable 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake Up Input Enable 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake Up Input Enable 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake Up Input Enable 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake Up Input Enable 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake Up Input Enable 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake Up Input Enable 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake Up Input Enable 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake Up Input Enable 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake Up Input Enable 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake Up Input Enable 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake Up Input Enable 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake Up Input Enable 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake Up Input Enable 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN14 (0x1u << 14) /**< \brief (SUPC_WUIR) Wake Up Input Enable 14 */ +#define SUPC_WUIR_WKUPEN14_DISABLE (0x0u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN14_ENABLE (0x1u << 14) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPEN15 (0x1u << 15) /**< \brief (SUPC_WUIR) Wake Up Input Enable 15 */ +#define SUPC_WUIR_WKUPEN15_DISABLE (0x0u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input has no wake up effect. */ +#define SUPC_WUIR_WKUPEN15_ENABLE (0x1u << 15) /**< \brief (SUPC_WUIR) the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake Up Input Type 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake Up Input Type 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake Up Input Type 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake Up Input Type 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake Up Input Type 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake Up Input Type 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake Up Input Type 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake Up Input Type 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake Up Input Type 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake Up Input Type 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake Up Input Type 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake Up Input Type 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake Up Input Type 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake Up Input Type 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14 (0x1u << 30) /**< \brief (SUPC_WUIR) Wake Up Input Type 14 */ +#define SUPC_WUIR_WKUPT14_LOW (0x0u << 30) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT14_HIGH (0x1u << 30) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15 (0x1u << 31) /**< \brief (SUPC_WUIR) Wake Up Input Type 15 */ +#define SUPC_WUIR_WKUPT15_LOW (0x0u << 31) /**< \brief (SUPC_WUIR) a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. */ +#define SUPC_WUIR_WKUPT15_HIGH (0x1u << 31) /**< \brief (SUPC_WUIR) a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake Up Status */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake Up Status */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) no core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) no supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) at least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) the supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP0 */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low Power Debouncer Wake Up Status on WKUP1 */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUP Input Status 0 */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUP Input Status 1 */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUP Input Status 2 */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUP Input Status 3 */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUP Input Status 4 */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUP Input Status 5 */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUP Input Status 6 */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUP Input Status 7 */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUP Input Status 8 */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUP Input Status 9 */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUP Input Status 10 */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUP Input Status 11 */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUP Input Status 12 */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUP Input Status 13 */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14 (0x1u << 30) /**< \brief (SUPC_SR) WKUP Input Status 14 */ +#define SUPC_SR_WKUPIS14_DIS (0x0u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS14_EN (0x1u << 30) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15 (0x1u << 31) /**< \brief (SUPC_SR) WKUP Input Status 15 */ +#define SUPC_SR_WKUPIS15_DIS (0x0u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. */ +#define SUPC_SR_WKUPIS15_EN (0x1u << 31) /**< \brief (SUPC_SR) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. */ + +/*@}*/ + + +#endif /* _SAM3SD8_SUPC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/tc.h b/zephyr/ports/asf/sam3sd8/include/component/tc.h new file mode 100644 index 0000000..82978c9 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/tc.h @@ -0,0 +1,303 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_TC_COMPONENT_ +#define _SAM3SD8_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t Reserved1[1]; + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t Reserved2[4]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protect Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: TCLK1 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: TCLK2 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: TCLK3 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: TCLK4 */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: TCLK5 */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) DOWN Count */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA2 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder ENabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) POSition ENabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) SPEED ENabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding TRANSparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) EDGe on PHA count mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) INVerted phA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) INVerted phB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) INVerted InDeX */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) SWAP PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) InDeX pin is PHB pin */ +#define TC_BMR_FILTER (0x1u << 19) /**< \brief (TC_BMR) */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) MAXimum FILTer */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) InDeX */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) DIRection CHanGe */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature ERRor */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) InDeX */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) DIRection CHanGe */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature ERRor */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) InDeX */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) DIRection CHanGe */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature ERRor */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) InDeX */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) DIRection CHanGe */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature ERRor */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) DIRection */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) ENable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) ENable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protect Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protect KEY */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) + +/*@}*/ + + +#endif /* _SAM3SD8_TC_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/twi.h b/zephyr/ports/asf/sam3sd8/include/component/twi.h new file mode 100644 index 0000000..7a27f62 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/twi.h @@ -0,0 +1,217 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_TWI_COMPONENT_ +#define _SAM3SD8_TWI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_TWI Two-wire Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twi hardware registers */ +typedef struct { + __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + __I uint32_t Reserved2[50]; + __IO uint32_t TWI_RPR; /**< \brief (Twi Offset: 0x100) Receive Pointer Register */ + __IO uint32_t TWI_RCR; /**< \brief (Twi Offset: 0x104) Receive Counter Register */ + __IO uint32_t TWI_TPR; /**< \brief (Twi Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t TWI_TCR; /**< \brief (Twi Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t TWI_RNPR; /**< \brief (Twi Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t TWI_RNCR; /**< \brief (Twi Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t TWI_TNPR; /**< \brief (Twi Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t TWI_TNCR; /**< \brief (Twi Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t TWI_PTCR; /**< \brief (Twi Offset: 0x120) Transfer Control Register */ + __I uint32_t TWI_PTSR; /**< \brief (Twi Offset: 0x124) Transfer Status Register */ +} Twi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +#define TWI_SR_ENDRX (0x1u << 12) /**< \brief (TWI_SR) End of RX buffer */ +#define TWI_SR_ENDTX (0x1u << 13) /**< \brief (TWI_SR) End of TX buffer */ +#define TWI_SR_RXBUFF (0x1u << 14) /**< \brief (TWI_SR) RX Buffer Full */ +#define TWI_SR_TXBUFE (0x1u << 15) /**< \brief (TWI_SR) TX Buffer Empty */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +#define TWI_IER_ENDRX (0x1u << 12) /**< \brief (TWI_IER) End of Receive Buffer Interrupt Enable */ +#define TWI_IER_ENDTX (0x1u << 13) /**< \brief (TWI_IER) End of Transmit Buffer Interrupt Enable */ +#define TWI_IER_RXBUFF (0x1u << 14) /**< \brief (TWI_IER) Receive Buffer Full Interrupt Enable */ +#define TWI_IER_TXBUFE (0x1u << 15) /**< \brief (TWI_IER) Transmit Buffer Empty Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +#define TWI_IDR_ENDRX (0x1u << 12) /**< \brief (TWI_IDR) End of Receive Buffer Interrupt Disable */ +#define TWI_IDR_ENDTX (0x1u << 13) /**< \brief (TWI_IDR) End of Transmit Buffer Interrupt Disable */ +#define TWI_IDR_RXBUFF (0x1u << 14) /**< \brief (TWI_IDR) Receive Buffer Full Interrupt Disable */ +#define TWI_IDR_TXBUFE (0x1u << 15) /**< \brief (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +#define TWI_IMR_ENDRX (0x1u << 12) /**< \brief (TWI_IMR) End of Receive Buffer Interrupt Mask */ +#define TWI_IMR_ENDTX (0x1u << 13) /**< \brief (TWI_IMR) End of Transmit Buffer Interrupt Mask */ +#define TWI_IMR_RXBUFF (0x1u << 14) /**< \brief (TWI_IMR) Receive Buffer Full Interrupt Mask */ +#define TWI_IMR_TXBUFE (0x1u << 15) /**< \brief (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) +/* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ +#define TWI_RPR_RXPTR_Pos 0 +#define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /**< \brief (TWI_RPR) Receive Pointer Register */ +#define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) +/* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ +#define TWI_RCR_RXCTR_Pos 0 +#define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /**< \brief (TWI_RCR) Receive Counter Register */ +#define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) +/* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ +#define TWI_TPR_TXPTR_Pos 0 +#define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /**< \brief (TWI_TPR) Transmit Counter Register */ +#define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) +/* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ +#define TWI_TCR_TXCTR_Pos 0 +#define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /**< \brief (TWI_TCR) Transmit Counter Register */ +#define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) +/* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ +#define TWI_RNPR_RXNPTR_Pos 0 +#define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /**< \brief (TWI_RNPR) Receive Next Pointer */ +#define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) +/* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ +#define TWI_RNCR_RXNCTR_Pos 0 +#define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /**< \brief (TWI_RNCR) Receive Next Counter */ +#define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) +/* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ +#define TWI_TNPR_TXNPTR_Pos 0 +#define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /**< \brief (TWI_TNPR) Transmit Next Pointer */ +#define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) +/* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ +#define TWI_TNCR_TXNCTR_Pos 0 +#define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /**< \brief (TWI_TNCR) Transmit Counter Next */ +#define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) +/* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ +#define TWI_PTCR_RXTEN (0x1u << 0) /**< \brief (TWI_PTCR) Receiver Transfer Enable */ +#define TWI_PTCR_RXTDIS (0x1u << 1) /**< \brief (TWI_PTCR) Receiver Transfer Disable */ +#define TWI_PTCR_TXTEN (0x1u << 8) /**< \brief (TWI_PTCR) Transmitter Transfer Enable */ +#define TWI_PTCR_TXTDIS (0x1u << 9) /**< \brief (TWI_PTCR) Transmitter Transfer Disable */ +/* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ +#define TWI_PTSR_RXTEN (0x1u << 0) /**< \brief (TWI_PTSR) Receiver Transfer Enable */ +#define TWI_PTSR_TXTEN (0x1u << 8) /**< \brief (TWI_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_TWI_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/uart.h b/zephyr/ports/asf/sam3sd8/include/component/uart.h new file mode 100644 index 0000000..68f93a7 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/uart.h @@ -0,0 +1,185 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_UART_COMPONENT_ +#define _SAM3SD8_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ + __IO uint32_t UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ + __IO uint32_t UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ + __I uint32_t UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status Bits */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal Mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic Echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local Loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote Loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ +#define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ +#define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ +#define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ +#define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ +#define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ +#define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */ +#define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ +#define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ +#define UART_RPR_RXPTR_Pos 0 +#define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */ +#define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) +/* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ +#define UART_RCR_RXCTR_Pos 0 +#define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */ +#define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) +/* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ +#define UART_TPR_TXPTR_Pos 0 +#define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */ +#define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) +/* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ +#define UART_TCR_TXCTR_Pos 0 +#define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */ +#define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) +/* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ +#define UART_RNPR_RXNPTR_Pos 0 +#define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */ +#define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) +/* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ +#define UART_RNCR_RXNCTR_Pos 0 +#define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */ +#define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) +/* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define UART_TNPR_TXNPTR_Pos 0 +#define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */ +#define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) +/* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define UART_TNCR_TXNCTR_Pos 0 +#define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */ +#define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) +/* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ +#define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ +#define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ +#define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ +#define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ +/* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ +#define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ +#define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_UART_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/udp.h b/zephyr/ports/asf/sam3sd8/include/component/udp.h new file mode 100644 index 0000000..e54b215 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/udp.h @@ -0,0 +1,185 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_UDP_COMPONENT_ +#define _SAM3SD8_UDP_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Device Port */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_UDP USB Device Port */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Udp hardware registers */ +typedef struct { + __I uint32_t UDP_FRM_NUM; /**< \brief (Udp Offset: 0x000) Frame Number Register */ + __IO uint32_t UDP_GLB_STAT; /**< \brief (Udp Offset: 0x004) Global State Register */ + __IO uint32_t UDP_FADDR; /**< \brief (Udp Offset: 0x008) Function Address Register */ + __I uint32_t Reserved1[1]; + __O uint32_t UDP_IER; /**< \brief (Udp Offset: 0x010) Interrupt Enable Register */ + __O uint32_t UDP_IDR; /**< \brief (Udp Offset: 0x014) Interrupt Disable Register */ + __I uint32_t UDP_IMR; /**< \brief (Udp Offset: 0x018) Interrupt Mask Register */ + __I uint32_t UDP_ISR; /**< \brief (Udp Offset: 0x01C) Interrupt Status Register */ + __O uint32_t UDP_ICR; /**< \brief (Udp Offset: 0x020) Interrupt Clear Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t UDP_RST_EP; /**< \brief (Udp Offset: 0x028) Reset Endpoint Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t UDP_CSR[8]; /**< \brief (Udp Offset: 0x030) Endpoint Control and Status Register */ + __IO uint32_t UDP_FDR[8]; /**< \brief (Udp Offset: 0x050) Endpoint FIFO Data Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t UDP_TXVC; /**< \brief (Udp Offset: 0x074) Transceiver Control Register */ +} Udp; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UDP_FRM_NUM : (UDP Offset: 0x000) Frame Number Register -------- */ +#define UDP_FRM_NUM_FRM_NUM_Pos 0 +#define UDP_FRM_NUM_FRM_NUM_Msk (0x7ffu << UDP_FRM_NUM_FRM_NUM_Pos) /**< \brief (UDP_FRM_NUM) Frame Number as Defined in the Packet Field Formats */ +#define UDP_FRM_NUM_FRM_ERR (0x1u << 16) /**< \brief (UDP_FRM_NUM) Frame Error */ +#define UDP_FRM_NUM_FRM_OK (0x1u << 17) /**< \brief (UDP_FRM_NUM) Frame OK */ +/* -------- UDP_GLB_STAT : (UDP Offset: 0x004) Global State Register -------- */ +#define UDP_GLB_STAT_FADDEN (0x1u << 0) /**< \brief (UDP_GLB_STAT) Function Address Enable */ +#define UDP_GLB_STAT_CONFG (0x1u << 1) /**< \brief (UDP_GLB_STAT) Configured */ +#define UDP_GLB_STAT_ESR (0x1u << 2) /**< \brief (UDP_GLB_STAT) Enable Send Resume */ +#define UDP_GLB_STAT_RSMINPR (0x1u << 3) /**< \brief (UDP_GLB_STAT) */ +#define UDP_GLB_STAT_RMWUPE (0x1u << 4) /**< \brief (UDP_GLB_STAT) Remote Wake Up Enable */ +/* -------- UDP_FADDR : (UDP Offset: 0x008) Function Address Register -------- */ +#define UDP_FADDR_FADD_Pos 0 +#define UDP_FADDR_FADD_Msk (0x7fu << UDP_FADDR_FADD_Pos) /**< \brief (UDP_FADDR) Function Address Value */ +#define UDP_FADDR_FADD(value) ((UDP_FADDR_FADD_Msk & ((value) << UDP_FADDR_FADD_Pos))) +#define UDP_FADDR_FEN (0x1u << 8) /**< \brief (UDP_FADDR) Function Enable */ +/* -------- UDP_IER : (UDP Offset: 0x010) Interrupt Enable Register -------- */ +#define UDP_IER_EP0INT (0x1u << 0) /**< \brief (UDP_IER) Enable Endpoint 0 Interrupt */ +#define UDP_IER_EP1INT (0x1u << 1) /**< \brief (UDP_IER) Enable Endpoint 1 Interrupt */ +#define UDP_IER_EP2INT (0x1u << 2) /**< \brief (UDP_IER) Enable Endpoint 2Interrupt */ +#define UDP_IER_EP3INT (0x1u << 3) /**< \brief (UDP_IER) Enable Endpoint 3 Interrupt */ +#define UDP_IER_EP4INT (0x1u << 4) /**< \brief (UDP_IER) Enable Endpoint 4 Interrupt */ +#define UDP_IER_EP5INT (0x1u << 5) /**< \brief (UDP_IER) Enable Endpoint 5 Interrupt */ +#define UDP_IER_EP6INT (0x1u << 6) /**< \brief (UDP_IER) Enable Endpoint 6 Interrupt */ +#define UDP_IER_EP7INT (0x1u << 7) /**< \brief (UDP_IER) Enable Endpoint 7 Interrupt */ +#define UDP_IER_RXSUSP (0x1u << 8) /**< \brief (UDP_IER) Enable UDP Suspend Interrupt */ +#define UDP_IER_RXRSM (0x1u << 9) /**< \brief (UDP_IER) Enable UDP Resume Interrupt */ +#define UDP_IER_EXTRSM (0x1u << 10) /**< \brief (UDP_IER) */ +#define UDP_IER_SOFINT (0x1u << 11) /**< \brief (UDP_IER) Enable Start Of Frame Interrupt */ +#define UDP_IER_WAKEUP (0x1u << 13) /**< \brief (UDP_IER) Enable UDP bus Wakeup Interrupt */ +/* -------- UDP_IDR : (UDP Offset: 0x014) Interrupt Disable Register -------- */ +#define UDP_IDR_EP0INT (0x1u << 0) /**< \brief (UDP_IDR) Disable Endpoint 0 Interrupt */ +#define UDP_IDR_EP1INT (0x1u << 1) /**< \brief (UDP_IDR) Disable Endpoint 1 Interrupt */ +#define UDP_IDR_EP2INT (0x1u << 2) /**< \brief (UDP_IDR) Disable Endpoint 2 Interrupt */ +#define UDP_IDR_EP3INT (0x1u << 3) /**< \brief (UDP_IDR) Disable Endpoint 3 Interrupt */ +#define UDP_IDR_EP4INT (0x1u << 4) /**< \brief (UDP_IDR) Disable Endpoint 4 Interrupt */ +#define UDP_IDR_EP5INT (0x1u << 5) /**< \brief (UDP_IDR) Disable Endpoint 5 Interrupt */ +#define UDP_IDR_EP6INT (0x1u << 6) /**< \brief (UDP_IDR) Disable Endpoint 6 Interrupt */ +#define UDP_IDR_EP7INT (0x1u << 7) /**< \brief (UDP_IDR) Disable Endpoint 7 Interrupt */ +#define UDP_IDR_RXSUSP (0x1u << 8) /**< \brief (UDP_IDR) Disable UDP Suspend Interrupt */ +#define UDP_IDR_RXRSM (0x1u << 9) /**< \brief (UDP_IDR) Disable UDP Resume Interrupt */ +#define UDP_IDR_EXTRSM (0x1u << 10) /**< \brief (UDP_IDR) */ +#define UDP_IDR_SOFINT (0x1u << 11) /**< \brief (UDP_IDR) Disable Start Of Frame Interrupt */ +#define UDP_IDR_WAKEUP (0x1u << 13) /**< \brief (UDP_IDR) Disable USB Bus Interrupt */ +/* -------- UDP_IMR : (UDP Offset: 0x018) Interrupt Mask Register -------- */ +#define UDP_IMR_EP0INT (0x1u << 0) /**< \brief (UDP_IMR) Mask Endpoint 0 Interrupt */ +#define UDP_IMR_EP1INT (0x1u << 1) /**< \brief (UDP_IMR) Mask Endpoint 1 Interrupt */ +#define UDP_IMR_EP2INT (0x1u << 2) /**< \brief (UDP_IMR) Mask Endpoint 2 Interrupt */ +#define UDP_IMR_EP3INT (0x1u << 3) /**< \brief (UDP_IMR) Mask Endpoint 3 Interrupt */ +#define UDP_IMR_EP4INT (0x1u << 4) /**< \brief (UDP_IMR) Mask Endpoint 4 Interrupt */ +#define UDP_IMR_EP5INT (0x1u << 5) /**< \brief (UDP_IMR) Mask Endpoint 5 Interrupt */ +#define UDP_IMR_EP6INT (0x1u << 6) /**< \brief (UDP_IMR) Mask Endpoint 6 Interrupt */ +#define UDP_IMR_EP7INT (0x1u << 7) /**< \brief (UDP_IMR) Mask Endpoint 7 Interrupt */ +#define UDP_IMR_RXSUSP (0x1u << 8) /**< \brief (UDP_IMR) Mask UDP Suspend Interrupt */ +#define UDP_IMR_RXRSM (0x1u << 9) /**< \brief (UDP_IMR) Mask UDP Resume Interrupt. */ +#define UDP_IMR_EXTRSM (0x1u << 10) /**< \brief (UDP_IMR) */ +#define UDP_IMR_SOFINT (0x1u << 11) /**< \brief (UDP_IMR) Mask Start Of Frame Interrupt */ +#define UDP_IMR_BIT12 (0x1u << 12) /**< \brief (UDP_IMR) UDP_IMR Bit 12 */ +#define UDP_IMR_WAKEUP (0x1u << 13) /**< \brief (UDP_IMR) USB Bus WAKEUP Interrupt */ +/* -------- UDP_ISR : (UDP Offset: 0x01C) Interrupt Status Register -------- */ +#define UDP_ISR_EP0INT (0x1u << 0) /**< \brief (UDP_ISR) Endpoint 0 Interrupt Status */ +#define UDP_ISR_EP1INT (0x1u << 1) /**< \brief (UDP_ISR) Endpoint 1 Interrupt Status */ +#define UDP_ISR_EP2INT (0x1u << 2) /**< \brief (UDP_ISR) Endpoint 2 Interrupt Status */ +#define UDP_ISR_EP3INT (0x1u << 3) /**< \brief (UDP_ISR) Endpoint 3 Interrupt Status */ +#define UDP_ISR_EP4INT (0x1u << 4) /**< \brief (UDP_ISR) Endpoint 4 Interrupt Status */ +#define UDP_ISR_EP5INT (0x1u << 5) /**< \brief (UDP_ISR) Endpoint 5 Interrupt Status */ +#define UDP_ISR_EP6INT (0x1u << 6) /**< \brief (UDP_ISR) Endpoint 6 Interrupt Status */ +#define UDP_ISR_EP7INT (0x1u << 7) /**< \brief (UDP_ISR) Endpoint 7Interrupt Status */ +#define UDP_ISR_RXSUSP (0x1u << 8) /**< \brief (UDP_ISR) UDP Suspend Interrupt Status */ +#define UDP_ISR_RXRSM (0x1u << 9) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +#define UDP_ISR_EXTRSM (0x1u << 10) /**< \brief (UDP_ISR) */ +#define UDP_ISR_SOFINT (0x1u << 11) /**< \brief (UDP_ISR) Start of Frame Interrupt Status */ +#define UDP_ISR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ISR) End of BUS Reset Interrupt Status */ +#define UDP_ISR_WAKEUP (0x1u << 13) /**< \brief (UDP_ISR) UDP Resume Interrupt Status */ +/* -------- UDP_ICR : (UDP Offset: 0x020) Interrupt Clear Register -------- */ +#define UDP_ICR_RXSUSP (0x1u << 8) /**< \brief (UDP_ICR) Clear UDP Suspend Interrupt */ +#define UDP_ICR_RXRSM (0x1u << 9) /**< \brief (UDP_ICR) Clear UDP Resume Interrupt */ +#define UDP_ICR_EXTRSM (0x1u << 10) /**< \brief (UDP_ICR) */ +#define UDP_ICR_SOFINT (0x1u << 11) /**< \brief (UDP_ICR) Clear Start Of Frame Interrupt */ +#define UDP_ICR_ENDBUSRES (0x1u << 12) /**< \brief (UDP_ICR) Clear End of Bus Reset Interrupt */ +#define UDP_ICR_WAKEUP (0x1u << 13) /**< \brief (UDP_ICR) Clear Wakeup Interrupt */ +/* -------- UDP_RST_EP : (UDP Offset: 0x028) Reset Endpoint Register -------- */ +#define UDP_RST_EP_EP0 (0x1u << 0) /**< \brief (UDP_RST_EP) Reset Endpoint 0 */ +#define UDP_RST_EP_EP1 (0x1u << 1) /**< \brief (UDP_RST_EP) Reset Endpoint 1 */ +#define UDP_RST_EP_EP2 (0x1u << 2) /**< \brief (UDP_RST_EP) Reset Endpoint 2 */ +#define UDP_RST_EP_EP3 (0x1u << 3) /**< \brief (UDP_RST_EP) Reset Endpoint 3 */ +#define UDP_RST_EP_EP4 (0x1u << 4) /**< \brief (UDP_RST_EP) Reset Endpoint 4 */ +#define UDP_RST_EP_EP5 (0x1u << 5) /**< \brief (UDP_RST_EP) Reset Endpoint 5 */ +#define UDP_RST_EP_EP6 (0x1u << 6) /**< \brief (UDP_RST_EP) Reset Endpoint 6 */ +#define UDP_RST_EP_EP7 (0x1u << 7) /**< \brief (UDP_RST_EP) Reset Endpoint 7 */ +/* -------- UDP_CSR[8] : (UDP Offset: 0x030) Endpoint Control and Status Register -------- */ +#define UDP_CSR_TXCOMP (0x1u << 0) /**< \brief (UDP_CSR[8]) Generates an IN Packet with Data Previously Written in the DPR */ +#define UDP_CSR_RX_DATA_BK0 (0x1u << 1) /**< \brief (UDP_CSR[8]) Receive Data Bank 0 */ +#define UDP_CSR_RXSETUP (0x1u << 2) /**< \brief (UDP_CSR[8]) Received Setup */ +#define UDP_CSR_STALLSENT (0x1u << 3) /**< \brief (UDP_CSR[8]) Stall Sent */ +#define UDP_CSR_TXPKTRDY (0x1u << 4) /**< \brief (UDP_CSR[8]) Transmit Packet Ready */ +#define UDP_CSR_FORCESTALL (0x1u << 5) /**< \brief (UDP_CSR[8]) Force Stall (used by Control, Bulk and Isochronous Endpoints) */ +#define UDP_CSR_RX_DATA_BK1 (0x1u << 6) /**< \brief (UDP_CSR[8]) Receive Data Bank 1 (only used by endpoints with ping-pong attributes) */ +#define UDP_CSR_DIR (0x1u << 7) /**< \brief (UDP_CSR[8]) Transfer Direction (only available for control endpoints) */ +#define UDP_CSR_EPTYPE_Pos 8 +#define UDP_CSR_EPTYPE_Msk (0x7u << UDP_CSR_EPTYPE_Pos) /**< \brief (UDP_CSR[8]) Endpoint Type */ +#define UDP_CSR_EPTYPE_CTRL (0x0u << 8) /**< \brief (UDP_CSR[8]) Control */ +#define UDP_CSR_EPTYPE_ISO_OUT (0x1u << 8) /**< \brief (UDP_CSR[8]) Isochronous OUT */ +#define UDP_CSR_EPTYPE_BULK_OUT (0x2u << 8) /**< \brief (UDP_CSR[8]) Bulk OUT */ +#define UDP_CSR_EPTYPE_INT_OUT (0x3u << 8) /**< \brief (UDP_CSR[8]) Interrupt OUT */ +#define UDP_CSR_EPTYPE_ISO_IN (0x5u << 8) /**< \brief (UDP_CSR[8]) Isochronous IN */ +#define UDP_CSR_EPTYPE_BULK_IN (0x6u << 8) /**< \brief (UDP_CSR[8]) Bulk IN */ +#define UDP_CSR_EPTYPE_INT_IN (0x7u << 8) /**< \brief (UDP_CSR[8]) Interrupt IN */ +#define UDP_CSR_DTGLE (0x1u << 11) /**< \brief (UDP_CSR[8]) Data Toggle */ +#define UDP_CSR_EPEDS (0x1u << 15) /**< \brief (UDP_CSR[8]) Endpoint Enable Disable */ +#define UDP_CSR_RXBYTECNT_Pos 16 +#define UDP_CSR_RXBYTECNT_Msk (0x7ffu << UDP_CSR_RXBYTECNT_Pos) /**< \brief (UDP_CSR[8]) Number of Bytes Available in the FIFO */ +#define UDP_CSR_RXBYTECNT(value) ((UDP_CSR_RXBYTECNT_Msk & ((value) << UDP_CSR_RXBYTECNT_Pos))) +#define UDP_CSR_ISOERROR (0x1u << 3) /**< \brief (UDP_CSR[8]) A CRC error has been detected in an isochronous transfer */ +/* -------- UDP_FDR[8] : (UDP Offset: 0x050) Endpoint FIFO Data Register -------- */ +#define UDP_FDR_FIFO_DATA_Pos 0 +#define UDP_FDR_FIFO_DATA_Msk (0xffu << UDP_FDR_FIFO_DATA_Pos) /**< \brief (UDP_FDR[8]) FIFO Data Value */ +#define UDP_FDR_FIFO_DATA(value) ((UDP_FDR_FIFO_DATA_Msk & ((value) << UDP_FDR_FIFO_DATA_Pos))) +/* -------- UDP_TXVC : (UDP Offset: 0x074) Transceiver Control Register -------- */ +#define UDP_TXVC_TXVDIS (0x1u << 8) /**< \brief (UDP_TXVC) Transceiver Disable */ +#define UDP_TXVC_PUON (0x1u << 9) /**< \brief (UDP_TXVC) Pull-up On */ + +/*@}*/ + + +#endif /* _SAM3SD8_UDP_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/usart.h b/zephyr/ports/asf/sam3sd8/include/component/usart.h new file mode 100644 index 0000000..7a61713 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/usart.h @@ -0,0 +1,362 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_USART_COMPONENT_ +#define _SAM3SD8_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receiver Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmitter Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t US_IF; /**< \brief (Usart Offset: 0x004C) IrDA Filter Register */ + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Encoder Decoder Register */ + __I uint32_t Reserved3[36]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0xE4) Write Protect Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0xE8) Write Protect Status Register */ + __I uint32_t Reserved4[4]; + __I uint32_t US_VERSION; /**< \brief (Usart Offset: 0xFC) Version Register */ + __IO uint32_t US_RPR; /**< \brief (Usart Offset: 0x100) Receive Pointer Register */ + __IO uint32_t US_RCR; /**< \brief (Usart Offset: 0x104) Receive Counter Register */ + __IO uint32_t US_TPR; /**< \brief (Usart Offset: 0x108) Transmit Pointer Register */ + __IO uint32_t US_TCR; /**< \brief (Usart Offset: 0x10C) Transmit Counter Register */ + __IO uint32_t US_RNPR; /**< \brief (Usart Offset: 0x110) Receive Next Pointer Register */ + __IO uint32_t US_RNCR; /**< \brief (Usart Offset: 0x114) Receive Next Counter Register */ + __IO uint32_t US_TNPR; /**< \brief (Usart Offset: 0x118) Transmit Next Pointer Register */ + __IO uint32_t US_TNCR; /**< \brief (Usart Offset: 0x11C) Transmit Next Counter Register */ + __O uint32_t US_PTCR; /**< \brief (Usart Offset: 0x120) Transfer Control Register */ + __I uint32_t US_PTSR; /**< \brief (Usart Offset: 0x124) Transfer Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Start Time-out */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Rearm Time-out */ +#define US_CR_DTREN (0x1u << 16) /**< \brief (US_CR) Data Terminal Ready Enable */ +#define US_CR_DTRDIS (0x1u << 17) /**< \brief (US_CR) Data Terminal Ready Disable */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Enable */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Disable */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_MODEM (0x3u << 0) /**< \brief (US_MR) Modem */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_IRDA (0x8u << 0) /**< \brief (US_MR) IrDA */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI Master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Master Clock MCK is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Internal Clock Divided MCK/DIV (DIV=8) is selected */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial Clock SLK is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length. */ +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal Mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MSBF (0x1u << 16) /**< \brief (US_MR) Bit Order */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_INACK (0x1u << 20) /**< \brief (US_MR) Inhibit Non Acknowledge */ +#define US_MR_DSNACK (0x1u << 21) /**< \brief (US_MR) Disable Successive NACK */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_INVDATA (0x1u << 23) /**< \brief (US_MR) INverted Data */ +#define US_MR_MAX_ITERATION_Pos 24 +#define US_MR_MAX_ITERATION_Msk (0x7u << US_MR_MAX_ITERATION_Pos) /**< \brief (US_MR) Maximum Number of Automatic Iteration */ +#define US_MR_MAX_ITERATION(value) ((US_MR_MAX_ITERATION_Msk & ((value) << US_MR_MAX_ITERATION_Pos))) +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Infrared Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_ENDRX (0x1u << 3) /**< \brief (US_IER) End of Receive Transfer Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_ENDTX (0x1u << 4) /**< \brief (US_IER) End of Transmit Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_ITER (0x1u << 10) /**< \brief (US_IER) Max number of Repetitions Reached Interrupt Enable */ +#define US_IER_TXBUFE (0x1u << 11) /**< \brief (US_IER) Buffer Empty Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_RXBUFF (0x1u << 12) /**< \brief (US_IER) Buffer Full Interrupt Enable (available in all USART modes of operation) */ +#define US_IER_NACK (0x1u << 13) /**< \brief (US_IER) Non AcknowledgeInterrupt Enable */ +#define US_IER_RIIC (0x1u << 16) /**< \brief (US_IER) Ring Indicator Input Change Enable */ +#define US_IER_DSRIC (0x1u << 17) /**< \brief (US_IER) Data Set Ready Input Change Enable */ +#define US_IER_DCDIC (0x1u << 18) /**< \brief (US_IER) Data Carrier Detect Input Change Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_ENDRX (0x1u << 3) /**< \brief (US_IDR) End of Receive Transfer Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_ENDTX (0x1u << 4) /**< \brief (US_IDR) End of Transmit Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_ITER (0x1u << 10) /**< \brief (US_IDR) Max number of Repetitions Reached Interrupt Disable */ +#define US_IDR_TXBUFE (0x1u << 11) /**< \brief (US_IDR) Buffer Empty Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_RXBUFF (0x1u << 12) /**< \brief (US_IDR) Buffer Full Interrupt Disable (available in all USART modes of operation) */ +#define US_IDR_NACK (0x1u << 13) /**< \brief (US_IDR) Non AcknowledgeInterrupt Disable */ +#define US_IDR_RIIC (0x1u << 16) /**< \brief (US_IDR) Ring Indicator Input Change Disable */ +#define US_IDR_DSRIC (0x1u << 17) /**< \brief (US_IDR) Data Set Ready Input Change Disable */ +#define US_IDR_DCDIC (0x1u << 18) /**< \brief (US_IDR) Data Carrier Detect Input Change Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_ENDRX (0x1u << 3) /**< \brief (US_IMR) End of Receive Transfer Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_ENDTX (0x1u << 4) /**< \brief (US_IMR) End of Transmit Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_ITER (0x1u << 10) /**< \brief (US_IMR) Max number of Repetitions Reached Interrupt Mask */ +#define US_IMR_TXBUFE (0x1u << 11) /**< \brief (US_IMR) Buffer Empty Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_RXBUFF (0x1u << 12) /**< \brief (US_IMR) Buffer Full Interrupt Mask (available in all USART modes of operation) */ +#define US_IMR_NACK (0x1u << 13) /**< \brief (US_IMR) Non AcknowledgeInterrupt Mask */ +#define US_IMR_RIIC (0x1u << 16) /**< \brief (US_IMR) Ring Indicator Input Change Mask */ +#define US_IMR_DSRIC (0x1u << 17) /**< \brief (US_IMR) Data Set Ready Input Change Mask */ +#define US_IMR_DCDIC (0x1u << 18) /**< \brief (US_IMR) Data Carrier Detect Input Change Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break */ +#define US_CSR_ENDRX (0x1u << 3) /**< \brief (US_CSR) End of Receiver Transfer */ +#define US_CSR_ENDTX (0x1u << 4) /**< \brief (US_CSR) End of Transmitter Transfer */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty */ +#define US_CSR_ITER (0x1u << 10) /**< \brief (US_CSR) Max number of Repetitions Reached */ +#define US_CSR_TXBUFE (0x1u << 11) /**< \brief (US_CSR) Transmission Buffer Empty */ +#define US_CSR_RXBUFF (0x1u << 12) /**< \brief (US_CSR) Reception Buffer Full */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ +#define US_CSR_RIIC (0x1u << 16) /**< \brief (US_CSR) Ring Indicator Input Change Flag */ +#define US_CSR_DSRIC (0x1u << 17) /**< \brief (US_CSR) Data Set Ready Input Change Flag */ +#define US_CSR_DCDIC (0x1u << 18) /**< \brief (US_CSR) Data Carrier Detect Input Change Flag */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag */ +#define US_CSR_RI (0x1u << 20) /**< \brief (US_CSR) Image of RI Input */ +#define US_CSR_DSR (0x1u << 21) /**< \brief (US_CSR) Image of DSR Input */ +#define US_CSR_DCD (0x1u << 22) /**< \brief (US_CSR) Image of DCD Input */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error */ +/* -------- US_RHR : (USART Offset: 0x0018) Receiver Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmitter Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0xffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +/* -------- US_FIDI : (USART Offset: 0x0040) FI DI Ratio Register -------- */ +#define US_FIDI_FI_DI_RATIO_Pos 0 +#define US_FIDI_FI_DI_RATIO_Msk (0x7ffu << US_FIDI_FI_DI_RATIO_Pos) /**< \brief (US_FIDI) FI Over DI Ratio Value */ +#define US_FIDI_FI_DI_RATIO(value) ((US_FIDI_FI_DI_RATIO_Msk & ((value) << US_FIDI_FI_DI_RATIO_Pos))) +/* -------- US_NER : (USART Offset: 0x0044) Number of Errors Register -------- */ +#define US_NER_NB_ERRORS_Pos 0 +#define US_NER_NB_ERRORS_Msk (0xffu << US_NER_NB_ERRORS_Pos) /**< \brief (US_NER) Number of Errors */ +/* -------- US_IF : (USART Offset: 0x004C) IrDA Filter Register -------- */ +#define US_IF_IRDA_FILTER_Pos 0 +#define US_IF_IRDA_FILTER_Msk (0xffu << US_IF_IRDA_FILTER_Pos) /**< \brief (US_IF) IrDA Filter */ +#define US_IF_IRDA_FILTER(value) ((US_IF_IRDA_FILTER_Msk & ((value) << US_IF_IRDA_FILTER_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Encoder Decoder Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift compensation */ +/* -------- US_WPMR : (USART Offset: 0xE4) Write Protect Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protect Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protect KEY */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +/* -------- US_WPSR : (USART Offset: 0xE8) Write Protect Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protect Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protect Violation Source */ +/* -------- US_VERSION : (USART Offset: 0xFC) Version Register -------- */ +#define US_VERSION_VERSION_Pos 0 +#define US_VERSION_VERSION_Msk (0xfffu << US_VERSION_VERSION_Pos) /**< \brief (US_VERSION) Harware Module Version */ +#define US_VERSION_MFN_Pos 16 +#define US_VERSION_MFN_Msk (0x7u << US_VERSION_MFN_Pos) /**< \brief (US_VERSION) Metal Fix Number */ +/* -------- US_RPR : (USART Offset: 0x100) Receive Pointer Register -------- */ +#define US_RPR_RXPTR_Pos 0 +#define US_RPR_RXPTR_Msk (0xffffffffu << US_RPR_RXPTR_Pos) /**< \brief (US_RPR) Receive Pointer Register */ +#define US_RPR_RXPTR(value) ((US_RPR_RXPTR_Msk & ((value) << US_RPR_RXPTR_Pos))) +/* -------- US_RCR : (USART Offset: 0x104) Receive Counter Register -------- */ +#define US_RCR_RXCTR_Pos 0 +#define US_RCR_RXCTR_Msk (0xffffu << US_RCR_RXCTR_Pos) /**< \brief (US_RCR) Receive Counter Register */ +#define US_RCR_RXCTR(value) ((US_RCR_RXCTR_Msk & ((value) << US_RCR_RXCTR_Pos))) +/* -------- US_TPR : (USART Offset: 0x108) Transmit Pointer Register -------- */ +#define US_TPR_TXPTR_Pos 0 +#define US_TPR_TXPTR_Msk (0xffffffffu << US_TPR_TXPTR_Pos) /**< \brief (US_TPR) Transmit Counter Register */ +#define US_TPR_TXPTR(value) ((US_TPR_TXPTR_Msk & ((value) << US_TPR_TXPTR_Pos))) +/* -------- US_TCR : (USART Offset: 0x10C) Transmit Counter Register -------- */ +#define US_TCR_TXCTR_Pos 0 +#define US_TCR_TXCTR_Msk (0xffffu << US_TCR_TXCTR_Pos) /**< \brief (US_TCR) Transmit Counter Register */ +#define US_TCR_TXCTR(value) ((US_TCR_TXCTR_Msk & ((value) << US_TCR_TXCTR_Pos))) +/* -------- US_RNPR : (USART Offset: 0x110) Receive Next Pointer Register -------- */ +#define US_RNPR_RXNPTR_Pos 0 +#define US_RNPR_RXNPTR_Msk (0xffffffffu << US_RNPR_RXNPTR_Pos) /**< \brief (US_RNPR) Receive Next Pointer */ +#define US_RNPR_RXNPTR(value) ((US_RNPR_RXNPTR_Msk & ((value) << US_RNPR_RXNPTR_Pos))) +/* -------- US_RNCR : (USART Offset: 0x114) Receive Next Counter Register -------- */ +#define US_RNCR_RXNCTR_Pos 0 +#define US_RNCR_RXNCTR_Msk (0xffffu << US_RNCR_RXNCTR_Pos) /**< \brief (US_RNCR) Receive Next Counter */ +#define US_RNCR_RXNCTR(value) ((US_RNCR_RXNCTR_Msk & ((value) << US_RNCR_RXNCTR_Pos))) +/* -------- US_TNPR : (USART Offset: 0x118) Transmit Next Pointer Register -------- */ +#define US_TNPR_TXNPTR_Pos 0 +#define US_TNPR_TXNPTR_Msk (0xffffffffu << US_TNPR_TXNPTR_Pos) /**< \brief (US_TNPR) Transmit Next Pointer */ +#define US_TNPR_TXNPTR(value) ((US_TNPR_TXNPTR_Msk & ((value) << US_TNPR_TXNPTR_Pos))) +/* -------- US_TNCR : (USART Offset: 0x11C) Transmit Next Counter Register -------- */ +#define US_TNCR_TXNCTR_Pos 0 +#define US_TNCR_TXNCTR_Msk (0xffffu << US_TNCR_TXNCTR_Pos) /**< \brief (US_TNCR) Transmit Counter Next */ +#define US_TNCR_TXNCTR(value) ((US_TNCR_TXNCTR_Msk & ((value) << US_TNCR_TXNCTR_Pos))) +/* -------- US_PTCR : (USART Offset: 0x120) Transfer Control Register -------- */ +#define US_PTCR_RXTEN (0x1u << 0) /**< \brief (US_PTCR) Receiver Transfer Enable */ +#define US_PTCR_RXTDIS (0x1u << 1) /**< \brief (US_PTCR) Receiver Transfer Disable */ +#define US_PTCR_TXTEN (0x1u << 8) /**< \brief (US_PTCR) Transmitter Transfer Enable */ +#define US_PTCR_TXTDIS (0x1u << 9) /**< \brief (US_PTCR) Transmitter Transfer Disable */ +/* -------- US_PTSR : (USART Offset: 0x124) Transfer Status Register -------- */ +#define US_PTSR_RXTEN (0x1u << 0) /**< \brief (US_PTSR) Receiver Transfer Enable */ +#define US_PTSR_TXTEN (0x1u << 8) /**< \brief (US_PTSR) Transmitter Transfer Enable */ + +/*@}*/ + + +#endif /* _SAM3SD8_USART_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/component/wdt.h b/zephyr/ports/asf/sam3sd8/include/component/wdt.h new file mode 100644 index 0000000..2af9bdd --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/component/wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_WDT_COMPONENT_ +#define _SAM3SD8_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAM3SD8_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDRPROC (0x1u << 14) /**< \brief (WDT_MR) Watchdog Reset Processor */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error */ + +/*@}*/ + + +#endif /* _SAM3SD8_WDT_COMPONENT_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/acc.h b/zephyr/ports/asf/sam3sd8/include/instance/acc.h new file mode 100644 index 0000000..581f8c1 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/acc.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_ACC_INSTANCE_ +#define _SAM3SD8_ACC_INSTANCE_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ACC_CR (0x40040000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (0x40040004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (0x40040030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (0x40040094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ + #define REG_ACC_WPSR (0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +#else + #define REG_ACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (ACC) Write Protect Mode Register */ + #define REG_ACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (ACC) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_ACC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/adc.h b/zephyr/ports/asf/sam3sd8/include/instance/adc.h new file mode 100644 index 0000000..26c6ab5 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/adc.h @@ -0,0 +1,92 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_ADC_INSTANCE_ +#define _SAM3SD8_ADC_INSTANCE_ + +/* ========== Register definition for ADC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ADC_CR (0x40038000U) /**< \brief (ADC) Control Register */ + #define REG_ADC_MR (0x40038004U) /**< \brief (ADC) Mode Register */ + #define REG_ADC_SEQR1 (0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ + #define REG_ADC_SEQR2 (0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */ + #define REG_ADC_CHER (0x40038010U) /**< \brief (ADC) Channel Enable Register */ + #define REG_ADC_CHDR (0x40038014U) /**< \brief (ADC) Channel Disable Register */ + #define REG_ADC_CHSR (0x40038018U) /**< \brief (ADC) Channel Status Register */ + #define REG_ADC_LCDR (0x40038020U) /**< \brief (ADC) Last Converted Data Register */ + #define REG_ADC_IER (0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ + #define REG_ADC_IDR (0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ + #define REG_ADC_IMR (0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ + #define REG_ADC_ISR (0x40038030U) /**< \brief (ADC) Interrupt Status Register */ + #define REG_ADC_OVER (0x4003803CU) /**< \brief (ADC) Overrun Status Register */ + #define REG_ADC_EMR (0x40038040U) /**< \brief (ADC) Extended Mode Register */ + #define REG_ADC_CWR (0x40038044U) /**< \brief (ADC) Compare Window Register */ + #define REG_ADC_CGR (0x40038048U) /**< \brief (ADC) Channel Gain Register */ + #define REG_ADC_COR (0x4003804CU) /**< \brief (ADC) Channel Offset Register */ + #define REG_ADC_CDR (0x40038050U) /**< \brief (ADC) Channel Data Register */ + #define REG_ADC_ACR (0x40038094U) /**< \brief (ADC) Analog Control Register */ + #define REG_ADC_WPMR (0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ + #define REG_ADC_WPSR (0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ + #define REG_ADC_RPR (0x40038100U) /**< \brief (ADC) Receive Pointer Register */ + #define REG_ADC_RCR (0x40038104U) /**< \brief (ADC) Receive Counter Register */ + #define REG_ADC_RNPR (0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ + #define REG_ADC_RNCR (0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ + #define REG_ADC_PTCR (0x40038120U) /**< \brief (ADC) Transfer Control Register */ + #define REG_ADC_PTSR (0x40038124U) /**< \brief (ADC) Transfer Status Register */ +#else + #define REG_ADC_CR (*(__O uint32_t*)0x40038000U) /**< \brief (ADC) Control Register */ + #define REG_ADC_MR (*(__IO uint32_t*)0x40038004U) /**< \brief (ADC) Mode Register */ + #define REG_ADC_SEQR1 (*(__IO uint32_t*)0x40038008U) /**< \brief (ADC) Channel Sequence Register 1 */ + #define REG_ADC_SEQR2 (*(__IO uint32_t*)0x4003800CU) /**< \brief (ADC) Channel Sequence Register 2 */ + #define REG_ADC_CHER (*(__O uint32_t*)0x40038010U) /**< \brief (ADC) Channel Enable Register */ + #define REG_ADC_CHDR (*(__O uint32_t*)0x40038014U) /**< \brief (ADC) Channel Disable Register */ + #define REG_ADC_CHSR (*(__I uint32_t*)0x40038018U) /**< \brief (ADC) Channel Status Register */ + #define REG_ADC_LCDR (*(__I uint32_t*)0x40038020U) /**< \brief (ADC) Last Converted Data Register */ + #define REG_ADC_IER (*(__O uint32_t*)0x40038024U) /**< \brief (ADC) Interrupt Enable Register */ + #define REG_ADC_IDR (*(__O uint32_t*)0x40038028U) /**< \brief (ADC) Interrupt Disable Register */ + #define REG_ADC_IMR (*(__I uint32_t*)0x4003802CU) /**< \brief (ADC) Interrupt Mask Register */ + #define REG_ADC_ISR (*(__I uint32_t*)0x40038030U) /**< \brief (ADC) Interrupt Status Register */ + #define REG_ADC_OVER (*(__I uint32_t*)0x4003803CU) /**< \brief (ADC) Overrun Status Register */ + #define REG_ADC_EMR (*(__IO uint32_t*)0x40038040U) /**< \brief (ADC) Extended Mode Register */ + #define REG_ADC_CWR (*(__IO uint32_t*)0x40038044U) /**< \brief (ADC) Compare Window Register */ + #define REG_ADC_CGR (*(__IO uint32_t*)0x40038048U) /**< \brief (ADC) Channel Gain Register */ + #define REG_ADC_COR (*(__IO uint32_t*)0x4003804CU) /**< \brief (ADC) Channel Offset Register */ + #define REG_ADC_CDR (*(__I uint32_t*)0x40038050U) /**< \brief (ADC) Channel Data Register */ + #define REG_ADC_ACR (*(__IO uint32_t*)0x40038094U) /**< \brief (ADC) Analog Control Register */ + #define REG_ADC_WPMR (*(__IO uint32_t*)0x400380E4U) /**< \brief (ADC) Write Protect Mode Register */ + #define REG_ADC_WPSR (*(__I uint32_t*)0x400380E8U) /**< \brief (ADC) Write Protect Status Register */ + #define REG_ADC_RPR (*(__IO uint32_t*)0x40038100U) /**< \brief (ADC) Receive Pointer Register */ + #define REG_ADC_RCR (*(__IO uint32_t*)0x40038104U) /**< \brief (ADC) Receive Counter Register */ + #define REG_ADC_RNPR (*(__IO uint32_t*)0x40038110U) /**< \brief (ADC) Receive Next Pointer Register */ + #define REG_ADC_RNCR (*(__IO uint32_t*)0x40038114U) /**< \brief (ADC) Receive Next Counter Register */ + #define REG_ADC_PTCR (*(__O uint32_t*)0x40038120U) /**< \brief (ADC) Transfer Control Register */ + #define REG_ADC_PTSR (*(__I uint32_t*)0x40038124U) /**< \brief (ADC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_ADC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/chipid.h b/zephyr/ports/asf/sam3sd8/include/instance/chipid.h new file mode 100644 index 0000000..6d813a8 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/chipid.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_CHIPID_INSTANCE_ +#define _SAM3SD8_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else + #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_CHIPID_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/crccu.h b/zephyr/ports/asf/sam3sd8/include/instance/crccu.h new file mode 100644 index 0000000..4e76524 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/crccu.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_CRCCU_INSTANCE_ +#define _SAM3SD8_CRCCU_INSTANCE_ + +/* ========== Register definition for CRCCU peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ + #define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ + #define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ + #define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ + #define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ + #define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ + #define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ + #define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ + #define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ + #define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ + #define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ + #define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ + #define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ + #define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ + #define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +#else + #define REG_CRCCU_DSCR (*(__IO uint32_t*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */ + #define REG_CRCCU_DMA_EN (*(__O uint32_t*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */ + #define REG_CRCCU_DMA_DIS (*(__O uint32_t*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */ + #define REG_CRCCU_DMA_SR (*(__I uint32_t*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */ + #define REG_CRCCU_DMA_IER (*(__O uint32_t*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */ + #define REG_CRCCU_DMA_IDR (*(__O uint32_t*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */ + #define REG_CRCCU_DMA_IMR (*(__I uint32_t*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */ + #define REG_CRCCU_DMA_ISR (*(__I uint32_t*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */ + #define REG_CRCCU_CR (*(__O uint32_t*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */ + #define REG_CRCCU_MR (*(__IO uint32_t*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */ + #define REG_CRCCU_SR (*(__I uint32_t*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */ + #define REG_CRCCU_IER (*(__O uint32_t*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */ + #define REG_CRCCU_IDR (*(__O uint32_t*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */ + #define REG_CRCCU_IMR (*(__I uint32_t*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */ + #define REG_CRCCU_ISR (*(__I uint32_t*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_CRCCU_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/dacc.h b/zephyr/ports/asf/sam3sd8/include/instance/dacc.h new file mode 100644 index 0000000..be4c598 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/dacc.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_DACC_INSTANCE_ +#define _SAM3SD8_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_DACC_CR (0x4003C000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (0x4003C004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_CHER (0x4003C010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (0x4003C014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (0x4003C018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (0x4003C020U) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (0x4003C094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ + #define REG_DACC_WPSR (0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ + #define REG_DACC_TPR (0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ + #define REG_DACC_TCR (0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ + #define REG_DACC_TNPR (0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ + #define REG_DACC_TNCR (0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ + #define REG_DACC_PTCR (0x4003C120U) /**< \brief (DACC) Transfer Control Register */ + #define REG_DACC_PTSR (0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +#else + #define REG_DACC_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_CHER (*(__O uint32_t*)0x4003C010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (*(__O uint32_t*)0x4003C014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (*(__I uint32_t*)0x4003C018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (*(__O uint32_t*)0x4003C020U) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (DACC) Write Protect Mode register */ + #define REG_DACC_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (DACC) Write Protect Status register */ + #define REG_DACC_TPR (*(__IO uint32_t*)0x4003C108U) /**< \brief (DACC) Transmit Pointer Register */ + #define REG_DACC_TCR (*(__IO uint32_t*)0x4003C10CU) /**< \brief (DACC) Transmit Counter Register */ + #define REG_DACC_TNPR (*(__IO uint32_t*)0x4003C118U) /**< \brief (DACC) Transmit Next Pointer Register */ + #define REG_DACC_TNCR (*(__IO uint32_t*)0x4003C11CU) /**< \brief (DACC) Transmit Next Counter Register */ + #define REG_DACC_PTCR (*(__O uint32_t*)0x4003C120U) /**< \brief (DACC) Transfer Control Register */ + #define REG_DACC_PTSR (*(__I uint32_t*)0x4003C124U) /**< \brief (DACC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_DACC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/efc.h b/zephyr/ports/asf/sam3sd8/include/instance/efc.h new file mode 100644 index 0000000..b508aa9 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/efc.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_EFC_INSTANCE_ +#define _SAM3SD8_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +#else + #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (*(__O uint32_t*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (*(__I uint32_t*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (*(__I uint32_t*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_EFC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/gpbr.h b/zephyr/ports/asf/sam3sd8/include/instance/gpbr.h new file mode 100644 index 0000000..e5ff700 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/gpbr.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_GPBR_INSTANCE_ +#define _SAM3SD8_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GPBR_GPBR (0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ +#else + #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1490U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_GPBR_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/hsmci.h b/zephyr/ports/asf/sam3sd8/include/instance/hsmci.h new file mode 100644 index 0000000..73dff65 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/hsmci.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_HSMCI_INSTANCE_ +#define _SAM3SD8_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_RPR (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ + #define REG_HSMCI_RCR (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ + #define REG_HSMCI_TPR (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ + #define REG_HSMCI_TCR (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ + #define REG_HSMCI_RNPR (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ + #define REG_HSMCI_RNCR (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ + #define REG_HSMCI_TNPR (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ + #define REG_HSMCI_TNCR (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ + #define REG_HSMCI_PTCR (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ + #define REG_HSMCI_PTSR (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ + #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else + #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_RPR (*(__IO uint32_t*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */ + #define REG_HSMCI_RCR (*(__IO uint32_t*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */ + #define REG_HSMCI_TPR (*(__IO uint32_t*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */ + #define REG_HSMCI_TCR (*(__IO uint32_t*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */ + #define REG_HSMCI_RNPR (*(__IO uint32_t*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */ + #define REG_HSMCI_RNCR (*(__IO uint32_t*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */ + #define REG_HSMCI_TNPR (*(__IO uint32_t*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */ + #define REG_HSMCI_TNCR (*(__IO uint32_t*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */ + #define REG_HSMCI_PTCR (*(__O uint32_t*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */ + #define REG_HSMCI_PTSR (*(__I uint32_t*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */ + #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_HSMCI_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/matrix.h b/zephyr/ports/asf/sam3sd8/include/instance/matrix.h new file mode 100644 index 0000000..1e55cb0 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/matrix.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_MATRIX_INSTANCE_ +#define _SAM3SD8_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_CCFG_SYSIO (0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ + #define REG_CCFG_SMCNFCS (0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ + #define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ + #define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#else + #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x400E0314U) /**< \brief (MATRIX) System I/O Configuration register */ + #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x400E031CU) /**< \brief (MATRIX) SMC Chip Select NAND Flash Assignment Register */ + #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */ + #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_MATRIX_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/pioa.h b/zephyr/ports/asf/sam3sd8/include/instance/pioa.h new file mode 100644 index 0000000..3de219c --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/pioa.h @@ -0,0 +1,156 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PIOA_INSTANCE_ +#define _SAM3SD8_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ + #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ + #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ + #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ + #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ + #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ + #define REG_PIOA_RPR (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */ + #define REG_PIOA_RCR (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */ + #define REG_PIOA_RNPR (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */ + #define REG_PIOA_RNCR (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */ + #define REG_PIOA_PTCR (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */ + #define REG_PIOA_PTSR (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */ +#else + #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */ + #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */ + #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */ + #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */ + #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */ + #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ + #define REG_PIOA_RPR (*(__IO uint32_t*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */ + #define REG_PIOA_RCR (*(__IO uint32_t*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */ + #define REG_PIOA_RNPR (*(__IO uint32_t*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */ + #define REG_PIOA_RNCR (*(__IO uint32_t*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */ + #define REG_PIOA_PTCR (*(__O uint32_t*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */ + #define REG_PIOA_PTSR (*(__I uint32_t*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_PIOA_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/piob.h b/zephyr/ports/asf/sam3sd8/include/instance/piob.h new file mode 100644 index 0000000..a6ad2ff --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/piob.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PIOB_INSTANCE_ +#define _SAM3SD8_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ + #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ + #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ + #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ + #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ + #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */ + #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */ + #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */ + #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */ + #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */ + #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_PIOB_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/pioc.h b/zephyr/ports/asf/sam3sd8/include/instance/pioc.h new file mode 100644 index 0000000..6f5e19a --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/pioc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PIOC_INSTANCE_ +#define _SAM3SD8_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ + #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ + #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ + #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ + #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ + #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */ + #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */ + #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */ + #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */ + #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */ + #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_PIOC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/pmc.h b/zephyr/ports/asf/sam3sd8/include/instance/pmc.h new file mode 100644 index 0000000..424860b --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/pmc.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PMC_INSTANCE_ +#define _SAM3SD8_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */ + #define REG_CKGR_PLLBR (0x400E042CU) /**< \brief (PMC) PLLB Register */ + #define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ + #define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ + #define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +#else + #define REG_PMC_SCER (*(__O uint32_t*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0428U) /**< \brief (PMC) PLLA Register */ + #define REG_CKGR_PLLBR (*(__IO uint32_t*)0x400E042CU) /**< \brief (PMC) PLLB Register */ + #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0430U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (*(__IO uint32_t*)0x400E0438U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (*(__O uint32_t*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (*(__O uint32_t*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (*(__I uint32_t*)0x400E0468U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (*(__I uint32_t*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */ + #define REG_PMC_WPSR (*(__I uint32_t*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */ + #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_PMC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/pwm.h b/zephyr/ports/asf/sam3sd8/include/instance/pwm.h new file mode 100644 index 0000000..66c227d --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/pwm.h @@ -0,0 +1,238 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_PWM_INSTANCE_ +#define _SAM3SD8_PWM_INSTANCE_ + +/* ========== Register definition for PWM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM_CLK (0x40020000U) /**< \brief (PWM) PWM Clock Register */ + #define REG_PWM_ENA (0x40020004U) /**< \brief (PWM) PWM Enable Register */ + #define REG_PWM_DIS (0x40020008U) /**< \brief (PWM) PWM Disable Register */ + #define REG_PWM_SR (0x4002000CU) /**< \brief (PWM) PWM Status Register */ + #define REG_PWM_IER1 (0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ + #define REG_PWM_IDR1 (0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ + #define REG_PWM_IMR1 (0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ + #define REG_PWM_ISR1 (0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ + #define REG_PWM_SCM (0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ + #define REG_PWM_SCUC (0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ + #define REG_PWM_SCUP (0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ + #define REG_PWM_SCUPUPD (0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ + #define REG_PWM_IER2 (0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ + #define REG_PWM_IDR2 (0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ + #define REG_PWM_IMR2 (0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ + #define REG_PWM_ISR2 (0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ + #define REG_PWM_OOV (0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ + #define REG_PWM_OS (0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ + #define REG_PWM_OSS (0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ + #define REG_PWM_OSC (0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ + #define REG_PWM_OSSUPD (0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ + #define REG_PWM_OSCUPD (0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ + #define REG_PWM_FMR (0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ + #define REG_PWM_FSR (0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ + #define REG_PWM_FCR (0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ + #define REG_PWM_FPV (0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ + #define REG_PWM_FPE (0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ + #define REG_PWM_ELMR (0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ + #define REG_PWM_WPCR (0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ + #define REG_PWM_WPSR (0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ + #define REG_PWM_TPR (0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ + #define REG_PWM_TCR (0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ + #define REG_PWM_TNPR (0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ + #define REG_PWM_TNCR (0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ + #define REG_PWM_PTCR (0x40020120U) /**< \brief (PWM) Transfer Control Register */ + #define REG_PWM_PTSR (0x40020124U) /**< \brief (PWM) Transfer Status Register */ + #define REG_PWM_CMPV0 (0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ + #define REG_PWM_CMPVUPD0 (0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ + #define REG_PWM_CMPM0 (0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ + #define REG_PWM_CMPMUPD0 (0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ + #define REG_PWM_CMPV1 (0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ + #define REG_PWM_CMPVUPD1 (0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ + #define REG_PWM_CMPM1 (0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ + #define REG_PWM_CMPMUPD1 (0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ + #define REG_PWM_CMPV2 (0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ + #define REG_PWM_CMPVUPD2 (0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ + #define REG_PWM_CMPM2 (0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ + #define REG_PWM_CMPMUPD2 (0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ + #define REG_PWM_CMPV3 (0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ + #define REG_PWM_CMPVUPD3 (0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ + #define REG_PWM_CMPM3 (0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ + #define REG_PWM_CMPMUPD3 (0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ + #define REG_PWM_CMPV4 (0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ + #define REG_PWM_CMPVUPD4 (0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ + #define REG_PWM_CMPM4 (0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ + #define REG_PWM_CMPMUPD4 (0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ + #define REG_PWM_CMPV5 (0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ + #define REG_PWM_CMPVUPD5 (0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ + #define REG_PWM_CMPM5 (0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ + #define REG_PWM_CMPMUPD5 (0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ + #define REG_PWM_CMPV6 (0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ + #define REG_PWM_CMPVUPD6 (0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ + #define REG_PWM_CMPM6 (0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ + #define REG_PWM_CMPMUPD6 (0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ + #define REG_PWM_CMPV7 (0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ + #define REG_PWM_CMPVUPD7 (0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ + #define REG_PWM_CMPM7 (0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ + #define REG_PWM_CMPMUPD7 (0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ + #define REG_PWM_CMR0 (0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM_CDTY0 (0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM_CDTYUPD0 (0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM_CPRD0 (0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM_CPRDUPD0 (0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM_CCNT0 (0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM_DT0 (0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM_DTUPD0 (0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM_CMR1 (0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM_CDTY1 (0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM_CDTYUPD1 (0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM_CPRD1 (0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM_CPRDUPD1 (0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM_CCNT1 (0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM_DT1 (0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM_DTUPD1 (0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM_CMR2 (0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM_CDTY2 (0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM_CDTYUPD2 (0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM_CPRD2 (0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM_CPRDUPD2 (0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM_CCNT2 (0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM_DT2 (0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM_DTUPD2 (0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM_CMR3 (0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM_CDTY3 (0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM_CDTYUPD3 (0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM_CPRD3 (0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM_CPRDUPD3 (0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM_CCNT3 (0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM_DT3 (0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM_DTUPD3 (0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#else + #define REG_PWM_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM) PWM Clock Register */ + #define REG_PWM_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM) PWM Enable Register */ + #define REG_PWM_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM) PWM Disable Register */ + #define REG_PWM_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM) PWM Status Register */ + #define REG_PWM_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */ + #define REG_PWM_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */ + #define REG_PWM_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */ + #define REG_PWM_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */ + #define REG_PWM_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM) PWM Sync Channels Mode Register */ + #define REG_PWM_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */ + #define REG_PWM_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */ + #define REG_PWM_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */ + #define REG_PWM_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */ + #define REG_PWM_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */ + #define REG_PWM_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */ + #define REG_PWM_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */ + #define REG_PWM_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM) PWM Output Override Value Register */ + #define REG_PWM_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM) PWM Output Selection Register */ + #define REG_PWM_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM) PWM Output Selection Set Register */ + #define REG_PWM_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM) PWM Output Selection Clear Register */ + #define REG_PWM_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM) PWM Output Selection Set Update Register */ + #define REG_PWM_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */ + #define REG_PWM_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM) PWM Fault Mode Register */ + #define REG_PWM_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM) PWM Fault Status Register */ + #define REG_PWM_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM) PWM Fault Clear Register */ + #define REG_PWM_FPV (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM) PWM Fault Protection Value Register */ + #define REG_PWM_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */ + #define REG_PWM_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */ + #define REG_PWM_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM) PWM Write Protect Control Register */ + #define REG_PWM_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM) PWM Write Protect Status Register */ + #define REG_PWM_TPR (*(__IO uint32_t*)0x40020108U) /**< \brief (PWM) Transmit Pointer Register */ + #define REG_PWM_TCR (*(__IO uint32_t*)0x4002010CU) /**< \brief (PWM) Transmit Counter Register */ + #define REG_PWM_TNPR (*(__IO uint32_t*)0x40020118U) /**< \brief (PWM) Transmit Next Pointer Register */ + #define REG_PWM_TNCR (*(__IO uint32_t*)0x4002011CU) /**< \brief (PWM) Transmit Next Counter Register */ + #define REG_PWM_PTCR (*(__O uint32_t*)0x40020120U) /**< \brief (PWM) Transfer Control Register */ + #define REG_PWM_PTSR (*(__I uint32_t*)0x40020124U) /**< \brief (PWM) Transfer Status Register */ + #define REG_PWM_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM) PWM Comparison 0 Value Register */ + #define REG_PWM_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */ + #define REG_PWM_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */ + #define REG_PWM_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */ + #define REG_PWM_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM) PWM Comparison 1 Value Register */ + #define REG_PWM_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */ + #define REG_PWM_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */ + #define REG_PWM_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */ + #define REG_PWM_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM) PWM Comparison 2 Value Register */ + #define REG_PWM_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */ + #define REG_PWM_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */ + #define REG_PWM_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */ + #define REG_PWM_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM) PWM Comparison 3 Value Register */ + #define REG_PWM_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */ + #define REG_PWM_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */ + #define REG_PWM_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */ + #define REG_PWM_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM) PWM Comparison 4 Value Register */ + #define REG_PWM_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */ + #define REG_PWM_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */ + #define REG_PWM_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */ + #define REG_PWM_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM) PWM Comparison 5 Value Register */ + #define REG_PWM_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */ + #define REG_PWM_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */ + #define REG_PWM_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */ + #define REG_PWM_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM) PWM Comparison 6 Value Register */ + #define REG_PWM_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */ + #define REG_PWM_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */ + #define REG_PWM_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */ + #define REG_PWM_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */ + #define REG_PWM_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */ + #define REG_PWM_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */ + #define REG_PWM_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */ + #define REG_PWM_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_PWM_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/rstc.h b/zephyr/ports/asf/sam3sd8/include/instance/rstc.h new file mode 100644 index 0000000..6ead678 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/rstc.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_RSTC_INSTANCE_ +#define _SAM3SD8_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSTC_CR (0x400E1400U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (0x400E1404U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (0x400E1408U) /**< \brief (RSTC) Mode Register */ +#else + #define REG_RSTC_CR (*(__O uint32_t*)0x400E1400U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (*(__I uint32_t*)0x400E1404U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1408U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_RSTC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/rtc.h b/zephyr/ports/asf/sam3sd8/include/instance/rtc.h new file mode 100644 index 0000000..1af0d34 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/rtc.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_RTC_INSTANCE_ +#define _SAM3SD8_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTC_CR (0x400E1460U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (0x400E1464U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (0x400E1468U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (0x400E146CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (0x400E1470U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (0x400E1478U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +#else + #define REG_RTC_CR (*(__IO uint32_t*)0x400E1460U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (*(__IO uint32_t*)0x400E1464U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1468U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (*(__IO uint32_t*)0x400E146CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1470U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1474U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (*(__I uint32_t*)0x400E1478U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (*(__O uint32_t*)0x400E147CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (*(__O uint32_t*)0x400E1480U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (*(__O uint32_t*)0x400E1484U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (*(__I uint32_t*)0x400E1488U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (*(__I uint32_t*)0x400E148CU) /**< \brief (RTC) Valid Entry Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_RTC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/rtt.h b/zephyr/ports/asf/sam3sd8/include/instance/rtt.h new file mode 100644 index 0000000..f861e1c --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/rtt.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_RTT_INSTANCE_ +#define _SAM3SD8_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTT_MR (0x400E1430U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (0x400E1434U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (0x400E1438U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (0x400E143CU) /**< \brief (RTT) Status Register */ +#else + #define REG_RTT_MR (*(__IO uint32_t*)0x400E1430U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (*(__IO uint32_t*)0x400E1434U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (*(__I uint32_t*)0x400E1438U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (*(__I uint32_t*)0x400E143CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_RTT_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/smc.h b/zephyr/ports/asf/sam3sd8/include/instance/smc.h new file mode 100644 index 0000000..6fa141d --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/smc.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SMC_INSTANCE_ +#define _SAM3SD8_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SMC_SETUP0 (0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ + #define REG_SMC_WPSR (0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +#else + #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x400E0000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x400E0004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x400E0008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (*(__IO uint32_t*)0x400E000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x400E0010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x400E0014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x400E0018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (*(__IO uint32_t*)0x400E001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x400E0020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x400E0024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x400E0028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (*(__IO uint32_t*)0x400E002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x400E0030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x400E0034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x400E0038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (*(__IO uint32_t*)0x400E003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */ + #define REG_SMC_OCMS (*(__IO uint32_t*)0x400E0080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (*(__O uint32_t*)0x400E0084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (*(__O uint32_t*)0x400E0088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (*(__IO uint32_t*)0x400E00E4U) /**< \brief (SMC) SMC Write Protect Mode Register */ + #define REG_SMC_WPSR (*(__I uint32_t*)0x400E00E8U) /**< \brief (SMC) SMC Write Protect Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_SMC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/spi.h b/zephyr/ports/asf/sam3sd8/include/instance/spi.h new file mode 100644 index 0000000..69707c5 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/spi.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SPI_INSTANCE_ +#define _SAM3SD8_SPI_INSTANCE_ + +/* ========== Register definition for SPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI_CR (0x40008000U) /**< \brief (SPI) Control Register */ + #define REG_SPI_MR (0x40008004U) /**< \brief (SPI) Mode Register */ + #define REG_SPI_RDR (0x40008008U) /**< \brief (SPI) Receive Data Register */ + #define REG_SPI_TDR (0x4000800CU) /**< \brief (SPI) Transmit Data Register */ + #define REG_SPI_SR (0x40008010U) /**< \brief (SPI) Status Register */ + #define REG_SPI_IER (0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ + #define REG_SPI_IDR (0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ + #define REG_SPI_IMR (0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ + #define REG_SPI_CSR (0x40008030U) /**< \brief (SPI) Chip Select Register */ + #define REG_SPI_WPMR (0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ + #define REG_SPI_WPSR (0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ + #define REG_SPI_RPR (0x40008100U) /**< \brief (SPI) Receive Pointer Register */ + #define REG_SPI_RCR (0x40008104U) /**< \brief (SPI) Receive Counter Register */ + #define REG_SPI_TPR (0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ + #define REG_SPI_TCR (0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ + #define REG_SPI_RNPR (0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ + #define REG_SPI_RNCR (0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ + #define REG_SPI_TNPR (0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ + #define REG_SPI_TNCR (0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ + #define REG_SPI_PTCR (0x40008120U) /**< \brief (SPI) Transfer Control Register */ + #define REG_SPI_PTSR (0x40008124U) /**< \brief (SPI) Transfer Status Register */ +#else + #define REG_SPI_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI) Control Register */ + #define REG_SPI_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI) Mode Register */ + #define REG_SPI_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI) Receive Data Register */ + #define REG_SPI_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI) Transmit Data Register */ + #define REG_SPI_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI) Status Register */ + #define REG_SPI_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI) Interrupt Enable Register */ + #define REG_SPI_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI) Interrupt Disable Register */ + #define REG_SPI_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI) Interrupt Mask Register */ + #define REG_SPI_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI) Chip Select Register */ + #define REG_SPI_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI) Write Protection Control Register */ + #define REG_SPI_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI) Write Protection Status Register */ + #define REG_SPI_RPR (*(__IO uint32_t*)0x40008100U) /**< \brief (SPI) Receive Pointer Register */ + #define REG_SPI_RCR (*(__IO uint32_t*)0x40008104U) /**< \brief (SPI) Receive Counter Register */ + #define REG_SPI_TPR (*(__IO uint32_t*)0x40008108U) /**< \brief (SPI) Transmit Pointer Register */ + #define REG_SPI_TCR (*(__IO uint32_t*)0x4000810CU) /**< \brief (SPI) Transmit Counter Register */ + #define REG_SPI_RNPR (*(__IO uint32_t*)0x40008110U) /**< \brief (SPI) Receive Next Pointer Register */ + #define REG_SPI_RNCR (*(__IO uint32_t*)0x40008114U) /**< \brief (SPI) Receive Next Counter Register */ + #define REG_SPI_TNPR (*(__IO uint32_t*)0x40008118U) /**< \brief (SPI) Transmit Next Pointer Register */ + #define REG_SPI_TNCR (*(__IO uint32_t*)0x4000811CU) /**< \brief (SPI) Transmit Next Counter Register */ + #define REG_SPI_PTCR (*(__O uint32_t*)0x40008120U) /**< \brief (SPI) Transfer Control Register */ + #define REG_SPI_PTSR (*(__I uint32_t*)0x40008124U) /**< \brief (SPI) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_SPI_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/ssc.h b/zephyr/ports/asf/sam3sd8/include/instance/ssc.h new file mode 100644 index 0000000..b987734 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/ssc.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SSC_INSTANCE_ +#define _SAM3SD8_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ + #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ + #define REG_SSC_RPR (0x40004100U) /**< \brief (SSC) Receive Pointer Register */ + #define REG_SSC_RCR (0x40004104U) /**< \brief (SSC) Receive Counter Register */ + #define REG_SSC_TPR (0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ + #define REG_SSC_TCR (0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ + #define REG_SSC_RNPR (0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ + #define REG_SSC_RNCR (0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ + #define REG_SSC_TNPR (0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ + #define REG_SSC_TNCR (0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ + #define REG_SSC_PTCR (0x40004120U) /**< \brief (SSC) Transfer Control Register */ + #define REG_SSC_PTSR (0x40004124U) /**< \brief (SSC) Transfer Status Register */ +#else + #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protect Mode Register */ + #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protect Status Register */ + #define REG_SSC_RPR (*(__IO uint32_t*)0x40004100U) /**< \brief (SSC) Receive Pointer Register */ + #define REG_SSC_RCR (*(__IO uint32_t*)0x40004104U) /**< \brief (SSC) Receive Counter Register */ + #define REG_SSC_TPR (*(__IO uint32_t*)0x40004108U) /**< \brief (SSC) Transmit Pointer Register */ + #define REG_SSC_TCR (*(__IO uint32_t*)0x4000410CU) /**< \brief (SSC) Transmit Counter Register */ + #define REG_SSC_RNPR (*(__IO uint32_t*)0x40004110U) /**< \brief (SSC) Receive Next Pointer Register */ + #define REG_SSC_RNCR (*(__IO uint32_t*)0x40004114U) /**< \brief (SSC) Receive Next Counter Register */ + #define REG_SSC_TNPR (*(__IO uint32_t*)0x40004118U) /**< \brief (SSC) Transmit Next Pointer Register */ + #define REG_SSC_TNCR (*(__IO uint32_t*)0x4000411CU) /**< \brief (SSC) Transmit Next Counter Register */ + #define REG_SSC_PTCR (*(__O uint32_t*)0x40004120U) /**< \brief (SSC) Transfer Control Register */ + #define REG_SSC_PTSR (*(__I uint32_t*)0x40004124U) /**< \brief (SSC) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_SSC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/supc.h b/zephyr/ports/asf/sam3sd8/include/instance/supc.h new file mode 100644 index 0000000..080bdb3 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/supc.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_SUPC_INSTANCE_ +#define _SAM3SD8_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SUPC_CR (0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ + #define REG_SUPC_WUIR (0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ + #define REG_SUPC_SR (0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +#else + #define REG_SUPC_CR (*(__O uint32_t*)0x400E1410U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1414U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1418U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E141CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */ + #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1420U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */ + #define REG_SUPC_SR (*(__I uint32_t*)0x400E1424U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_SUPC_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/tc0.h b/zephyr/ports/asf/sam3sd8/include/instance/tc0.h new file mode 100644 index 0000000..34c774d --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/tc0.h @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_TC0_INSTANCE_ +#define _SAM3SD8_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC0_CCR0 (0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_CV0 (0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_CCR1 (0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_CV1 (0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_CCR2 (0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_CV2 (0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_BCR (0x400100C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (0x400100C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (0x400100D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#else + #define REG_TC0_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC0) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_TC0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/tc1.h b/zephyr/ports/asf/sam3sd8/include/instance/tc1.h new file mode 100644 index 0000000..01330ac --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/tc1.h @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_TC1_INSTANCE_ +#define _SAM3SD8_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC1_CCR0 (0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_CV0 (0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_CCR1 (0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_CV1 (0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_CCR2 (0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_CV2 (0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_BCR (0x400140C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (0x400140C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (0x400140D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#else + #define REG_TC1_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC1) Write Protect Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_TC1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/twi0.h b/zephyr/ports/asf/sam3sd8/include/instance/twi0.h new file mode 100644 index 0000000..8436d57 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/twi0.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_TWI0_INSTANCE_ +#define _SAM3SD8_TWI0_INSTANCE_ + +/* ========== Register definition for TWI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWI0_CR (0x40018000U) /**< \brief (TWI0) Control Register */ + #define REG_TWI0_MMR (0x40018004U) /**< \brief (TWI0) Master Mode Register */ + #define REG_TWI0_SMR (0x40018008U) /**< \brief (TWI0) Slave Mode Register */ + #define REG_TWI0_IADR (0x4001800CU) /**< \brief (TWI0) Internal Address Register */ + #define REG_TWI0_CWGR (0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ + #define REG_TWI0_SR (0x40018020U) /**< \brief (TWI0) Status Register */ + #define REG_TWI0_IER (0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ + #define REG_TWI0_IDR (0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ + #define REG_TWI0_IMR (0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ + #define REG_TWI0_RHR (0x40018030U) /**< \brief (TWI0) Receive Holding Register */ + #define REG_TWI0_THR (0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ + #define REG_TWI0_RPR (0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ + #define REG_TWI0_RCR (0x40018104U) /**< \brief (TWI0) Receive Counter Register */ + #define REG_TWI0_TPR (0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ + #define REG_TWI0_TCR (0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ + #define REG_TWI0_RNPR (0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ + #define REG_TWI0_RNCR (0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ + #define REG_TWI0_TNPR (0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ + #define REG_TWI0_TNCR (0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ + #define REG_TWI0_PTCR (0x40018120U) /**< \brief (TWI0) Transfer Control Register */ + #define REG_TWI0_PTSR (0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +#else + #define REG_TWI0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWI0) Control Register */ + #define REG_TWI0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWI0) Master Mode Register */ + #define REG_TWI0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWI0) Slave Mode Register */ + #define REG_TWI0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWI0) Internal Address Register */ + #define REG_TWI0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWI0) Clock Waveform Generator Register */ + #define REG_TWI0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWI0) Status Register */ + #define REG_TWI0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWI0) Interrupt Enable Register */ + #define REG_TWI0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWI0) Interrupt Disable Register */ + #define REG_TWI0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWI0) Interrupt Mask Register */ + #define REG_TWI0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWI0) Receive Holding Register */ + #define REG_TWI0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWI0) Transmit Holding Register */ + #define REG_TWI0_RPR (*(__IO uint32_t*)0x40018100U) /**< \brief (TWI0) Receive Pointer Register */ + #define REG_TWI0_RCR (*(__IO uint32_t*)0x40018104U) /**< \brief (TWI0) Receive Counter Register */ + #define REG_TWI0_TPR (*(__IO uint32_t*)0x40018108U) /**< \brief (TWI0) Transmit Pointer Register */ + #define REG_TWI0_TCR (*(__IO uint32_t*)0x4001810CU) /**< \brief (TWI0) Transmit Counter Register */ + #define REG_TWI0_RNPR (*(__IO uint32_t*)0x40018110U) /**< \brief (TWI0) Receive Next Pointer Register */ + #define REG_TWI0_RNCR (*(__IO uint32_t*)0x40018114U) /**< \brief (TWI0) Receive Next Counter Register */ + #define REG_TWI0_TNPR (*(__IO uint32_t*)0x40018118U) /**< \brief (TWI0) Transmit Next Pointer Register */ + #define REG_TWI0_TNCR (*(__IO uint32_t*)0x4001811CU) /**< \brief (TWI0) Transmit Next Counter Register */ + #define REG_TWI0_PTCR (*(__O uint32_t*)0x40018120U) /**< \brief (TWI0) Transfer Control Register */ + #define REG_TWI0_PTSR (*(__I uint32_t*)0x40018124U) /**< \brief (TWI0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_TWI0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/twi1.h b/zephyr/ports/asf/sam3sd8/include/instance/twi1.h new file mode 100644 index 0000000..2912ef7 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/twi1.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_TWI1_INSTANCE_ +#define _SAM3SD8_TWI1_INSTANCE_ + +/* ========== Register definition for TWI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWI1_CR (0x4001C000U) /**< \brief (TWI1) Control Register */ + #define REG_TWI1_MMR (0x4001C004U) /**< \brief (TWI1) Master Mode Register */ + #define REG_TWI1_SMR (0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ + #define REG_TWI1_IADR (0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ + #define REG_TWI1_CWGR (0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ + #define REG_TWI1_SR (0x4001C020U) /**< \brief (TWI1) Status Register */ + #define REG_TWI1_IER (0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ + #define REG_TWI1_IDR (0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ + #define REG_TWI1_IMR (0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ + #define REG_TWI1_RHR (0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ + #define REG_TWI1_THR (0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ + #define REG_TWI1_RPR (0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ + #define REG_TWI1_RCR (0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ + #define REG_TWI1_TPR (0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ + #define REG_TWI1_TCR (0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ + #define REG_TWI1_RNPR (0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ + #define REG_TWI1_RNCR (0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ + #define REG_TWI1_TNPR (0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ + #define REG_TWI1_TNCR (0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ + #define REG_TWI1_PTCR (0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ + #define REG_TWI1_PTSR (0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +#else + #define REG_TWI1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWI1) Control Register */ + #define REG_TWI1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWI1) Master Mode Register */ + #define REG_TWI1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWI1) Slave Mode Register */ + #define REG_TWI1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWI1) Internal Address Register */ + #define REG_TWI1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWI1) Clock Waveform Generator Register */ + #define REG_TWI1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWI1) Status Register */ + #define REG_TWI1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWI1) Interrupt Enable Register */ + #define REG_TWI1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWI1) Interrupt Disable Register */ + #define REG_TWI1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWI1) Interrupt Mask Register */ + #define REG_TWI1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWI1) Receive Holding Register */ + #define REG_TWI1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWI1) Transmit Holding Register */ + #define REG_TWI1_RPR (*(__IO uint32_t*)0x4001C100U) /**< \brief (TWI1) Receive Pointer Register */ + #define REG_TWI1_RCR (*(__IO uint32_t*)0x4001C104U) /**< \brief (TWI1) Receive Counter Register */ + #define REG_TWI1_TPR (*(__IO uint32_t*)0x4001C108U) /**< \brief (TWI1) Transmit Pointer Register */ + #define REG_TWI1_TCR (*(__IO uint32_t*)0x4001C10CU) /**< \brief (TWI1) Transmit Counter Register */ + #define REG_TWI1_RNPR (*(__IO uint32_t*)0x4001C110U) /**< \brief (TWI1) Receive Next Pointer Register */ + #define REG_TWI1_RNCR (*(__IO uint32_t*)0x4001C114U) /**< \brief (TWI1) Receive Next Counter Register */ + #define REG_TWI1_TNPR (*(__IO uint32_t*)0x4001C118U) /**< \brief (TWI1) Transmit Next Pointer Register */ + #define REG_TWI1_TNCR (*(__IO uint32_t*)0x4001C11CU) /**< \brief (TWI1) Transmit Next Counter Register */ + #define REG_TWI1_PTCR (*(__O uint32_t*)0x4001C120U) /**< \brief (TWI1) Transfer Control Register */ + #define REG_TWI1_PTSR (*(__I uint32_t*)0x4001C124U) /**< \brief (TWI1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_TWI1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/uart0.h b/zephyr/ports/asf/sam3sd8/include/instance/uart0.h new file mode 100644 index 0000000..2c31e85 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/uart0.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_UART0_INSTANCE_ +#define _SAM3SD8_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ + #define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */ + #define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ + #define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ + #define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ + #define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ + #define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ + #define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ + #define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */ + #define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +#else + #define REG_UART0_CR (*(__O uint32_t*)0x400E0600U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (*(__IO uint32_t*)0x400E0604U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (*(__O uint32_t*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (*(__O uint32_t*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (*(__I uint32_t*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (*(__I uint32_t*)0x400E0614U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (*(__I uint32_t*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (*(__O uint32_t*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_RPR (*(__IO uint32_t*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */ + #define REG_UART0_RCR (*(__IO uint32_t*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */ + #define REG_UART0_TPR (*(__IO uint32_t*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */ + #define REG_UART0_TCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */ + #define REG_UART0_RNPR (*(__IO uint32_t*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */ + #define REG_UART0_RNCR (*(__IO uint32_t*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */ + #define REG_UART0_TNPR (*(__IO uint32_t*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */ + #define REG_UART0_TNCR (*(__IO uint32_t*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */ + #define REG_UART0_PTCR (*(__O uint32_t*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */ + #define REG_UART0_PTSR (*(__I uint32_t*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_UART0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/uart1.h b/zephyr/ports/asf/sam3sd8/include/instance/uart1.h new file mode 100644 index 0000000..eda4dfb --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/uart1.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_UART1_INSTANCE_ +#define _SAM3SD8_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART1_CR (0x400E0800U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (0x400E0804U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (0x400E0814U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (0x400E0818U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_RPR (0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ + #define REG_UART1_RCR (0x400E0904U) /**< \brief (UART1) Receive Counter Register */ + #define REG_UART1_TPR (0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ + #define REG_UART1_TCR (0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ + #define REG_UART1_RNPR (0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ + #define REG_UART1_RNCR (0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ + #define REG_UART1_TNPR (0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ + #define REG_UART1_TNCR (0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ + #define REG_UART1_PTCR (0x400E0920U) /**< \brief (UART1) Transfer Control Register */ + #define REG_UART1_PTSR (0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +#else + #define REG_UART1_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_RPR (*(__IO uint32_t*)0x400E0900U) /**< \brief (UART1) Receive Pointer Register */ + #define REG_UART1_RCR (*(__IO uint32_t*)0x400E0904U) /**< \brief (UART1) Receive Counter Register */ + #define REG_UART1_TPR (*(__IO uint32_t*)0x400E0908U) /**< \brief (UART1) Transmit Pointer Register */ + #define REG_UART1_TCR (*(__IO uint32_t*)0x400E090CU) /**< \brief (UART1) Transmit Counter Register */ + #define REG_UART1_RNPR (*(__IO uint32_t*)0x400E0910U) /**< \brief (UART1) Receive Next Pointer Register */ + #define REG_UART1_RNCR (*(__IO uint32_t*)0x400E0914U) /**< \brief (UART1) Receive Next Counter Register */ + #define REG_UART1_TNPR (*(__IO uint32_t*)0x400E0918U) /**< \brief (UART1) Transmit Next Pointer Register */ + #define REG_UART1_TNCR (*(__IO uint32_t*)0x400E091CU) /**< \brief (UART1) Transmit Next Counter Register */ + #define REG_UART1_PTCR (*(__O uint32_t*)0x400E0920U) /**< \brief (UART1) Transfer Control Register */ + #define REG_UART1_PTSR (*(__I uint32_t*)0x400E0924U) /**< \brief (UART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_UART1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/udp.h b/zephyr/ports/asf/sam3sd8/include/instance/udp.h new file mode 100644 index 0000000..08fac05 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/udp.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_UDP_INSTANCE_ +#define _SAM3SD8_UDP_INSTANCE_ + +/* ========== Register definition for UDP peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UDP_FRM_NUM (0x40034000U) /**< \brief (UDP) Frame Number Register */ + #define REG_UDP_GLB_STAT (0x40034004U) /**< \brief (UDP) Global State Register */ + #define REG_UDP_FADDR (0x40034008U) /**< \brief (UDP) Function Address Register */ + #define REG_UDP_IER (0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ + #define REG_UDP_IDR (0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ + #define REG_UDP_IMR (0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ + #define REG_UDP_ISR (0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ + #define REG_UDP_ICR (0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ + #define REG_UDP_RST_EP (0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ + #define REG_UDP_CSR (0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */ + #define REG_UDP_FDR (0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */ + #define REG_UDP_TXVC (0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +#else + #define REG_UDP_FRM_NUM (*(__I uint32_t*)0x40034000U) /**< \brief (UDP) Frame Number Register */ + #define REG_UDP_GLB_STAT (*(__IO uint32_t*)0x40034004U) /**< \brief (UDP) Global State Register */ + #define REG_UDP_FADDR (*(__IO uint32_t*)0x40034008U) /**< \brief (UDP) Function Address Register */ + #define REG_UDP_IER (*(__O uint32_t*)0x40034010U) /**< \brief (UDP) Interrupt Enable Register */ + #define REG_UDP_IDR (*(__O uint32_t*)0x40034014U) /**< \brief (UDP) Interrupt Disable Register */ + #define REG_UDP_IMR (*(__I uint32_t*)0x40034018U) /**< \brief (UDP) Interrupt Mask Register */ + #define REG_UDP_ISR (*(__I uint32_t*)0x4003401CU) /**< \brief (UDP) Interrupt Status Register */ + #define REG_UDP_ICR (*(__O uint32_t*)0x40034020U) /**< \brief (UDP) Interrupt Clear Register */ + #define REG_UDP_RST_EP (*(__IO uint32_t*)0x40034028U) /**< \brief (UDP) Reset Endpoint Register */ + #define REG_UDP_CSR (*(__IO uint32_t*)0x40034030U) /**< \brief (UDP) Endpoint Control and Status Register */ + #define REG_UDP_FDR (*(__IO uint32_t*)0x40034050U) /**< \brief (UDP) Endpoint FIFO Data Register */ + #define REG_UDP_TXVC (*(__IO uint32_t*)0x40034074U) /**< \brief (UDP) Transceiver Control Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_UDP_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/usart0.h b/zephyr/ports/asf/sam3sd8/include/instance/usart0.h new file mode 100644 index 0000000..b62ce36 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/usart0.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_USART0_INSTANCE_ +#define _SAM3SD8_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receiver Holding Register */ + #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ + #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ + #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ + #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ + #define REG_USART0_VERSION (0x400240FCU) /**< \brief (USART0) Version Register */ + #define REG_USART0_RPR (0x40024100U) /**< \brief (USART0) Receive Pointer Register */ + #define REG_USART0_RCR (0x40024104U) /**< \brief (USART0) Receive Counter Register */ + #define REG_USART0_TPR (0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ + #define REG_USART0_TCR (0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ + #define REG_USART0_RNPR (0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ + #define REG_USART0_RNCR (0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ + #define REG_USART0_TNPR (0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ + #define REG_USART0_TNCR (0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ + #define REG_USART0_PTCR (0x40024120U) /**< \brief (USART0) Transfer Control Register */ + #define REG_USART0_PTSR (0x40024124U) /**< \brief (USART0) Transfer Status Register */ +#else + #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receiver Holding Register */ + #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmitter Holding Register */ + #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_FIDI (*(__IO uint32_t*)0x40024040U) /**< \brief (USART0) FI DI Ratio Register */ + #define REG_USART0_NER (*(__I uint32_t*)0x40024044U) /**< \brief (USART0) Number of Errors Register */ + #define REG_USART0_IF (*(__IO uint32_t*)0x4002404CU) /**< \brief (USART0) IrDA Filter Register */ + #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Encoder Decoder Register */ + #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protect Mode Register */ + #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protect Status Register */ + #define REG_USART0_VERSION (*(__I uint32_t*)0x400240FCU) /**< \brief (USART0) Version Register */ + #define REG_USART0_RPR (*(__IO uint32_t*)0x40024100U) /**< \brief (USART0) Receive Pointer Register */ + #define REG_USART0_RCR (*(__IO uint32_t*)0x40024104U) /**< \brief (USART0) Receive Counter Register */ + #define REG_USART0_TPR (*(__IO uint32_t*)0x40024108U) /**< \brief (USART0) Transmit Pointer Register */ + #define REG_USART0_TCR (*(__IO uint32_t*)0x4002410CU) /**< \brief (USART0) Transmit Counter Register */ + #define REG_USART0_RNPR (*(__IO uint32_t*)0x40024110U) /**< \brief (USART0) Receive Next Pointer Register */ + #define REG_USART0_RNCR (*(__IO uint32_t*)0x40024114U) /**< \brief (USART0) Receive Next Counter Register */ + #define REG_USART0_TNPR (*(__IO uint32_t*)0x40024118U) /**< \brief (USART0) Transmit Next Pointer Register */ + #define REG_USART0_TNCR (*(__IO uint32_t*)0x4002411CU) /**< \brief (USART0) Transmit Next Counter Register */ + #define REG_USART0_PTCR (*(__O uint32_t*)0x40024120U) /**< \brief (USART0) Transfer Control Register */ + #define REG_USART0_PTSR (*(__I uint32_t*)0x40024124U) /**< \brief (USART0) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_USART0_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/usart1.h b/zephyr/ports/asf/sam3sd8/include/instance/usart1.h new file mode 100644 index 0000000..dc7ed66 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/usart1.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_USART1_INSTANCE_ +#define _SAM3SD8_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receiver Holding Register */ + #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ + #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ + #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ + #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ + #define REG_USART1_VERSION (0x400280FCU) /**< \brief (USART1) Version Register */ + #define REG_USART1_RPR (0x40028100U) /**< \brief (USART1) Receive Pointer Register */ + #define REG_USART1_RCR (0x40028104U) /**< \brief (USART1) Receive Counter Register */ + #define REG_USART1_TPR (0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ + #define REG_USART1_TCR (0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ + #define REG_USART1_RNPR (0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ + #define REG_USART1_RNCR (0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ + #define REG_USART1_TNPR (0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ + #define REG_USART1_TNCR (0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ + #define REG_USART1_PTCR (0x40028120U) /**< \brief (USART1) Transfer Control Register */ + #define REG_USART1_PTSR (0x40028124U) /**< \brief (USART1) Transfer Status Register */ +#else + #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receiver Holding Register */ + #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmitter Holding Register */ + #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_FIDI (*(__IO uint32_t*)0x40028040U) /**< \brief (USART1) FI DI Ratio Register */ + #define REG_USART1_NER (*(__I uint32_t*)0x40028044U) /**< \brief (USART1) Number of Errors Register */ + #define REG_USART1_IF (*(__IO uint32_t*)0x4002804CU) /**< \brief (USART1) IrDA Filter Register */ + #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Encoder Decoder Register */ + #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protect Mode Register */ + #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protect Status Register */ + #define REG_USART1_VERSION (*(__I uint32_t*)0x400280FCU) /**< \brief (USART1) Version Register */ + #define REG_USART1_RPR (*(__IO uint32_t*)0x40028100U) /**< \brief (USART1) Receive Pointer Register */ + #define REG_USART1_RCR (*(__IO uint32_t*)0x40028104U) /**< \brief (USART1) Receive Counter Register */ + #define REG_USART1_TPR (*(__IO uint32_t*)0x40028108U) /**< \brief (USART1) Transmit Pointer Register */ + #define REG_USART1_TCR (*(__IO uint32_t*)0x4002810CU) /**< \brief (USART1) Transmit Counter Register */ + #define REG_USART1_RNPR (*(__IO uint32_t*)0x40028110U) /**< \brief (USART1) Receive Next Pointer Register */ + #define REG_USART1_RNCR (*(__IO uint32_t*)0x40028114U) /**< \brief (USART1) Receive Next Counter Register */ + #define REG_USART1_TNPR (*(__IO uint32_t*)0x40028118U) /**< \brief (USART1) Transmit Next Pointer Register */ + #define REG_USART1_TNCR (*(__IO uint32_t*)0x4002811CU) /**< \brief (USART1) Transmit Next Counter Register */ + #define REG_USART1_PTCR (*(__O uint32_t*)0x40028120U) /**< \brief (USART1) Transfer Control Register */ + #define REG_USART1_PTSR (*(__I uint32_t*)0x40028124U) /**< \brief (USART1) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_USART1_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/usart2.h b/zephyr/ports/asf/sam3sd8/include/instance/usart2.h new file mode 100644 index 0000000..39d4c25 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/usart2.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_USART2_INSTANCE_ +#define _SAM3SD8_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receiver Holding Register */ + #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */ + #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ + #define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */ + #define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ + #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ + #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */ + #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */ + #define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */ + #define REG_USART2_RPR (0x4002C100U) /**< \brief (USART2) Receive Pointer Register */ + #define REG_USART2_RCR (0x4002C104U) /**< \brief (USART2) Receive Counter Register */ + #define REG_USART2_TPR (0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */ + #define REG_USART2_TCR (0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */ + #define REG_USART2_RNPR (0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */ + #define REG_USART2_RNCR (0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */ + #define REG_USART2_TNPR (0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */ + #define REG_USART2_TNCR (0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */ + #define REG_USART2_PTCR (0x4002C120U) /**< \brief (USART2) Transfer Control Register */ + #define REG_USART2_PTSR (0x4002C124U) /**< \brief (USART2) Transfer Status Register */ +#else + #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receiver Holding Register */ + #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */ + #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */ + #define REG_USART2_NER (*(__I uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */ + #define REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */ + #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */ + #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */ + #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */ + #define REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */ + #define REG_USART2_RPR (*(__IO uint32_t*)0x4002C100U) /**< \brief (USART2) Receive Pointer Register */ + #define REG_USART2_RCR (*(__IO uint32_t*)0x4002C104U) /**< \brief (USART2) Receive Counter Register */ + #define REG_USART2_TPR (*(__IO uint32_t*)0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */ + #define REG_USART2_TCR (*(__IO uint32_t*)0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */ + #define REG_USART2_RNPR (*(__IO uint32_t*)0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */ + #define REG_USART2_RNCR (*(__IO uint32_t*)0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */ + #define REG_USART2_TNPR (*(__IO uint32_t*)0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */ + #define REG_USART2_TNCR (*(__IO uint32_t*)0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */ + #define REG_USART2_PTCR (*(__O uint32_t*)0x4002C120U) /**< \brief (USART2) Transfer Control Register */ + #define REG_USART2_PTSR (*(__I uint32_t*)0x4002C124U) /**< \brief (USART2) Transfer Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_USART2_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/instance/wdt.h b/zephyr/ports/asf/sam3sd8/include/instance/wdt.h new file mode 100644 index 0000000..29a9363 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/instance/wdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_WDT_INSTANCE_ +#define _SAM3SD8_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_WDT_CR (0x400E1450U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (0x400E1454U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (0x400E1458U) /**< \brief (WDT) Status Register */ +#else + #define REG_WDT_CR (*(__O uint32_t*)0x400E1450U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (*(__IO uint32_t*)0x400E1454U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (*(__I uint32_t*)0x400E1458U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAM3SD8_WDT_INSTANCE_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/pio/sam3s8b.h b/zephyr/ports/asf/sam3sd8/include/pio/sam3s8b.h new file mode 100644 index 0000000..7d3da9a --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/pio/sam3s8b.h @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S8B_PIO_ +#define _SAM3S8B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 + +#endif /* _SAM3S8B_PIO_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/pio/sam3s8c.h b/zephyr/ports/asf/sam3sd8/include/pio/sam3s8c.h new file mode 100644 index 0000000..f694e13 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/pio/sam3s8c.h @@ -0,0 +1,403 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S8C_PIO_ +#define _SAM3S8C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PC17B_CTS2 (1u << 17) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PC16B_RTS2 (1u << 16) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PC9B_RXD2 (1u << 9) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PC14B_SCK2 (1u << 14) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PC10B_TXD2 (1u << 10) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 + +#endif /* _SAM3S8C_PIO_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/pio/sam3sd8b.h b/zephyr/ports/asf/sam3sd8/include/pio/sam3sd8b.h new file mode 100644 index 0000000..8ff4e10 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/pio/sam3sd8b.h @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8B_PIO_ +#define _SAM3SD8B_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 + +#endif /* _SAM3SD8B_PIO_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/pio/sam3sd8c.h b/zephyr/ports/asf/sam3sd8/include/pio/sam3sd8c.h new file mode 100644 index 0000000..1675f91 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/pio/sam3sd8c.h @@ -0,0 +1,403 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8C_PIO_ +#define _SAM3SD8C_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB10 (1u << 10) /**< \brief Pin Controlled by PB10 */ +#define PIO_PB11 (1u << 11) /**< \brief Pin Controlled by PB11 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PB14 (1u << 14) /**< \brief Pin Controlled by PB14 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +/* ========== Pio definition for ADC peripheral ========== */ +#define PIO_PA17X1_AD0 (1u << 17) /**< \brief Adc signal: AD0 */ +#define PIO_PA18X1_AD1 (1u << 18) /**< \brief Adc signal: AD1 */ +#define PIO_PC13X1_AD10 (1u << 13) /**< \brief Adc signal: AD10 */ +#define PIO_PC15X1_AD11 (1u << 15) /**< \brief Adc signal: AD11 */ +#define PIO_PC12X1_AD12 (1u << 12) /**< \brief Adc signal: AD12 */ +#define PIO_PC29X1_AD13 (1u << 29) /**< \brief Adc signal: AD13 */ +#define PIO_PC30X1_AD14 (1u << 30) /**< \brief Adc signal: AD14 */ +#define PIO_PA19X1_AD2 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Adc signal: AD2/WKUP9 */ +#define PIO_PA20X1_AD3 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Adc signal: AD3/WKUP10 */ +#define PIO_PB0X1_AD4 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Adc signal: AD4/RTCOUT0 */ +#define PIO_PB1X1_AD5 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Adc signal: AD5/RTCOUT1 */ +#define PIO_PB2X1_AD6 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB2X1_WKUP12 (1u << 2) /**< \brief Adc signal: AD6/WKUP12 */ +#define PIO_PB3X1_AD7 (1u << 3) /**< \brief Adc signal: AD7 */ +#define PIO_PA21X1_AD8 (1u << 21) /**< \brief Adc signal: AD8 */ +#define PIO_PA22X1_AD9 (1u << 22) /**< \brief Adc signal: AD9 */ +#define PIO_PA8B_ADTRG (1u << 8) /**< \brief Adc signal: ADTRG */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PB14X1_DAC1 (1u << 14) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1 */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWE */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA29C_MCCK (1u << 29) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA24D_PIODC0 (1u << 24) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA25D_PIODC1 (1u << 25) /**< \brief Pioa signal: PIODC1 */ +#define PIO_PA26D_PIODC2 (1u << 26) /**< \brief Pioa signal: PIODC2 */ +#define PIO_PA27D_PIODC3 (1u << 27) /**< \brief Pioa signal: PIODC3 */ +#define PIO_PA28D_PIODC4 (1u << 28) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA29D_PIODC5 (1u << 29) /**< \brief Pioa signal: PIODC5 */ +#define PIO_PA30D_PIODC6 (1u << 30) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA31D_PIODC7 (1u << 31) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA23D_PIODCCLK (1u << 23) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA15D_PIODCEN1 (1u << 15) /**< \brief Pioa signal: PIODCEN1 */ +#define PIO_PA16D_PIODCEN2 (1u << 16) /**< \brief Pioa signal: PIODCEN2 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM peripheral ========== */ +#define PIO_PA9C_PWMFI0 (1u << 9) /**< \brief Pwm signal: PWMFI0 */ +#define PIO_PA0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA11B_PWMH0 (1u << 11) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA23B_PWMH0 (1u << 23) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PB0A_PWMH0 (1u << 0) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PC18B_PWMH0 (1u << 18) /**< \brief Pwm signal: PWMH0 */ +#define PIO_PA1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA12B_PWMH1 (1u << 12) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA24B_PWMH1 (1u << 24) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PB1A_PWMH1 (1u << 1) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PC19B_PWMH1 (1u << 19) /**< \brief Pwm signal: PWMH1 */ +#define PIO_PA2A_PWMH2 (1u << 2) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA13B_PWMH2 (1u << 13) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA25B_PWMH2 (1u << 25) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PB4B_PWMH2 (1u << 4) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PC20B_PWMH2 (1u << 20) /**< \brief Pwm signal: PWMH2 */ +#define PIO_PA7B_PWMH3 (1u << 7) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA17C_PWMH3 (1u << 17) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PB14B_PWMH3 (1u << 14) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PC21B_PWMH3 (1u << 21) /**< \brief Pwm signal: PWMH3 */ +#define PIO_PA19B_PWML0 (1u << 19) /**< \brief Pwm signal: PWML0 */ +#define PIO_PB5B_PWML0 (1u << 5) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC0B_PWML0 (1u << 0) /**< \brief Pwm signal: PWML0 */ +#define PIO_PC13B_PWML0 (1u << 13) /**< \brief Pwm signal: PWML0 */ +#define PIO_PA20B_PWML1 (1u << 20) /**< \brief Pwm signal: PWML1 */ +#define PIO_PB12A_PWML1 (1u << 12) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC1B_PWML1 (1u << 1) /**< \brief Pwm signal: PWML1 */ +#define PIO_PC15B_PWML1 (1u << 15) /**< \brief Pwm signal: PWML1 */ +#define PIO_PA16C_PWML2 (1u << 16) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA30A_PWML2 (1u << 30) /**< \brief Pwm signal: PWML2 */ +#define PIO_PB13A_PWML2 (1u << 13) /**< \brief Pwm signal: PWML2 */ +#define PIO_PC2B_PWML2 (1u << 2) /**< \brief Pwm signal: PWML2 */ +#define PIO_PA15C_PWML3 (1u << 15) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC3B_PWML3 (1u << 3) /**< \brief Pwm signal: PWML3 */ +#define PIO_PC22B_PWML3 (1u << 22) /**< \brief Pwm signal: PWML3 */ +/* ========== Pio definition for SPI peripheral ========== */ +#define PIO_PA12A_MISO (1u << 12) /**< \brief Spi signal: MISO */ +#define PIO_PA13A_MOSI (1u << 13) /**< \brief Spi signal: MOSI */ +#define PIO_PA11A_NPCS0 (1u << 11) /**< \brief Spi signal: NPCS0 */ +#define PIO_PA9B_NPCS1 (1u << 9) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA31A_NPCS1 (1u << 31) /**< \brief Spi signal: NPCS1 */ +#define PIO_PB14A_NPCS1 (1u << 14) /**< \brief Spi signal: NPCS1 */ +#define PIO_PC4B_NPCS1 (1u << 4) /**< \brief Spi signal: NPCS1 */ +#define PIO_PA10B_NPCS2 (1u << 10) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA30B_NPCS2 (1u << 30) /**< \brief Spi signal: NPCS2 */ +#define PIO_PB2B_NPCS2 (1u << 2) /**< \brief Spi signal: NPCS2 */ +#define PIO_PA3B_NPCS3 (1u << 3) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA5B_NPCS3 (1u << 5) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA22B_NPCS3 (1u << 22) /**< \brief Spi signal: NPCS3 */ +#define PIO_PA14A_SPCK (1u << 14) /**< \brief Spi signal: SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA18A_RD (1u << 18) /**< \brief Ssc signal: RD */ +#define PIO_PA20A_RF (1u << 20) /**< \brief Ssc signal: RF */ +#define PIO_PA19A_RK (1u << 19) /**< \brief Ssc signal: RK */ +#define PIO_PA17A_TD (1u << 17) /**< \brief Ssc signal: TD */ +#define PIO_PA15A_TF (1u << 15) /**< \brief Ssc signal: TF */ +#define PIO_PA16A_TK (1u << 16) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TWI0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twi0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twi0 signal: TWD0 */ +/* ========== Pio definition for TWI1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twi1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twi1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PB2A_URXD1 (1u << 2) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PB3A_UTXD1 (1u << 3) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PA8A_CTS0 (1u << 8) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PA7A_RTS0 (1u << 7) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PA5A_RXD0 (1u << 5) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PA2B_SCK0 (1u << 2) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PA6A_TXD0 (1u << 6) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PA22A_TXD1 (1u << 22) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PC17B_CTS2 (1u << 17) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PC16B_RTS2 (1u << 16) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PC9B_RXD2 (1u << 9) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PC14B_SCK2 (1u << 14) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PC10B_TXD2 (1u << 10) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB10_IDX 42 +#define PIO_PB11_IDX 43 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PB14_IDX 46 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 + +#endif /* _SAM3SD8C_PIO_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/sam.h b/zephyr/ports/asf/sam3sd8/include/sam.h new file mode 100644 index 0000000..d36557d --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/sam.h @@ -0,0 +1,60 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAM3S8B__) || defined(__ATSAM3S8B__) + #include "sam3s8b.h" +#elif defined(__SAM3S8C__) || defined(__ATSAM3S8C__) + #include "sam3s8c.h" +#elif defined(__SAM3SD8B__) || defined(__ATSAM3SD8B__) + #include "sam3sd8b.h" +#elif defined(__SAM3SD8C__) || defined(__ATSAM3SD8C__) + #include "sam3sd8c.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_ */ + diff --git a/zephyr/ports/asf/sam3sd8/include/sam3s8b.h b/zephyr/ports/asf/sam3sd8/include/sam3s8b.h new file mode 100644 index 0000000..16a386f --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/sam3s8b.h @@ -0,0 +1,496 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S8B_ +#define _SAM3S8B_ + +/** \addtogroup SAM3S8B_definitions SAM3S8B definitions + This file defines all structures and symbols for SAM3S8B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S8B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S8B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S8B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S8B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S8B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S8B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S8B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S8B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S8B UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S8B UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S8B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S8B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3S8B USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S8B USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3S8B Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S8B Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S8B Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S8B Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S8B Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S8B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S8B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S8B Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3S8B Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S8B Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S8B Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S8B CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S8B Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S8B USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S8B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S8B does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S8B uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3sd8.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s8b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x80000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (2048u) +#define IFLASH0_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0x10000u) +#define IFLASH_SIZE (IFLASH0_SIZE) + +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x289B0A60UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (10UL) +#define NB_CH_DAC (2UL) +#define USB_DEVICE_MAX_EP (8UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S8B */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S8B_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/sam3s8c.h b/zephyr/ports/asf/sam3sd8/include/sam3s8c.h new file mode 100644 index 0000000..8d1b2b4 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/sam3s8c.h @@ -0,0 +1,527 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3S8C_ +#define _SAM3S8C_ + +/** \addtogroup SAM3S8C_definitions SAM3S8C definitions + This file defines all structures and symbols for SAM3S8C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3S8C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3S8C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3S8C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3S8C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3S8C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3S8C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3S8C Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3S8C Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3S8C UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3S8C UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3S8C Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3S8C Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3S8C Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 SAM3S8C USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3S8C USART 1 (USART1) */ + USART2_IRQn = 16, /**< 16 SAM3S8C USART 2 (SAM3SD8 100 pins only) (USART2) */ + HSMCI_IRQn = 18, /**< 18 SAM3S8C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3S8C Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3S8C Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3S8C Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3S8C Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3S8C Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3S8C Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3S8C Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAM3S8C Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAM3S8C Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAM3S8C Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 SAM3S8C Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3S8C Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3S8C Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3S8C CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3S8C Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3S8C USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pfnUSART2_Handler; /* 16 USART 2 (SAM3SD8 100 pins only) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3S8C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3S8C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3S8C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3sd8.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3S8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8C_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/smc.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3S8C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3s8c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x80000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (2048u) +#define IFLASH0_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0x10000u) +#define IFLASH_SIZE (IFLASH0_SIZE) + +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x28AB0A60UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (15UL) +#define NB_CH_DAC (2UL) +#define USB_DEVICE_MAX_EP (8UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3S8C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3S8C_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/sam3sd8.h b/zephyr/ports/asf/sam3sd8/include/sam3sd8.h new file mode 100644 index 0000000..2d811bc --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/sam3sd8.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8_ +#define _SAM3SD8_ + +#if defined __SAM3SD8B__ + #include "sam3sd8b.h" +#elif defined __SAM3SD8C__ + #include "sam3sd8c.h" +#elif defined __SAM3S8B__ + #include "sam3s8b.h" +#elif defined __SAM3S8C__ + #include "sam3s8c.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAM3SD8_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/sam3sd8b.h b/zephyr/ports/asf/sam3sd8/include/sam3sd8b.h new file mode 100644 index 0000000..5b4fd27 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/sam3sd8b.h @@ -0,0 +1,507 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8B_ +#define _SAM3SD8B_ + +/** \addtogroup SAM3SD8B_definitions SAM3SD8B definitions + This file defines all structures and symbols for SAM3SD8B: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8B_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3SD8B specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3SD8B Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3SD8B Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3SD8B Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3SD8B Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3SD8B Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3SD8B Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3SD8B Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3SD8B UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3SD8B UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3SD8B Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3SD8B Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 14, /**< 14 SAM3SD8B USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3SD8B USART 1 (USART1) */ + HSMCI_IRQn = 18, /**< 18 SAM3SD8B Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3SD8B Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3SD8B Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3SD8B Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3SD8B Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3SD8B Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3SD8B Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3SD8B Timer/Counter 2 (TC2) */ + ADC_IRQn = 29, /**< 29 SAM3SD8B Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3SD8B Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3SD8B Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3SD8B CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3SD8B Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3SD8B USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pvReserved13; + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pvReserved16; + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3SD8B core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3SD8B does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3SD8B uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3sd8.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8B_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8B_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8B_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8B_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8B_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3sd8b.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x40000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (1024u) +#define IFLASH0_NB_OF_LOCK_BITS (16u) +#define IFLASH1_SIZE (0x40000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (1024u) +#define IFLASH1_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0x10000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) + +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x299B0A60UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (10UL) +#define NB_CH_DAC (2UL) +#define USB_DEVICE_MAX_EP (8UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3SD8B */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3SD8B_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/sam3sd8c.h b/zephyr/ports/asf/sam3sd8/include/sam3sd8c.h new file mode 100644 index 0000000..cfddb61 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/sam3sd8c.h @@ -0,0 +1,538 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM3SD8C_ +#define _SAM3SD8C_ + +/** \addtogroup SAM3SD8C_definitions SAM3SD8C definitions + This file defines all structures and symbols for SAM3SD8C: + - registers and bitfields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8C_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M3 System Tick Interrupt */ +/****** SAM3SD8C specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAM3SD8C Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAM3SD8C Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAM3SD8C Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAM3SD8C Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAM3SD8C Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAM3SD8C Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAM3SD8C Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 8, /**< 8 SAM3SD8C UART 0 (UART0) */ + UART1_IRQn = 9, /**< 9 SAM3SD8C UART 1 (UART1) */ + PIOA_IRQn = 11, /**< 11 SAM3SD8C Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 12, /**< 12 SAM3SD8C Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 13, /**< 13 SAM3SD8C Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 14, /**< 14 SAM3SD8C USART 0 (USART0) */ + USART1_IRQn = 15, /**< 15 SAM3SD8C USART 1 (USART1) */ + USART2_IRQn = 16, /**< 16 SAM3SD8C USART 2 (SAM3SD8 100 pins only) (USART2) */ + HSMCI_IRQn = 18, /**< 18 SAM3SD8C Multimedia Card Interface (HSMCI) */ + TWI0_IRQn = 19, /**< 19 SAM3SD8C Two Wire Interface 0 (TWI0) */ + TWI1_IRQn = 20, /**< 20 SAM3SD8C Two Wire Interface 1 (TWI1) */ + SPI_IRQn = 21, /**< 21 SAM3SD8C Serial Peripheral Interface (SPI) */ + SSC_IRQn = 22, /**< 22 SAM3SD8C Synchronous Serial Controler (SSC) */ + TC0_IRQn = 23, /**< 23 SAM3SD8C Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAM3SD8C Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAM3SD8C Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAM3SD8C Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAM3SD8C Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAM3SD8C Timer/Counter 5 (TC5) */ + ADC_IRQn = 29, /**< 29 SAM3SD8C Analog To Digital Converter (ADC) */ + DACC_IRQn = 30, /**< 30 SAM3SD8C Digital To Analog Converter (DACC) */ + PWM_IRQn = 31, /**< 31 SAM3SD8C Pulse Width Modulation (PWM) */ + CRCCU_IRQn = 32, /**< 32 SAM3SD8C CRC Calculation Unit (CRCCU) */ + ACC_IRQn = 33, /**< 33 SAM3SD8C Analog Comparator (ACC) */ + UDP_IRQn = 34, /**< 34 SAM3SD8C USB Device Port (UDP) */ + + PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pvReserved7; + void* pfnUART0_Handler; /* 8 UART 0 */ + void* pfnUART1_Handler; /* 9 UART 1 */ + void* pvReserved10; + void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 13 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 14 USART 0 */ + void* pfnUSART1_Handler; /* 15 USART 1 */ + void* pfnUSART2_Handler; /* 16 USART 2 (SAM3SD8 100 pins only) */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ + void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ + void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controler */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnADC_Handler; /* 29 Analog To Digital Converter */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ + void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUDP_Handler; /* 34 USB Device Port */ +} DeviceVectors; + +/* Cortex-M3 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void ADC_Handler ( void ); +void CRCCU_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void HSMCI_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PMC_Handler ( void ); +void PWM_Handler ( void ); +void RSTC_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TWI0_Handler ( void ); +void TWI1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UDP_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void WDT_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ + +#define __CM3_REV 0x0200 /**< SAM3SD8C core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAM3SD8C does provide a MPU */ +#define __NVIC_PRIO_BITS 4 /**< SAM3SD8C uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_sam3sd8.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAM3SD8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8C_api Peripheral Software API */ +/*@{*/ + +#include "component/acc.h" +#include "component/adc.h" +#include "component/chipid.h" +#include "component/crccu.h" +#include "component/dacc.h" +#include "component/efc.h" +#include "component/gpbr.h" +#include "component/hsmci.h" +#include "component/matrix.h" +#include "component/pdc.h" +#include "component/pio.h" +#include "component/pmc.h" +#include "component/pwm.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/rtt.h" +#include "component/smc.h" +#include "component/spi.h" +#include "component/ssc.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/twi.h" +#include "component/uart.h" +#include "component/udp.h" +#include "component/usart.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8C_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/hsmci.h" +#include "instance/ssc.h" +#include "instance/spi.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/twi0.h" +#include "instance/twi1.h" +#include "instance/pwm.h" +#include "instance/usart0.h" +#include "instance/usart1.h" +#include "instance/usart2.h" +#include "instance/udp.h" +#include "instance/adc.h" +#include "instance/dacc.h" +#include "instance/acc.h" +#include "instance/crccu.h" +#include "instance/smc.h" +#include "instance/matrix.h" +#include "instance/pmc.h" +#include "instance/uart0.h" +#include "instance/chipid.h" +#include "instance/uart1.h" +#include "instance/efc.h" +#include "instance/pioa.h" +#include "instance/piob.h" +#include "instance/pioc.h" +#include "instance/rstc.h" +#include "instance/supc.h" +#include "instance/rtt.h" +#include "instance/wdt.h" +#include "instance/rtc.h" +#include "instance/gpbr.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8C_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ +#define ID_SMC (10) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (13) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (14) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (15) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (16) /**< \brief USART 2 (SAM3SD8 100 pins only) (USART2) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ +#define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ +#define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controler (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ +#define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_UDP (34) /**< \brief USB Device Port (UDP) */ + +#define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8C_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI (0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 (0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 (0x4002C100U) /**< \brief (PDC_USART2) Base Address */ +#define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC (0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC (0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC (0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define PDC_HSMCI ((Pdc *)0x40000100U) /**< \brief (PDC_HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ +#define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ +#define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ +#define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40014000U) /**< \brief (TC1 ) Base Address */ +#define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ +#define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ +#define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ +#define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ +#define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ +#define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ +#define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ +#define PDC_USART1 ((Pdc *)0x40028100U) /**< \brief (PDC_USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ +#define PDC_USART2 ((Pdc *)0x4002C100U) /**< \brief (PDC_USART2) Base Address */ +#define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ +#define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ +#define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ +#define DACC ((Dacc *)0x4003C000U) /**< \brief (DACC ) Base Address */ +#define PDC_DACC ((Pdc *)0x4003C100U) /**< \brief (PDC_DACC ) Base Address */ +#define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ +#define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ +#define SMC ((Smc *)0x400E0000U) /**< \brief (SMC ) Base Address */ +#define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ +#define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ +#define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ +#define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ +#define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ +/** \addtogroup SAM3SD8C_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/sam3sd8c.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ + +#define IFLASH0_SIZE (0x40000u) +#define IFLASH0_PAGE_SIZE (256u) +#define IFLASH0_LOCK_REGION_SIZE (16384u) +#define IFLASH0_NB_OF_PAGES (1024u) +#define IFLASH0_NB_OF_LOCK_BITS (16u) +#define IFLASH1_SIZE (0x40000u) +#define IFLASH1_PAGE_SIZE (256u) +#define IFLASH1_LOCK_REGION_SIZE (16384u) +#define IFLASH1_NB_OF_PAGES (1024u) +#define IFLASH1_NB_OF_LOCK_BITS (16u) +#define IRAM_SIZE (0x10000u) +#define IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) + +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#if defined IFLASH0_SIZE +#define IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) /**< Internal Flash 1 base address */ +#endif +#define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B2D03FUL) +#define CHIP_CIDR (0x29AB0A60UL) +#define CHIP_EXID (0x0UL) +#define NB_CH_ADC (15UL) +#define NB_CH_DAC (2UL) +#define USB_DEVICE_MAX_EP (8UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAM3SD8C */ +/* ************************************************************************** */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (64000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Write Wait State */ +#define CHIP_FLASH_WRITE_WAIT_STATE (6U) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.65V) */ +#define CHIP_FREQ_FWS_0 (21000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (35000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (64000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ + +/* HYSTeresis levels: please refer to Electrical Characteristics */ +#define ACC_ACR_HYST_50MV_MAX (0x01UL) +#define ACC_ACR_HYST_90MV_MAX (0x11UL) + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAM3SD8C_ */ diff --git a/zephyr/ports/asf/sam3sd8/include/system_sam3sd8.h b/zephyr/ports/asf/sam3sd8/include/system_sam3sd8.h new file mode 100644 index 0000000..5fda208 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/include/system_sam3sd8.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) %copyright_year%, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAM3SD8_H_INCLUDED +#define SYSTEM_SAM3SD8_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAM3SD8_H_INCLUDED */ diff --git a/zephyr/ports/asf/sam3sd8/keil/Flash/ATSAM3S_512.FLM b/zephyr/ports/asf/sam3sd8/keil/Flash/ATSAM3S_512.FLM new file mode 100644 index 0000000000000000000000000000000000000000..509997f061adb63047dadd049cfd184b176bfe00 GIT binary patch literal 13192 zcmeHNYiwIbc0O}2NzsyQNtB;!hq<=stZd6NDN(ZQ$cZSDk{FQ^Bg&TID4{8ml4wgL z!-s4K&J#{Hi`}-nKpLcrO<=T}?PGtmKiUFCyM+;S(QMHcNs$x)%jJ5 z9O_EHa(PF~&pr`{6?A-R?9k#e8O2Ghch5&hr;bGemtI+8o%h$i+0ydy(a6tzit^1C z+b2hAeAaPC_D?y_C_YoTdVkLq-4~07JZoLkwu2tc)9%quK72Iz%%ykM{u!2kc!<5x zeq{XFj)#rgbnM?hYM*Kyu?3edy}foD{I}P}T3+s;4~60VzKw_8x@&A~_pUJt#^Sea zyT(MvX|a>&V!K8cWn}OXA~2r_#0C?_kZ<71xG}MwDz7Q#|4Pdn!ok-bDV54E*D)~4ghz}_Wv=TT?3{h+f;xJ0Le$k9w9YN->L4?(3uw4;s$ zp=erYZ6vZvn<6NQ_C^BHPKC1YE`<@SlQ_S(VoAO>0VGW<66Ag3=_HVG8SdPfg0MSrCG|zTC z+Hs~scRt=8*=xpTxS4DcPuGc)mfT34WU3qJ^-MF7NoVV%$-PW?v`#P;iAI}AMCa;+ zNyO^0I$C#i3?X~GnZeF7d8|%0-DP5+PHZsJN;KZgkVZfb*2$I;5JL|kXg=g4=Tq23 zh$iaP#g3;s7BI?5lcdloHm390j>FZ!LX`v2AE}4kQNtp=Km;LD8>@_Vxbd+I$yU8*@ zv|^XdDmT2)*X)+BL^%tD)@2hUx}w-@e_bJF&l^gfd3iR->#-mK*eI$IaIl{sPUQ2Xs)B+G_ysQ)P>#UwCZKTsDNV~Di zwUb(?MYL!wy3^*gI~~pzXS;LPe=qC&!m>{7i^@91y|Nf}t;_*pybqOOzlATNeI3%u*kElcnl!o8VV4{sDJ*U9xRjJzq_l>)}OD%o!{ z7A~dArsB7S{v*xxoDg?)a+eW_0=sxY=smXt9s4z1jv!&to#@hpVG4tA2Qryb1A!+H z77Vgyl zLqHHqgEJso+RSEr=(CI6XO+jLlko z8WtX$um~QL5RXO!7NxgF8Mi2Xvb$Jt+QPm1@9JB+8zk5F(4AjOo==RM5g5_`ZmXc5 zTpvSlRR5{uXl9V&!D({+3+Q9|FWK0%tsavhayc}uCn`-xRB$husESBNqADJ1CNpOF zyDrg*gu;s!9=G@v6Q2!Q_%;1aJ3Dcp?!+*;z6K|5NXdn`X-V(7W6t?P-0WHJ`BYGx zvw$~(PcH&}6 z*XanK2L=e1A9gAEpw>G2qEAtO2i025pTF#nxPE~i`>_yzAncKRu0o=#%69l5d=@pA z;$8j5Ll{Udy?zB?D}yWfG{B#-P%>G{maFR(>Z*!(T+m~`uZe#Y_VamVj!p47`UIOZ z74O`mI3O;rluFe37YNoz;L>CNpo#Blc6kH@*K$R6jIHnqJdE1hZzuYFPZvM16s*l2 zDlE>2^bu5REPs5Dwg&B6Hu14$=kuqO+K>kpv{{oQ%Ei+D9zajmjq>x9TdpGK-<2LU zd-H^Ns>ny491UHRlTMv4;;=43`yyv9b-oJpH8#xU8>mgW`k->;o`fhacu)Y7z>$P6{@G3c*)7|e8|8wdPyuba~9%E_mOyJD?Q4L0TRzPGs33E zAc^EX45{KLacK)Dz@~;sq_)uGQel|H@>Yh_I87qm%t%DX+0+P$Ofw^BGR~05HZvwo zMu5ahGb1q>m$t@9tTuCk7AHtzt(h}vaY7_=&78#i`3QR!CUJQSCvI{kNNkuKLr4y@!A`wfi2a5X!>Yfpm`{2K zvELFC(LiD<84pZ`lZnX1urV++EZ;@24~n)6;kkr?x!HMsW_o6JVaC8PcFoQNry_AC zcZ3(`M-WT{6V(aWH_QlDL>G|30Y)%aE+C0`#6aHfPK1N=vvbLr^D+L3B8fe+<5*zP z7#c30Ft=Ur{PX_<`OWD+VCRIt96K7uc`YYLM73!~( z@iK*5Yk#_sFIOa0zP<%2l@c!Wm2BDLnV*U!BZtaq1R-4ku#qYbW2u7qiz+#=O8+fF}wol?xMbVC%VZXTzn;s3oXf8i&XubhcpAN4&OM(k_nF^Hp^{oJ_f_-NayHYqnayYM zgxQL?q7Qy--N@!E<+FHg=bttg@zho@L-KjAv4~7Ch<-EKn9XObfz=FV zz}Xs(R54vXhc~rs>1v^L<}ozCXgmoPC)!B`@aSc>G+>(xwl z3okMgTnbb+vg`8Y_q=g3Wc^s1V+qXM)MDWn`Y&v(B$rEttL5xg@6x3ebL<%;|NrRN z+2H@(v9otPcHVYZgN00%+Ys*%*abr6bO{>+Pi-=_yj;SIwS}$V2_UNw&N&4m3v2ZC z0(KEodn1)@lqy!2^Dt1Rek`C$Y8h>%B-?zU0{yg^kRY#F47p$O{-_G?Z(OmLdwE^+ z8V*@BwfFJ<3!cIJFIw0RR~%uoaG&+F!rX(If&Vy?a{MO2eE!=SM^vq-KD$6+dpHiI zzw9IXrHYa}00PUYatDgv!AYx%;(Zwe1vBrBedgZ3RgV2`lzVeO(FY9ybbJ literal 0 HcmV?d00001 diff --git a/zephyr/ports/asf/sam3sd8/keil/Flash/ATSAM3S_GPNVM.FLM b/zephyr/ports/asf/sam3sd8/keil/Flash/ATSAM3S_GPNVM.FLM new file mode 100644 index 0000000000000000000000000000000000000000..fd598909edaff46e5a538524c2ce5b6317be11e8 GIT binary patch literal 13980 zcmeHOeQaCTbwBq#lA6Iwlh}?dlM-bsjvSMsD2b*%7*Up#LLzLHcFEeU0h$Hf))hg!w%Hb7`(ycI=mG>Sy0yVJctwI?NLplA{wTUEUG~og zq^S2h_r1$U$}Z9Y%PCDUK-U+(fW@afLj^@twK-mGl?$Ckga{uX4k9@|)Vurv5oNPM%b_bMILmYbLD(LFWa zf4DA|i{my9WAnaXuxnqC!c+0rZ2N+u?Tpw<^iYdN56LLwBSdH}5t)%60P+FqP+@b;e84rYEz)4yWJwO zaK~N5Eppk=G~Lj(}-?E1v;$wemtez zZb&fL&2$FtXdy1#d!adcU}z7~Ck&9tqiBIvq9Y1vY1!M-3e`v3q?_g47ZTGd^+on6uw?+>bu{qsHHi%~|;G!u<9 zGNcla!xq_80^;Z$2$~<`k;hZSK#0aH>SEi2Z3}4SxIt3r1S?bZq87rAU8qB0B4(gO zlMLw2;nn~;=RA6B$|5j2y&rrYN;3=)#Sh34YIG^l0|v@nJ$q1U;&G8+kbyaaMs)F@ z98L3wFq#$)$+5l|keakTy%2m*A$SEfK{)-e0kXi70TMl;B-!Sp3h8ZQG-;v^MwSi4 z;G_(M=_>)4H>{>52tyeL*i4oIqE)*r*0|t_zHT>tCCZr~YF#owqRWcS`Zp9}Sl(3f z%*(Svo{t3yKu1xvfP?**ft+t022wJR?gQ*sSs_G~K{_ zvS>*y%>rV)7nxyx3uk;0dA<&3K0kyjKI4y?co#}eE67hEhdQ6Urv0`c9$B2;Mh+r} zIzM$y{~U8H8{I%y?hjGo2^-1Q+}F1>wvj5Y&m{ULC^S3e37-nzbB`xn*evEYvZY>6 zpwI7lc%+)!$av292OhzXBH^=37t7gFd1*6MTC3)L{-w<;o_MKnDVwg8m*k`U(30_b zPhIGfr`eFLshTh6*7DhmXQPl`Bb#Os%Ik$vg>1r^UQd;{tcgm(@eefV;%Ig&m(J3Q zN8IzUPOfXD^^pFiaJ@j{DRP57o!ZQj>u*5U7@fOP1bU71p3exzLzxnFl=Yr#!d-p> zxI~^|B%WH!O6-fmJ)12{@Hye$N^L|oiFA6&T4PCY%VbYy2X~0m0Mz}+nOsS5*9gnn)tolhspfCL~ z^pdoOPe=QoDsTyg8*Il*Yafeko&Z7Qn@7mbabUCAbNLEYIv$H}RR{XX^?M{*d*Tds zJSO&fN0Vq>5%??ZHFc}J1n%GZg)5~KAW7HF>QKGJUnI+yapjY zIT*{0V#PgF=9kuNdNIp!2r45fZ(wHACjXP zL5hcCZl6tvVp3IWF)HMv2HM@On)~dI+jp)(Zu5> zzhdAsVH4lhpSQCUw^>e{Cf66>#8oM|5H~dGJ?|QQz7RJo>pede6z5UE3&Ci1m0Yiq z=+jU9(%$M;+R3f_u(_4PPKqy#&RMnI(!_**;=7J^_m~nU_n6XPbC1<3y2oZsuUjb| ziHy~m?$AX-KZ@~r)b&Rg?$?mb`Q`jr=XOzP=e4u_HVyZTy*QxK6*|g$gVUPlb}9LB z&2!kI04)9)N^>TE^prp9`YpQu=R*92ut)Q`3W<&?>*3Aw+sL^Tujp5&(5PH`<1)ar z46f$W0PhC)Xfj#Kma7{T>Zpo%T+sb5Y2sgm{bF9JV^zHOewo!76}xV#sG;JAn)qGK zKC+R@Uk+=1Dv#)fAybGq0U+}*!9-#08Zzhb%>wnj#5Vc z!2k(1!~>2~PP*o!_9t;3`MVmyZxFsCWr&_b*)S(RuDNj2z%Q=g9FdeGDCgYE+rK$I zX;}K?#}`d;?8Vq-HkuWu%6a91|Q4NPlE~qm93^KA$~x>cRJB`!`vHy&}YP zIs$o&f?N4pvxhelh~TU1-w_Vs=yV)#bm|VrosQ0Gl*qg|5N zkWBC3yHAo52El0PyFi3=M^d@%hT57ROk!(w>MJ0w2RUlP*b8 zO+Ayia-Dh(_;Mpj#kS6(MXKpy5?>cYJ7&Qh+ByVEKDghG9J2)X$HAo`0gC3U^ zPLo*K$&fY9kVrQ&5|bmWYKTOpkr6f+_mapqGR6%?h{S3mBQYMAx<*K>HFClxCro0! zkuz>`MoHuvIf=Q8QT8lC;?fRI+~ACn*fcm8e`7qrAda}_Eh2g`!c+vkU{NP$!ZArk zU`qxWV`(fjWesgPSjrY}!5C$=k+LO^PRWtzoR9Tm6g*y|_)R~yYm|P|htCNf*dw6? zTMzhr5g$GzJ}-DU*OC2!L6Cn#uzg=W!xv)tZ?YQCv11Yrix+6DGcPweRbQ!mT*8!>{JG9g7$Qm8O8}aji_=U4} zGzNTgg66s;WZ$S$KW}19;Lg>AG>I?OaGm(~9hGeK!3~a$O6X(q0$GGSZ+<#FJE52; zS$+^D>wB@C`8oyb`0d&UH@*v;&GDA&!X56fQSw2A^)b$u5x%)8{2u{7T!;TN;A9=n zU64lR$Z-7+QT`Y?XyPCdUx)aem-&2bQvP>n8u4#i%HIwRo$IZTH-mqDrEF>=ld7bQ z!C)NI`zqP(3iVlJyqe;+(U&gd%N0qLFTzu%hx6pch8es6TaJG&5%dY??p#lo>s@5MwUF@FZ=#H4p75f6nU-q{)O zBO{?9Z(=SqJsO%Fos5onXCn^`d3nno@;<>8w537tey+wK|H&Ca>@sM6?mesTA3e<1KY@zE9d%_W~vqQ zi9L~&3v!>KyilzatG53#X5lt*b^XZLhCcA?doenRBDx292`HRIx&&g5qKO7{n@&Yp!Q5jo! zP}p2eu9OOom$N(lOP5xS)@Lv^{zqHS3jZ&+p8ez2^V+@^E@ZM?j`9kERbsT9E@9!| z?oFmvR!aD_#l%+e`jk}&k2?ipB-ZE~1*|eg?afrWUaDAK$wNVz`Y@3ysTGu!k}UIu z3hJkgK?(A@$&l-Bz?`>S@cPFYdxMYXH_zqgOqyC7c|8Zu!~9=2u^!IYHf3U)*4|^R z@yx*HCgrgDO8zsbRJ(P9rfhbYa@ZoJzw9IXrIM1n4FtBUlFxq*%j~q76fX!|!OZ%~QEVsdteF&V61aky^_O0vdJv>sWH$0{&9mXlf6hiURNeopmc|GSVF2|3<`6M#;g-ZX~N90jT xKvdx80b|V6(jgxnAZnP^Z(jsW)nRr3a{SJ&lH&ai2z6u{9zg#pA(Tq)zW|{v4sHMd literal 0 HcmV?d00001 diff --git a/zephyr/ports/asf/sam3sd8/svd/ATSAM3S8B.svd b/zephyr/ports/asf/sam3sd8/svd/ATSAM3S8B.svd new file mode 100644 index 0000000..7d1cbbd --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/svd/ATSAM3S8B.svd @@ -0,0 +1,51033 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S8B + SAM3SD8 + 0 + Atmel ATSAM3S8B Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449H + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + 11 + 1 + read-write + + + WRPROOF + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SDCard Single Block + 0x0 + + + MULTIPLE + MMC/SDCard Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + MULTIPLE + MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. + 0x0 + + + BYTE + SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x4 + + + BLOCK + SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x5 + + + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078J + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Transmit Clock only during data transfers + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Transmit Clock enabled only if TF Low + 0x1 + + + TRANSFER + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. + 0x0 + + + RECEIVE + Receive start + 0x1 + + + RF_LOW + Detection of a low level on TF signal + 0x2 + + + RF_HIGH + Detection of a high level on TF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + RF_RISING + Detection of a rising edge on TF signal + 0x5 + + + RF_LEVEL + Detection of any level change on TF signal + 0x6 + + + RF_EDGE + Detection of any edge on TF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088R + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protection Enable + 0 + 1 + read-write + + + WPKEY + Write Protection Key Password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082Q + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + + + TWI0 + 6212L + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212L + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343H + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489I + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + AUTOCAL + Automatic Calibration of ADC + 3 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + LOWRES + Resolution + 4 + 1 + read-write + + + BITS_12 + 12-bit resolution + 0 + + + BITS_10 + 10-bit resolution + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit + 0 + + + ON + Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. + 1 + + + + + + + SEQR1 + Channel Sequence Register 1 + 0x00000008 + 32 + read-write + 0x00000000 + + + USCH1 + User Sequence Number 1 + 0 + 3 + read-write + + + USCH2 + User Sequence Number 2 + 4 + 3 + read-write + + + USCH3 + User Sequence Number 3 + 8 + 3 + read-write + + + USCH4 + User Sequence Number 4 + 12 + 3 + read-write + + + USCH5 + User Sequence Number 5 + 16 + 3 + read-write + + + USCH6 + User Sequence Number 6 + 20 + 3 + read-write + + + USCH7 + User Sequence Number 7 + 24 + 3 + read-write + + + USCH8 + User Sequence Number 8 + 28 + 3 + read-write + + + + + SEQR2 + Channel Sequence Register 2 + 0x0000000C + 32 + read-write + 0x00000000 + + + USCH9 + User Sequence Number 9 + 0 + 3 + read-write + + + USCH10 + User Sequence Number 10 + 4 + 3 + read-write + + + USCH11 + User Sequence Number 11 + 8 + 3 + read-write + + + USCH12 + User Sequence Number 12 + 12 + 3 + read-write + + + USCH13 + User Sequence Number 13 + 16 + 3 + read-write + + + USCH14 + User Sequence Number 14 + 20 + 3 + read-write + + + USCH15 + User Sequence Number 15 + 24 + 3 + read-write + + + USCH16 + User Sequence Number 16 + 28 + 3 + read-write + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + CMPFILTER + Compare Event Filtering + 12 + 2 + read-write + + + TAG + TAG of ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461F + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116D + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID2 + Peripheral Clock 2 Enable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Enable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Enable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Enable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Enable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Enable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Enable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID2 + Peripheral Clock 2 Disable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Disable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Disable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Disable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Disable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Disable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Disable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID2 + Peripheral Clock 2 Status + 2 + 1 + read-only + + + PID3 + Peripheral Clock 3 Status + 3 + 1 + read-only + + + PID4 + Peripheral Clock 4 Status + 4 + 1 + read-only + + + PID5 + Peripheral Clock 5 Status + 5 + 1 + read-only + + + PID6 + Peripheral Clock 6 Status + 6 + 1 + read-only + + + PID7 + Peripheral Clock 7 Status + 7 + 1 + read-only + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID16 + Peripheral Clock 16 Status + 16 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000001 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Password + 16 + 8 + read-write + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-write + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-write + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-write + + + RCMEAS + RC Oscillator Frequency Measure (write-only) + 20 + 1 + read-write + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Startup Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Startup Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Startup Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Startup Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Startup Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Startup Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Startup Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Startup Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Startup Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Startup Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Startup Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Startup Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Startup Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Startup Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Startup Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Startup Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Startup Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Startup Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Startup Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Startup Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Startup Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Startup Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Startup Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Startup Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Startup Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Startup Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Startup Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Startup Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Startup Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Startup Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Startup Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Startup Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Startup Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Startup Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 Mhz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 Mhz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 Mhz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 Mhz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 Mhz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 Mhz + 23 + 1 + read-write + + + + + + + UART0 + 6418E + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417K + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48K bytes + 0x0 + + + 1K + 1K bytes + 0x1 + + + 2K + 2K bytes + 0x2 + + + 6K + 6K bytes + 0x3 + + + 24K + 24K bytes + 0x4 + + + 4K + 4K bytes + 0x5 + + + 80K + 80K bytes + 0x6 + + + 160K + 160K bytes + 0x7 + + + 8K + 8K bytes + 0x8 + + + 16K + 16K bytes + 0x9 + + + 32K + 32K bytes + 0xA + + + 64K + 64K bytes + 0xB + + + 128K + 128K bytes + 0xC + + + 256K + 256K bytes + 0xD + + + 96K + 96K bytes + 0xE + + + 512K + 512K bytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM4AxC + SAM4AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM4XxC + SAM4XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM4XxE + SAM4XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM4XxG + SAM4XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM4SxA + SAM4SxA Series (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM4SxB + SAM4SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + SAM4SxC + SAM4SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3NxA + SAM3NxA Series (48-pin version) + 0x93 + + + SAM3NxB + SAM3NxB Series (64-pin version) + 0x94 + + + SAM3NxC + SAM3NxC Series (100-pin version) + 0x95 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418E + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450G + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004F + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + RPR + Receive Pointer Register + 0x00000168 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x0000016C + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000178 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x0000017C + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000188 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x0000018C + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004F + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452M + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + 1_9V + 1.9 V + 0x0 + + + 2_0V + 2.0 V + 0x1 + + + 2_1V + 2.1 V + 0x2 + + + 2_2V + 2.2 V + 0x3 + + + 2_3V + 2.3 V + 0x4 + + + 2_4V + 2.4 V + 0x5 + + + 2_5V + 2.5 V + 0x6 + + + 2_6V + 2.6 V + 0x7 + + + 2_7V + 2.7 V + 0x8 + + + 2_8V + 2.8 V + 0x9 + + + 2_9V + 2.9 V + 0xA + + + 3_0V + 3.0 V + 0xB + + + 3_1V + 3.1 V + 0xC + + + 3_2V + 3.2 V + 0xD + + + 3_3V + 3.3 V + 0xE + + + 3_4V + 3.4 V + 0xF + + + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Voltage Regulator is not used + 0 + + + ONREG_USED + Voltage Regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + + + WUMR + Supply Controller Wake Up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake Up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake Up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake Up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake up of the core power supply. + 1 + + + + + LPDBCEN0 + Low power Debouncer ENable WKUP0 + 5 + 1 + read-write + + + NOT_ENABLE + the WKUP0 input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP0 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCEN1 + Low power Debouncer ENable WKUP1 + 6 + 1 + read-write + + + NOT_ENABLE + the WKUP1input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP1 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCCLR + Low power Debouncer Clear + 7 + 1 + read-write + + + NOT_ENABLE + a low power debounce event does not create an immediate clear on first half GPBR registers. + 0 + + + ENABLE + a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. + 1 + + + + + WKUPDBC + Wake Up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + LPDBC + Low Power DeBounCer Period + 16 + 3 + read-write + + + DISABLE + Disable the low power debouncer. + 0x0 + + + 2_RTCOUT0 + WKUP0/1 in its active state for at least 2 RTCOUT0 periods + 0x1 + + + 3_RTCOUT0 + WKUP0/1 in its active state for at least 3 RTCOUT0 periods + 0x2 + + + 4_RTCOUT0 + WKUP0/1 in its active state for at least 4 RTCOUT0 periods + 0x3 + + + 5_RTCOUT0 + WKUP0/1 in its active state for at least 5 RTCOUT0 periods + 0x4 + + + 6_RTCOUT0 + WKUP0/1 in its active state for at least 6 RTCOUT0 periods + 0x5 + + + 7_RTCOUT0 + WKUP0/1 in its active state for at least 7 RTCOUT0 periods + 0x6 + + + 8_RTCOUT0 + WKUP0/1 in its active state for at least 8 RTCOUT0 periods + 0x7 + + + + + + + WUIR + Supply Controller Wake Up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake Up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN1 + Wake Up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN2 + Wake Up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN3 + Wake Up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN4 + Wake Up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN5 + Wake Up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN6 + Wake Up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN7 + Wake Up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN8 + Wake Up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN9 + Wake Up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN10 + Wake Up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN11 + Wake Up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN12 + Wake Up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN13 + Wake Up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN14 + Wake Up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN15 + Wake Up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT0 + Wake Up Input Type 0 + 16 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT1 + Wake Up Input Type 1 + 17 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT2 + Wake Up Input Type 2 + 18 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT3 + Wake Up Input Type 3 + 19 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT4 + Wake Up Input Type 4 + 20 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT5 + Wake Up Input Type 5 + 21 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT6 + Wake Up Input Type 6 + 22 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT7 + Wake Up Input Type 7 + 23 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT8 + Wake Up Input Type 8 + 24 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT9 + Wake Up Input Type 9 + 25 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT10 + Wake Up Input Type 10 + 26 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT11 + Wake Up Input Type 11 + 27 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT12 + Wake Up Input Type 12 + 28 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT13 + Wake Up Input Type 13 + 29 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT14 + Wake Up Input Type 14 + 30 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT15 + Wake Up Input Type 15 + 31 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000800 + + + WKUPS + WKUP Wake Up Status + 1 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake Up Status + 2 + 1 + read-only + + + NO + no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + LPDBCS0 + Low Power Debouncer Wake Up Status on WKUP0 + 13 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 1 + + + + + LPDBCS1 + Low Power Debouncer Wake Up Status on WKUP1 + 14 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + + + + + RTT + 6081F + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + RTTDIS + Real-time Timer Disable + 20 + 1 + read-write + + + RTC1HZ + Real-Time Clock 1Hz Clock Selection + 24 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080B + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password + 24 + 8 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056K + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + PERSIAN + PERSIAN Calendar + 1 + 1 + read-write + + + NEGPPM + NEGative PPM Correction + 4 + 1 + read-write + + + CORRECTION + Slow Clock Correction + 8 + 7 + read-write + + + HIGHPPM + HIGH PPM Correction + 15 + 1 + read-write + + + OUT0 + RTCOUT0 Output Source Selection + 16 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + OUT1 + RTCOUT1 Output Source Selection + 20 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + THIGH + High Duration of the Output Pulse + 24 + 3 + read-write + + + H_31MS + 31.2 ms + 0x0 + + + H_16MS + 15.6 ms + 0x1 + + + H_4MS + 3.91 ms + 0x2 + + + H_976US + 976 us + 0x3 + + + H_488US + 488 us + 0x4 + + + H_122US + 122 us + 0x5 + + + H_30US + 30.5 us + 0x6 + + + H_15US + 15.2 us + 0x7 + + + + + TPERIOD + Period of the Output Pulse + 28 + 2 + read-write + + + P_1S + 1 second + 0x0 + + + P_500MS + 500 ms + 0x1 + + + P_250MS + 250 ms + 0x2 + + + P_125MS + 125 ms + 0x3 + + + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + TDERR + Time and/or Date Free Running Error + 5 + 1 + read-only + + + CORRECT + The internal free running counters are carrying valid values since the last read of RTC_SR. + 0 + + + ERR_TIMEDATE + The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + TDERRCLR + Time and/or Date Free Running Error Clear + 5 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + TDERREN + Time and/or Date Error Interrupt Enable + 5 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + TDERRDIS + Time and/or Date Error Interrupt Disable + 5 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Register + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3sd8/svd/ATSAM3S8C.svd b/zephyr/ports/asf/sam3sd8/svd/ATSAM3S8C.svd new file mode 100644 index 0000000..e825a06 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/svd/ATSAM3S8C.svd @@ -0,0 +1,68019 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3S8C + SAM3SD8 + 0 + Atmel ATSAM3S8C Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449H + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + 11 + 1 + read-write + + + WRPROOF + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SDCard Single Block + 0x0 + + + MULTIPLE + MMC/SDCard Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + MULTIPLE + MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. + 0x0 + + + BYTE + SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x4 + + + BLOCK + SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x5 + + + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078J + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Transmit Clock only during data transfers + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Transmit Clock enabled only if TF Low + 0x1 + + + TRANSFER + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. + 0x0 + + + RECEIVE + Receive start + 0x1 + + + RF_LOW + Detection of a low level on TF signal + 0x2 + + + RF_HIGH + Detection of a high level on TF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + RF_RISING + Detection of a rising edge on TF signal + 0x5 + + + RF_LEVEL + Detection of any level change on TF signal + 0x6 + + + RF_EDGE + Detection of any edge on TF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088R + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protection Enable + 0 + 1 + read-write + + + WPKEY + Write Protection Key Password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082Q + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + + + TC1 + 6082Q + Timer Counter 1 + TC + TC1_ + 0x40014000 + + 0 + 0x4000 + registers + + + TC3 + 26 + + + TC4 + 27 + + + TC5 + 28 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + + + TWI0 + 6212L + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212L + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343H + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART2 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 2 + USART + USART2_ + 0x4002C000 + + 0 + 0x4000 + registers + + + USART2 + 16 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489I + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + AUTOCAL + Automatic Calibration of ADC + 3 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + LOWRES + Resolution + 4 + 1 + read-write + + + BITS_12 + 12-bit resolution + 0 + + + BITS_10 + 10-bit resolution + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit + 0 + + + ON + Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. + 1 + + + + + + + SEQR1 + Channel Sequence Register 1 + 0x00000008 + 32 + read-write + 0x00000000 + + + USCH1 + User Sequence Number 1 + 0 + 3 + read-write + + + USCH2 + User Sequence Number 2 + 4 + 3 + read-write + + + USCH3 + User Sequence Number 3 + 8 + 3 + read-write + + + USCH4 + User Sequence Number 4 + 12 + 3 + read-write + + + USCH5 + User Sequence Number 5 + 16 + 3 + read-write + + + USCH6 + User Sequence Number 6 + 20 + 3 + read-write + + + USCH7 + User Sequence Number 7 + 24 + 3 + read-write + + + USCH8 + User Sequence Number 8 + 28 + 3 + read-write + + + + + SEQR2 + Channel Sequence Register 2 + 0x0000000C + 32 + read-write + 0x00000000 + + + USCH9 + User Sequence Number 9 + 0 + 3 + read-write + + + USCH10 + User Sequence Number 10 + 4 + 3 + read-write + + + USCH11 + User Sequence Number 11 + 8 + 3 + read-write + + + USCH12 + User Sequence Number 12 + 12 + 3 + read-write + + + USCH13 + User Sequence Number 13 + 16 + 3 + read-write + + + USCH14 + User Sequence Number 14 + 20 + 3 + read-write + + + USCH15 + User Sequence Number 15 + 24 + 3 + read-write + + + USCH16 + User Sequence Number 16 + 28 + 3 + read-write + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + CMPFILTER + Compare Event Filtering + 12 + 2 + read-write + + + TAG + TAG of ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461F + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + SMC + 6498E + Static Memory Controller + EBI + SMC_ + 0x400E0000 + + 0 + 0x200 + registers + + + + SETUP0 + SMC Setup Register (CS_number = 0) + 0x00000000 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE0 + SMC Pulse Register (CS_number = 0) + 0x00000004 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE0 + SMC Cycle Register (CS_number = 0) + 0x00000008 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE0 + SMC Mode Register (CS_number = 0) + 0x0000000C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP1 + SMC Setup Register (CS_number = 1) + 0x00000010 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE1 + SMC Pulse Register (CS_number = 1) + 0x00000014 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE1 + SMC Cycle Register (CS_number = 1) + 0x00000018 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE1 + SMC Mode Register (CS_number = 1) + 0x0000001C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP2 + SMC Setup Register (CS_number = 2) + 0x00000020 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE2 + SMC Pulse Register (CS_number = 2) + 0x00000024 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE2 + SMC Cycle Register (CS_number = 2) + 0x00000028 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE2 + SMC Mode Register (CS_number = 2) + 0x0000002C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP3 + SMC Setup Register (CS_number = 3) + 0x00000030 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE3 + SMC Pulse Register (CS_number = 3) + 0x00000034 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE3 + SMC Cycle Register (CS_number = 3) + 0x00000038 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE3 + SMC Mode Register (CS_number = 3) + 0x0000003C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + OCMS + SMC OCMS MODE Register + 0x00000080 + 32 + read-write + 0x00000000 + + + SMSE + Static Memory Controller Scrambling Enable + 0 + 1 + read-write + + + CS0SE + Chip Select (x = 0 to 3) Scrambling Enable + 16 + 1 + read-write + + + CS1SE + Chip Select (x = 0 to 3) Scrambling Enable + 17 + 1 + read-write + + + CS2SE + Chip Select (x = 0 to 3) Scrambling Enable + 18 + 1 + read-write + + + CS3SE + Chip Select (x = 0 to 3) Scrambling Enable + 19 + 1 + read-write + + + + + KEY1 + SMC OCMS KEY1 Register + 0x00000084 + 32 + write-only + 0x00000000 + + + KEY1 + Off Chip Memory Scrambling (OCMS) Key Part 1 + 0 + 32 + write-only + + + + + KEY2 + SMC OCMS KEY2 Register + 0x00000088 + 32 + write-only + 0x00000000 + + + KEY2 + Off Chip Memory Scrambling (OCMS) Key Part 2 + 0 + 32 + write-only + + + + + WPMR + SMC Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + SMC Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Enable + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116D + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID2 + Peripheral Clock 2 Enable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Enable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Enable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Enable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Enable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Enable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Enable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID2 + Peripheral Clock 2 Disable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Disable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Disable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Disable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Disable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Disable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Disable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID2 + Peripheral Clock 2 Status + 2 + 1 + read-only + + + PID3 + Peripheral Clock 3 Status + 3 + 1 + read-only + + + PID4 + Peripheral Clock 4 Status + 4 + 1 + read-only + + + PID5 + Peripheral Clock 5 Status + 5 + 1 + read-only + + + PID6 + Peripheral Clock 6 Status + 6 + 1 + read-only + + + PID7 + Peripheral Clock 7 Status + 7 + 1 + read-only + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID16 + Peripheral Clock 16 Status + 16 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000001 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Password + 16 + 8 + read-write + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-write + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-write + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-write + + + RCMEAS + RC Oscillator Frequency Measure (write-only) + 20 + 1 + read-write + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Startup Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Startup Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Startup Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Startup Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Startup Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Startup Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Startup Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Startup Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Startup Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Startup Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Startup Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Startup Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Startup Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Startup Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Startup Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Startup Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Startup Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Startup Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Startup Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Startup Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Startup Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Startup Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Startup Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Startup Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Startup Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Startup Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Startup Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Startup Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Startup Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Startup Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Startup Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Startup Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Startup Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Startup Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 Mhz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 Mhz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 Mhz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 Mhz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 Mhz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 Mhz + 23 + 1 + read-write + + + + + + + UART0 + 6418E + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417K + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48K bytes + 0x0 + + + 1K + 1K bytes + 0x1 + + + 2K + 2K bytes + 0x2 + + + 6K + 6K bytes + 0x3 + + + 24K + 24K bytes + 0x4 + + + 4K + 4K bytes + 0x5 + + + 80K + 80K bytes + 0x6 + + + 160K + 160K bytes + 0x7 + + + 8K + 8K bytes + 0x8 + + + 16K + 16K bytes + 0x9 + + + 32K + 32K bytes + 0xA + + + 64K + 64K bytes + 0xB + + + 128K + 128K bytes + 0xC + + + 256K + 256K bytes + 0xD + + + 96K + 96K bytes + 0xE + + + 512K + 512K bytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM4AxC + SAM4AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM4XxC + SAM4XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM4XxE + SAM4XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM4XxG + SAM4XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM4SxA + SAM4SxA Series (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM4SxB + SAM4SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + SAM4SxC + SAM4SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3NxA + SAM3NxA Series (48-pin version) + 0x93 + + + SAM3NxB + SAM3NxB Series (64-pin version) + 0x94 + + + SAM3NxC + SAM3NxC Series (100-pin version) + 0x95 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418E + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450G + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004F + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + RPR + Receive Pointer Register + 0x00000168 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x0000016C + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000178 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x0000017C + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000188 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x0000018C + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004F + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + + + PIOC + 11004F + Parallel Input/Output Controller C + PIO + PIOC_ + 0x400E1200 + + 0 + 0x200 + registers + + + PIOC + 13 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452M + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + 1_9V + 1.9 V + 0x0 + + + 2_0V + 2.0 V + 0x1 + + + 2_1V + 2.1 V + 0x2 + + + 2_2V + 2.2 V + 0x3 + + + 2_3V + 2.3 V + 0x4 + + + 2_4V + 2.4 V + 0x5 + + + 2_5V + 2.5 V + 0x6 + + + 2_6V + 2.6 V + 0x7 + + + 2_7V + 2.7 V + 0x8 + + + 2_8V + 2.8 V + 0x9 + + + 2_9V + 2.9 V + 0xA + + + 3_0V + 3.0 V + 0xB + + + 3_1V + 3.1 V + 0xC + + + 3_2V + 3.2 V + 0xD + + + 3_3V + 3.3 V + 0xE + + + 3_4V + 3.4 V + 0xF + + + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Voltage Regulator is not used + 0 + + + ONREG_USED + Voltage Regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + + + WUMR + Supply Controller Wake Up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake Up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake Up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake Up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake up of the core power supply. + 1 + + + + + LPDBCEN0 + Low power Debouncer ENable WKUP0 + 5 + 1 + read-write + + + NOT_ENABLE + the WKUP0 input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP0 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCEN1 + Low power Debouncer ENable WKUP1 + 6 + 1 + read-write + + + NOT_ENABLE + the WKUP1input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP1 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCCLR + Low power Debouncer Clear + 7 + 1 + read-write + + + NOT_ENABLE + a low power debounce event does not create an immediate clear on first half GPBR registers. + 0 + + + ENABLE + a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. + 1 + + + + + WKUPDBC + Wake Up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + LPDBC + Low Power DeBounCer Period + 16 + 3 + read-write + + + DISABLE + Disable the low power debouncer. + 0x0 + + + 2_RTCOUT0 + WKUP0/1 in its active state for at least 2 RTCOUT0 periods + 0x1 + + + 3_RTCOUT0 + WKUP0/1 in its active state for at least 3 RTCOUT0 periods + 0x2 + + + 4_RTCOUT0 + WKUP0/1 in its active state for at least 4 RTCOUT0 periods + 0x3 + + + 5_RTCOUT0 + WKUP0/1 in its active state for at least 5 RTCOUT0 periods + 0x4 + + + 6_RTCOUT0 + WKUP0/1 in its active state for at least 6 RTCOUT0 periods + 0x5 + + + 7_RTCOUT0 + WKUP0/1 in its active state for at least 7 RTCOUT0 periods + 0x6 + + + 8_RTCOUT0 + WKUP0/1 in its active state for at least 8 RTCOUT0 periods + 0x7 + + + + + + + WUIR + Supply Controller Wake Up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake Up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN1 + Wake Up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN2 + Wake Up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN3 + Wake Up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN4 + Wake Up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN5 + Wake Up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN6 + Wake Up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN7 + Wake Up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN8 + Wake Up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN9 + Wake Up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN10 + Wake Up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN11 + Wake Up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN12 + Wake Up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN13 + Wake Up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN14 + Wake Up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN15 + Wake Up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT0 + Wake Up Input Type 0 + 16 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT1 + Wake Up Input Type 1 + 17 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT2 + Wake Up Input Type 2 + 18 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT3 + Wake Up Input Type 3 + 19 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT4 + Wake Up Input Type 4 + 20 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT5 + Wake Up Input Type 5 + 21 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT6 + Wake Up Input Type 6 + 22 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT7 + Wake Up Input Type 7 + 23 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT8 + Wake Up Input Type 8 + 24 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT9 + Wake Up Input Type 9 + 25 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT10 + Wake Up Input Type 10 + 26 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT11 + Wake Up Input Type 11 + 27 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT12 + Wake Up Input Type 12 + 28 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT13 + Wake Up Input Type 13 + 29 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT14 + Wake Up Input Type 14 + 30 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT15 + Wake Up Input Type 15 + 31 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000800 + + + WKUPS + WKUP Wake Up Status + 1 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake Up Status + 2 + 1 + read-only + + + NO + no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + LPDBCS0 + Low Power Debouncer Wake Up Status on WKUP0 + 13 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 1 + + + + + LPDBCS1 + Low Power Debouncer Wake Up Status on WKUP1 + 14 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + + + + + RTT + 6081F + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + RTTDIS + Real-time Timer Disable + 20 + 1 + read-write + + + RTC1HZ + Real-Time Clock 1Hz Clock Selection + 24 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080B + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password + 24 + 8 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056K + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + PERSIAN + PERSIAN Calendar + 1 + 1 + read-write + + + NEGPPM + NEGative PPM Correction + 4 + 1 + read-write + + + CORRECTION + Slow Clock Correction + 8 + 7 + read-write + + + HIGHPPM + HIGH PPM Correction + 15 + 1 + read-write + + + OUT0 + RTCOUT0 Output Source Selection + 16 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + OUT1 + RTCOUT1 Output Source Selection + 20 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + THIGH + High Duration of the Output Pulse + 24 + 3 + read-write + + + H_31MS + 31.2 ms + 0x0 + + + H_16MS + 15.6 ms + 0x1 + + + H_4MS + 3.91 ms + 0x2 + + + H_976US + 976 us + 0x3 + + + H_488US + 488 us + 0x4 + + + H_122US + 122 us + 0x5 + + + H_30US + 30.5 us + 0x6 + + + H_15US + 15.2 us + 0x7 + + + + + TPERIOD + Period of the Output Pulse + 28 + 2 + read-write + + + P_1S + 1 second + 0x0 + + + P_500MS + 500 ms + 0x1 + + + P_250MS + 250 ms + 0x2 + + + P_125MS + 125 ms + 0x3 + + + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + TDERR + Time and/or Date Free Running Error + 5 + 1 + read-only + + + CORRECT + The internal free running counters are carrying valid values since the last read of RTC_SR. + 0 + + + ERR_TIMEDATE + The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + TDERRCLR + Time and/or Date Free Running Error Clear + 5 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + TDERREN + Time and/or Date Error Interrupt Enable + 5 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + TDERRDIS + Time and/or Date Error Interrupt Disable + 5 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Register + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8B.svd b/zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8B.svd new file mode 100644 index 0000000..9984b15 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8B.svd @@ -0,0 +1,51033 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3SD8B + SAM3SD8 + 0 + Atmel ATSAM3SD8B Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449H + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + 11 + 1 + read-write + + + WRPROOF + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SDCard Single Block + 0x0 + + + MULTIPLE + MMC/SDCard Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + MULTIPLE + MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. + 0x0 + + + BYTE + SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x4 + + + BLOCK + SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x5 + + + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078J + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Transmit Clock only during data transfers + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Transmit Clock enabled only if TF Low + 0x1 + + + TRANSFER + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. + 0x0 + + + RECEIVE + Receive start + 0x1 + + + RF_LOW + Detection of a low level on TF signal + 0x2 + + + RF_HIGH + Detection of a high level on TF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + RF_RISING + Detection of a rising edge on TF signal + 0x5 + + + RF_LEVEL + Detection of any level change on TF signal + 0x6 + + + RF_EDGE + Detection of any edge on TF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088R + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protection Enable + 0 + 1 + read-write + + + WPKEY + Write Protection Key Password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082Q + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + + + TWI0 + 6212L + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212L + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343H + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489I + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + AUTOCAL + Automatic Calibration of ADC + 3 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + LOWRES + Resolution + 4 + 1 + read-write + + + BITS_12 + 12-bit resolution + 0 + + + BITS_10 + 10-bit resolution + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit + 0 + + + ON + Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. + 1 + + + + + + + SEQR1 + Channel Sequence Register 1 + 0x00000008 + 32 + read-write + 0x00000000 + + + USCH1 + User Sequence Number 1 + 0 + 3 + read-write + + + USCH2 + User Sequence Number 2 + 4 + 3 + read-write + + + USCH3 + User Sequence Number 3 + 8 + 3 + read-write + + + USCH4 + User Sequence Number 4 + 12 + 3 + read-write + + + USCH5 + User Sequence Number 5 + 16 + 3 + read-write + + + USCH6 + User Sequence Number 6 + 20 + 3 + read-write + + + USCH7 + User Sequence Number 7 + 24 + 3 + read-write + + + USCH8 + User Sequence Number 8 + 28 + 3 + read-write + + + + + SEQR2 + Channel Sequence Register 2 + 0x0000000C + 32 + read-write + 0x00000000 + + + USCH9 + User Sequence Number 9 + 0 + 3 + read-write + + + USCH10 + User Sequence Number 10 + 4 + 3 + read-write + + + USCH11 + User Sequence Number 11 + 8 + 3 + read-write + + + USCH12 + User Sequence Number 12 + 12 + 3 + read-write + + + USCH13 + User Sequence Number 13 + 16 + 3 + read-write + + + USCH14 + User Sequence Number 14 + 20 + 3 + read-write + + + USCH15 + User Sequence Number 15 + 24 + 3 + read-write + + + USCH16 + User Sequence Number 16 + 28 + 3 + read-write + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + CMPFILTER + Compare Event Filtering + 12 + 2 + read-write + + + TAG + TAG of ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461F + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116D + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID2 + Peripheral Clock 2 Enable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Enable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Enable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Enable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Enable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Enable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Enable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID2 + Peripheral Clock 2 Disable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Disable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Disable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Disable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Disable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Disable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Disable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID2 + Peripheral Clock 2 Status + 2 + 1 + read-only + + + PID3 + Peripheral Clock 3 Status + 3 + 1 + read-only + + + PID4 + Peripheral Clock 4 Status + 4 + 1 + read-only + + + PID5 + Peripheral Clock 5 Status + 5 + 1 + read-only + + + PID6 + Peripheral Clock 6 Status + 6 + 1 + read-only + + + PID7 + Peripheral Clock 7 Status + 7 + 1 + read-only + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID16 + Peripheral Clock 16 Status + 16 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000001 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Password + 16 + 8 + read-write + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-write + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-write + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-write + + + RCMEAS + RC Oscillator Frequency Measure (write-only) + 20 + 1 + read-write + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Startup Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Startup Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Startup Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Startup Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Startup Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Startup Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Startup Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Startup Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Startup Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Startup Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Startup Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Startup Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Startup Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Startup Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Startup Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Startup Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Startup Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Startup Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Startup Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Startup Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Startup Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Startup Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Startup Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Startup Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Startup Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Startup Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Startup Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Startup Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Startup Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Startup Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Startup Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Startup Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Startup Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Startup Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 Mhz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 Mhz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 Mhz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 Mhz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 Mhz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 Mhz + 23 + 1 + read-write + + + + + + + UART0 + 6418E + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417K + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48K bytes + 0x0 + + + 1K + 1K bytes + 0x1 + + + 2K + 2K bytes + 0x2 + + + 6K + 6K bytes + 0x3 + + + 24K + 24K bytes + 0x4 + + + 4K + 4K bytes + 0x5 + + + 80K + 80K bytes + 0x6 + + + 160K + 160K bytes + 0x7 + + + 8K + 8K bytes + 0x8 + + + 16K + 16K bytes + 0x9 + + + 32K + 32K bytes + 0xA + + + 64K + 64K bytes + 0xB + + + 128K + 128K bytes + 0xC + + + 256K + 256K bytes + 0xD + + + 96K + 96K bytes + 0xE + + + 512K + 512K bytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM4AxC + SAM4AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM4XxC + SAM4XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM4XxE + SAM4XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM4XxG + SAM4XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM4SxA + SAM4SxA Series (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM4SxB + SAM4SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + SAM4SxC + SAM4SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3NxA + SAM3NxA Series (48-pin version) + 0x93 + + + SAM3NxB + SAM3NxB Series (64-pin version) + 0x94 + + + SAM3NxC + SAM3NxC Series (100-pin version) + 0x95 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418E + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450G + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004F + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + RPR + Receive Pointer Register + 0x00000168 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x0000016C + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000178 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x0000017C + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000188 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x0000018C + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004F + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452M + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + 1_9V + 1.9 V + 0x0 + + + 2_0V + 2.0 V + 0x1 + + + 2_1V + 2.1 V + 0x2 + + + 2_2V + 2.2 V + 0x3 + + + 2_3V + 2.3 V + 0x4 + + + 2_4V + 2.4 V + 0x5 + + + 2_5V + 2.5 V + 0x6 + + + 2_6V + 2.6 V + 0x7 + + + 2_7V + 2.7 V + 0x8 + + + 2_8V + 2.8 V + 0x9 + + + 2_9V + 2.9 V + 0xA + + + 3_0V + 3.0 V + 0xB + + + 3_1V + 3.1 V + 0xC + + + 3_2V + 3.2 V + 0xD + + + 3_3V + 3.3 V + 0xE + + + 3_4V + 3.4 V + 0xF + + + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Voltage Regulator is not used + 0 + + + ONREG_USED + Voltage Regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + + + WUMR + Supply Controller Wake Up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake Up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake Up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake Up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake up of the core power supply. + 1 + + + + + LPDBCEN0 + Low power Debouncer ENable WKUP0 + 5 + 1 + read-write + + + NOT_ENABLE + the WKUP0 input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP0 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCEN1 + Low power Debouncer ENable WKUP1 + 6 + 1 + read-write + + + NOT_ENABLE + the WKUP1input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP1 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCCLR + Low power Debouncer Clear + 7 + 1 + read-write + + + NOT_ENABLE + a low power debounce event does not create an immediate clear on first half GPBR registers. + 0 + + + ENABLE + a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. + 1 + + + + + WKUPDBC + Wake Up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + LPDBC + Low Power DeBounCer Period + 16 + 3 + read-write + + + DISABLE + Disable the low power debouncer. + 0x0 + + + 2_RTCOUT0 + WKUP0/1 in its active state for at least 2 RTCOUT0 periods + 0x1 + + + 3_RTCOUT0 + WKUP0/1 in its active state for at least 3 RTCOUT0 periods + 0x2 + + + 4_RTCOUT0 + WKUP0/1 in its active state for at least 4 RTCOUT0 periods + 0x3 + + + 5_RTCOUT0 + WKUP0/1 in its active state for at least 5 RTCOUT0 periods + 0x4 + + + 6_RTCOUT0 + WKUP0/1 in its active state for at least 6 RTCOUT0 periods + 0x5 + + + 7_RTCOUT0 + WKUP0/1 in its active state for at least 7 RTCOUT0 periods + 0x6 + + + 8_RTCOUT0 + WKUP0/1 in its active state for at least 8 RTCOUT0 periods + 0x7 + + + + + + + WUIR + Supply Controller Wake Up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake Up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN1 + Wake Up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN2 + Wake Up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN3 + Wake Up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN4 + Wake Up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN5 + Wake Up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN6 + Wake Up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN7 + Wake Up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN8 + Wake Up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN9 + Wake Up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN10 + Wake Up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN11 + Wake Up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN12 + Wake Up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN13 + Wake Up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN14 + Wake Up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN15 + Wake Up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT0 + Wake Up Input Type 0 + 16 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT1 + Wake Up Input Type 1 + 17 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT2 + Wake Up Input Type 2 + 18 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT3 + Wake Up Input Type 3 + 19 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT4 + Wake Up Input Type 4 + 20 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT5 + Wake Up Input Type 5 + 21 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT6 + Wake Up Input Type 6 + 22 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT7 + Wake Up Input Type 7 + 23 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT8 + Wake Up Input Type 8 + 24 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT9 + Wake Up Input Type 9 + 25 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT10 + Wake Up Input Type 10 + 26 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT11 + Wake Up Input Type 11 + 27 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT12 + Wake Up Input Type 12 + 28 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT13 + Wake Up Input Type 13 + 29 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT14 + Wake Up Input Type 14 + 30 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT15 + Wake Up Input Type 15 + 31 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000800 + + + WKUPS + WKUP Wake Up Status + 1 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake Up Status + 2 + 1 + read-only + + + NO + no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + LPDBCS0 + Low Power Debouncer Wake Up Status on WKUP0 + 13 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 1 + + + + + LPDBCS1 + Low Power Debouncer Wake Up Status on WKUP1 + 14 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + + + + + RTT + 6081F + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + RTTDIS + Real-time Timer Disable + 20 + 1 + read-write + + + RTC1HZ + Real-Time Clock 1Hz Clock Selection + 24 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080B + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password + 24 + 8 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056K + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + PERSIAN + PERSIAN Calendar + 1 + 1 + read-write + + + NEGPPM + NEGative PPM Correction + 4 + 1 + read-write + + + CORRECTION + Slow Clock Correction + 8 + 7 + read-write + + + HIGHPPM + HIGH PPM Correction + 15 + 1 + read-write + + + OUT0 + RTCOUT0 Output Source Selection + 16 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + OUT1 + RTCOUT1 Output Source Selection + 20 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + THIGH + High Duration of the Output Pulse + 24 + 3 + read-write + + + H_31MS + 31.2 ms + 0x0 + + + H_16MS + 15.6 ms + 0x1 + + + H_4MS + 3.91 ms + 0x2 + + + H_976US + 976 us + 0x3 + + + H_488US + 488 us + 0x4 + + + H_122US + 122 us + 0x5 + + + H_30US + 30.5 us + 0x6 + + + H_15US + 15.2 us + 0x7 + + + + + TPERIOD + Period of the Output Pulse + 28 + 2 + read-write + + + P_1S + 1 second + 0x0 + + + P_500MS + 500 ms + 0x1 + + + P_250MS + 250 ms + 0x2 + + + P_125MS + 125 ms + 0x3 + + + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + TDERR + Time and/or Date Free Running Error + 5 + 1 + read-only + + + CORRECT + The internal free running counters are carrying valid values since the last read of RTC_SR. + 0 + + + ERR_TIMEDATE + The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + TDERRCLR + Time and/or Date Free Running Error Clear + 5 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + TDERREN + Time and/or Date Error Interrupt Enable + 5 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + TDERRDIS + Time and/or Date Error Interrupt Disable + 5 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Register + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8C.svd b/zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8C.svd new file mode 100644 index 0000000..13567d5 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/svd/ATSAM3SD8C.svd @@ -0,0 +1,68019 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Atmel + ATSAM3SD8C + SAM3SD8 + 0 + Atmel ATSAM3SD8C Microcontroller + + CM3 + r2p0 + selectable + true + false + 4 + false + + 8 + 32 + + + HSMCI + 6449H + High Speed MultiMedia Card Interface + HSMCI_ + 0x40000000 + + 0 + 0x4000 + registers + + + HSMCI + 18 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + MCIEN + Multi-Media Interface Enable + 0 + 1 + write-only + + + MCIDIS + Multi-Media Interface Disable + 1 + 1 + write-only + + + PWSEN + Power Save Mode Enable + 2 + 1 + write-only + + + PWSDIS + Power Save Mode Disable + 3 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + CLKDIV + Clock Divider + 0 + 8 + read-write + + + PWSDIV + Power Saving Divider + 8 + 3 + read-write + + + RDPROOF + 11 + 1 + read-write + + + WRPROOF + 12 + 1 + read-write + + + FBYTE + Force Byte Transfer + 13 + 1 + read-write + + + PADV + Padding Value + 14 + 1 + read-write + + + PDCMODE + PDC-oriented Mode + 15 + 1 + read-write + + + + + DTOR + Data Timeout Register + 0x00000008 + 32 + read-write + 0x00000000 + + + DTOCYC + Data Timeout Cycle Number + 0 + 4 + read-write + + + DTOMUL + Data Timeout Multiplier + 4 + 3 + read-write + + + 1 + DTOCYC + 0x0 + + + 16 + DTOCYC x 16 + 0x1 + + + 128 + DTOCYC x 128 + 0x2 + + + 256 + DTOCYC x 256 + 0x3 + + + 1024 + DTOCYC x 1024 + 0x4 + + + 4096 + DTOCYC x 4096 + 0x5 + + + 65536 + DTOCYC x 65536 + 0x6 + + + 1048576 + DTOCYC x 1048576 + 0x7 + + + + + + + SDCR + SD/SDIO Card Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SDCSEL + SDCard/SDIO Slot + 0 + 2 + read-write + + + SLOTA + Slot A is selected. + 0x0 + + + SLOTB + - + 0x1 + + + SLOTC + - + 0x2 + + + SLOTD + - + 0x3 + + + + + SDCBUS + SDCard/SDIO Bus Width + 6 + 2 + read-write + + + 1 + 1 bit + 0x0 + + + 4 + 4 bit + 0x2 + + + 8 + 8 bit + 0x3 + + + + + + + ARGR + Argument Register + 0x00000010 + 32 + read-write + 0x00000000 + + + ARG + Command Argument + 0 + 32 + read-write + + + + + CMDR + Command Register + 0x00000014 + 32 + write-only + + + CMDNB + Command Number + 0 + 6 + write-only + + + RSPTYP + Response Type + 6 + 2 + write-only + + + NORESP + No response. + 0x0 + + + 48_BIT + 48-bit response. + 0x1 + + + 136_BIT + 136-bit response. + 0x2 + + + R1B + R1b response type + 0x3 + + + + + SPCMD + Special Command + 8 + 3 + write-only + + + STD + Not a special CMD. + 0x0 + + + INIT + Initialization CMD: 74 clock cycles for initialization sequence. + 0x1 + + + SYNC + Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. + 0x2 + + + CE_ATA + CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. + 0x3 + + + IT_CMD + Interrupt command: Corresponds to the Interrupt Mode (CMD40). + 0x4 + + + IT_RESP + Interrupt response: Corresponds to the Interrupt Mode (CMD40). + 0x5 + + + BOR + Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. + 0x6 + + + EBO + End Boot Operation. This command allows the host processor to terminate the boot operation mode. + 0x7 + + + + + OPDCMD + Open Drain Command + 11 + 1 + write-only + + + PUSHPULL + Push pull command. + 0 + + + OPENDRAIN + Open drain command. + 1 + + + + + MAXLAT + Max Latency for Command to Response + 12 + 1 + write-only + + + 5 + 5-cycle max latency. + 0 + + + 64 + 64-cycle max latency. + 1 + + + + + TRCMD + Transfer Command + 16 + 2 + write-only + + + NO_DATA + No data transfer + 0x0 + + + START_DATA + Start data transfer + 0x1 + + + STOP_DATA + Stop data transfer + 0x2 + + + + + TRDIR + Transfer Direction + 18 + 1 + write-only + + + WRITE + Write. + 0 + + + READ + Read. + 1 + + + + + TRTYP + Transfer Type + 19 + 3 + write-only + + + SINGLE + MMC/SDCard Single Block + 0x0 + + + MULTIPLE + MMC/SDCard Multiple Block + 0x1 + + + STREAM + MMC Stream + 0x2 + + + BYTE + SDIO Byte + 0x4 + + + BLOCK + SDIO Block + 0x5 + + + + + IOSPCMD + SDIO Special Command + 24 + 2 + write-only + + + STD + Not an SDIO Special Command + 0x0 + + + SUSPEND + SDIO Suspend Command + 0x1 + + + RESUME + SDIO Resume Command + 0x2 + + + + + ATACS + ATA with Command Completion Signal + 26 + 1 + write-only + + + NORMAL + Normal operation mode. + 0 + + + COMPLETION + This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). + 1 + + + + + BOOT_ACK + Boot Operation Acknowledge. + 27 + 1 + write-only + + + + + BLKR + Block Register + 0x00000018 + 32 + read-write + 0x00000000 + + + BCNT + MMC/SDIO Block Count - SDIO Byte Count + 0 + 16 + read-write + + + MULTIPLE + MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer. + 0x0 + + + BYTE + SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x4 + + + BLOCK + SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden. + 0x5 + + + + + BLKLEN + Data Block Length + 16 + 16 + read-write + + + + + CSTOR + Completion Signal Timeout Register + 0x0000001C + 32 + read-write + 0x00000000 + + + CSTOCYC + Completion Signal Timeout Cycle Number + 0 + 4 + read-write + + + CSTOMUL + Completion Signal Timeout Multiplier + 4 + 3 + read-write + + + 1 + CSTOCYC x 1 + 0x0 + + + 16 + CSTOCYC x 16 + 0x1 + + + 128 + CSTOCYC x 128 + 0x2 + + + 256 + CSTOCYC x 256 + 0x3 + + + 1024 + CSTOCYC x 1024 + 0x4 + + + 4096 + CSTOCYC x 4096 + 0x5 + + + 65536 + CSTOCYC x 65536 + 0x6 + + + 1048576 + CSTOCYC x 1048576 + 0x7 + + + + + + + 4 + 4 + 0-3 + RSPR[%s] + Response Register + 0x00000020 + 32 + read-only + + + RSP + Response + 0 + 32 + read-only + + + + + RDR + Receive Data Register + 0x00000030 + 32 + read-only + 0x00000000 + + + DATA + Data to Read + 0 + 32 + read-only + + + + + TDR + Transmit Data Register + 0x00000034 + 32 + write-only + + + DATA + Data to Write + 0 + 32 + write-only + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x0000C0E5 + + + CMDRDY + Command Ready + 0 + 1 + read-only + + + RXRDY + Receiver Ready + 1 + 1 + read-only + + + TXRDY + Transmit Ready + 2 + 1 + read-only + + + BLKE + Data Block Ended + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress + 4 + 1 + read-only + + + NOTBUSY + HSMCI Not Busy + 5 + 1 + read-only + + + ENDRX + End of RX Buffer + 6 + 1 + read-only + + + ENDTX + End of TX Buffer + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status + 12 + 1 + read-only + + + CSRCV + CE-ATA Completion Signal Received + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + RINDE + Response Index Error + 16 + 1 + read-only + + + RDIRE + Response Direction Error + 17 + 1 + read-only + + + RCRCE + Response CRC Error + 18 + 1 + read-only + + + RENDE + Response End Bit Error + 19 + 1 + read-only + + + RTOE + Response Time-out Error + 20 + 1 + read-only + + + DCRCE + Data CRC Error + 21 + 1 + read-only + + + DTOE + Data Time-out Error + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error + 23 + 1 + read-only + + + FIFOEMPTY + FIFO empty flag + 26 + 1 + read-only + + + XFRDONE + Transfer Done flag + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error + 29 + 1 + read-only + + + OVRE + Overrun + 30 + 1 + read-only + + + UNRE + Underrun + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Enable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Enable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Enable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Enable + 12 + 1 + write-only + + + CSRCV + Completion Signal Received Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Enable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Enable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Enable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Enable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Enable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Enable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Enable + 22 + 1 + write-only + + + CSTOE + Completion Signal Timeout Error Interrupt Enable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt enable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt enable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Enable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Enable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Enable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + CMDRDY + Command Ready Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receiver Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 2 + 1 + write-only + + + BLKE + Data Block Ended Interrupt Disable + 3 + 1 + write-only + + + DTIP + Data Transfer in Progress Interrupt Disable + 4 + 1 + write-only + + + NOTBUSY + Data Not Busy Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 6 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 7 + 1 + write-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Disable + 8 + 1 + write-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Disable + 12 + 1 + write-only + + + CSRCV + Completion Signal received interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + RINDE + Response Index Error Interrupt Disable + 16 + 1 + write-only + + + RDIRE + Response Direction Error Interrupt Disable + 17 + 1 + write-only + + + RCRCE + Response CRC Error Interrupt Disable + 18 + 1 + write-only + + + RENDE + Response End Bit Error Interrupt Disable + 19 + 1 + write-only + + + RTOE + Response Time-out Error Interrupt Disable + 20 + 1 + write-only + + + DCRCE + Data CRC Error Interrupt Disable + 21 + 1 + write-only + + + DTOE + Data Time-out Error Interrupt Disable + 22 + 1 + write-only + + + CSTOE + Completion Signal Time out Error Interrupt Disable + 23 + 1 + write-only + + + FIFOEMPTY + FIFO empty Interrupt Disable + 26 + 1 + write-only + + + XFRDONE + Transfer Done Interrupt Disable + 27 + 1 + write-only + + + ACKRCV + Boot Acknowledge Interrupt Disable + 28 + 1 + write-only + + + ACKRCVE + Boot Acknowledge Error Interrupt Disable + 29 + 1 + write-only + + + OVRE + Overrun Interrupt Disable + 30 + 1 + write-only + + + UNRE + Underrun Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + CMDRDY + Command Ready Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receiver Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Ready Interrupt Mask + 2 + 1 + read-only + + + BLKE + Data Block Ended Interrupt Mask + 3 + 1 + read-only + + + DTIP + Data Transfer in Progress Interrupt Mask + 4 + 1 + read-only + + + NOTBUSY + Data Not Busy Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 6 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 7 + 1 + read-only + + + SDIOIRQA + SDIO Interrupt for Slot A Interrupt Mask + 8 + 1 + read-only + + + SDIOWAIT + SDIO Read Wait Operation Status Interrupt Mask + 12 + 1 + read-only + + + CSRCV + Completion Signal Received Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + RINDE + Response Index Error Interrupt Mask + 16 + 1 + read-only + + + RDIRE + Response Direction Error Interrupt Mask + 17 + 1 + read-only + + + RCRCE + Response CRC Error Interrupt Mask + 18 + 1 + read-only + + + RENDE + Response End Bit Error Interrupt Mask + 19 + 1 + read-only + + + RTOE + Response Time-out Error Interrupt Mask + 20 + 1 + read-only + + + DCRCE + Data CRC Error Interrupt Mask + 21 + 1 + read-only + + + DTOE + Data Time-out Error Interrupt Mask + 22 + 1 + read-only + + + CSTOE + Completion Signal Time-out Error Interrupt Mask + 23 + 1 + read-only + + + FIFOEMPTY + FIFO Empty Interrupt Mask + 26 + 1 + read-only + + + XFRDONE + Transfer Done Interrupt Mask + 27 + 1 + read-only + + + ACKRCV + Boot Operation Acknowledge Received Interrupt Mask + 28 + 1 + read-only + + + ACKRCVE + Boot Operation Acknowledge Error Interrupt Mask + 29 + 1 + read-only + + + OVRE + Overrun Interrupt Mask + 30 + 1 + read-only + + + UNRE + Underrun Interrupt Mask + 31 + 1 + read-only + + + + + CFG + Configuration Register + 0x00000054 + 32 + read-write + 0x00000000 + + + FIFOMODE + HSMCI Internal FIFO control mode + 0 + 1 + read-write + + + FERRCTRL + Flow Error flag reset control mode + 4 + 1 + read-write + + + HSMODE + High Speed Mode + 8 + 1 + read-write + + + LSYNC + Synchronize on the last block + 12 + 1 + read-write + + + + + WPMR + Write Protection Mode Register + 0x000000E4 + 32 + read-write + + + WP_EN + Write Protection Enable + 0 + 1 + read-write + + + WP_KEY + Write Protection Key password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + + + WP_VS + Write Protection Violation Status + 0 + 4 + read-only + + + NONE + No Write Protection Violation occurred since the last read of this register (WP_SR) + 0x0 + + + WRITE + Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.) + 0x1 + + + RESET + Software reset had been performed while Write Protection was enabled (since the last read). + 0x2 + + + BOTH + Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. + 0x3 + + + + + WP_VSRC + Write Protection Violation SouRCe + 8 + 16 + read-only + + + + + 256 + 4 + 0-255 + FIFO[%s] + FIFO Memory Aperture0 + 0x00000200 + 32 + read-write + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SSC + 6078J + Synchronous Serial Controller + SSC_ + 0x40004000 + + 0 + 0x4000 + registers + + + SSC + 22 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RXEN + Receive Enable + 0 + 1 + write-only + + + RXDIS + Receive Disable + 1 + 1 + write-only + + + TXEN + Transmit Enable + 8 + 1 + write-only + + + TXDIS + Transmit Disable + 9 + 1 + write-only + + + SWRST + Software Reset + 15 + 1 + write-only + + + + + CMR + Clock Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + DIV + Clock Divider + 0 + 12 + read-write + + + + + RCMR + Receive Clock Mode Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CKS + Receive Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Receive Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + CKI + Receive Clock Inversion + 5 + 1 + read-write + + + CKG + Receive Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Receive Clock only during data transfers + 0x2 + + + + + START + Receive Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. + 0x0 + + + TRANSMIT + Transmit start + 0x1 + + + RF_LOW + Detection of a low level on RF signal + 0x2 + + + RF_HIGH + Detection of a high level on RF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on RF signal + 0x4 + + + RF_RISING + Detection of a rising edge on RF signal + 0x5 + + + RF_LEVEL + Detection of any level change on RF signal + 0x6 + + + RF_EDGE + Detection of any edge on RF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STOP + Receive Stop Selection + 12 + 1 + read-write + + + STTDLY + Receive Start Delay + 16 + 8 + read-write + + + PERIOD + Receive Period Divider Selection + 24 + 8 + read-write + + + + + RFMR + Receive Frame Mode Register + 0x00000014 + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + LOOP + Loop Mode + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per Frame + 8 + 4 + read-write + + + FSLEN + Receive Frame Sync Length + 16 + 4 + read-write + + + FSOS + Receive Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + TCMR + Transmit Clock Mode Register + 0x00000018 + 32 + read-write + 0x00000000 + + + CKS + Transmit Clock Selection + 0 + 2 + read-write + + + MCK + Divided Clock + 0x0 + + + TK + TK Clock signal + 0x1 + + + RK + RK pin + 0x2 + + + + + CKO + Transmit Clock Output Mode Selection + 2 + 3 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Continuous Receive Clock + 0x1 + + + TRANSFER + Transmit Clock only during data transfers + 0x2 + + + + + CKI + Transmit Clock Inversion + 5 + 1 + read-write + + + CKG + Transmit Clock Gating Selection + 6 + 2 + read-write + + + NONE + None + 0x0 + + + CONTINUOUS + Transmit Clock enabled only if TF Low + 0x1 + + + TRANSFER + Transmit Clock enabled only if TF High + 0x2 + + + + + START + Transmit Start Selection + 8 + 4 + read-write + + + CONTINUOUS + Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. + 0x0 + + + RECEIVE + Receive start + 0x1 + + + RF_LOW + Detection of a low level on TF signal + 0x2 + + + RF_HIGH + Detection of a high level on TF signal + 0x3 + + + RF_FALLING + Detection of a falling edge on TF signal + 0x4 + + + RF_RISING + Detection of a rising edge on TF signal + 0x5 + + + RF_LEVEL + Detection of any level change on TF signal + 0x6 + + + RF_EDGE + Detection of any edge on TF signal + 0x7 + + + CMP_0 + Compare 0 + 0x8 + + + + + STTDLY + Transmit Start Delay + 16 + 8 + read-write + + + PERIOD + Transmit Period Divider Selection + 24 + 8 + read-write + + + + + TFMR + Transmit Frame Mode Register + 0x0000001C + 32 + read-write + 0x00000000 + + + DATLEN + Data Length + 0 + 5 + read-write + + + DATDEF + Data Default Value + 5 + 1 + read-write + + + MSBF + Most Significant Bit First + 7 + 1 + read-write + + + DATNB + Data Number per frame + 8 + 4 + read-write + + + FSLEN + Transmit Frame Sync Length + 16 + 4 + read-write + + + FSOS + Transmit Frame Sync Output Selection + 20 + 3 + read-write + + + NONE + None + 0x0 + + + NEGATIVE + Negative Pulse + 0x1 + + + POSITIVE + Positive Pulse + 0x2 + + + LOW + Driven Low during data transfer + 0x3 + + + HIGH + Driven High during data transfer + 0x4 + + + TOGGLING + Toggling at each start of data transfer + 0x5 + + + + + FSDEN + Frame Sync Data Enable + 23 + 1 + read-write + + + FSEDGE + Frame Sync Edge Detection + 24 + 1 + read-write + + + POSITIVE + Positive Edge Detection + 0 + + + NEGATIVE + Negative Edge Detection + 1 + + + + + FSLEN_EXT + FSLEN Field Extension + 28 + 4 + read-write + + + + + RHR + Receive Holding Register + 0x00000020 + 32 + read-only + 0x00000000 + + + RDAT + Receive Data + 0 + 32 + read-only + + + + + THR + Transmit Holding Register + 0x00000024 + 32 + write-only + + + TDAT + Transmit Data + 0 + 32 + write-only + + + + + RSHR + Receive Sync. Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RSDAT + Receive Synchronization Data + 0 + 16 + read-only + + + + + TSHR + Transmit Sync. Holding Register + 0x00000034 + 32 + read-write + 0x00000000 + + + TSDAT + Transmit Synchronization Data + 0 + 16 + read-write + + + + + RC0R + Receive Compare 0 Register + 0x00000038 + 32 + read-write + 0x00000000 + + + CP0 + Receive Compare Data 0 + 0 + 16 + read-write + + + + + RC1R + Receive Compare 1 Register + 0x0000003C + 32 + read-write + 0x00000000 + + + CP1 + Receive Compare Data 1 + 0 + 16 + read-write + + + + + SR + Status Register + 0x00000040 + 32 + read-only + 0x000000CC + + + TXRDY + Transmit Ready + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty + 1 + 1 + read-only + + + ENDTX + End of Transmission + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + RXRDY + Receive Ready + 4 + 1 + read-only + + + OVRUN + Receive Overrun + 5 + 1 + read-only + + + ENDRX + End of Reception + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 7 + 1 + read-only + + + CP0 + Compare 0 + 8 + 1 + read-only + + + CP1 + Compare 1 + 9 + 1 + read-only + + + TXSYN + Transmit Sync + 10 + 1 + read-only + + + RXSYN + Receive Sync + 11 + 1 + read-only + + + TXEN + Transmit Enable + 16 + 1 + read-only + + + RXEN + Receive Enable + 17 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000044 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Enable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Enable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Enable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Enable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Enable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000048 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable + 0 + 1 + write-only + + + TXEMPTY + Transmit Empty Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmission Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + RXRDY + Receive Ready Interrupt Disable + 4 + 1 + write-only + + + OVRUN + Receive Overrun Interrupt Disable + 5 + 1 + write-only + + + ENDRX + End of Reception Interrupt Disable + 6 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 7 + 1 + write-only + + + CP0 + Compare 0 Interrupt Disable + 8 + 1 + write-only + + + CP1 + Compare 1 Interrupt Disable + 9 + 1 + write-only + + + TXSYN + Tx Sync Interrupt Enable + 10 + 1 + write-only + + + RXSYN + Rx Sync Interrupt Enable + 11 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000004C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + TXEMPTY + Transmit Empty Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmission Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + RXRDY + Receive Ready Interrupt Mask + 4 + 1 + read-only + + + OVRUN + Receive Overrun Interrupt Mask + 5 + 1 + read-only + + + ENDRX + End of Reception Interrupt Mask + 6 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 7 + 1 + read-only + + + CP0 + Compare 0 Interrupt Mask + 8 + 1 + read-only + + + CP1 + Compare 1 Interrupt Mask + 9 + 1 + read-only + + + TXSYN + Tx Sync Interrupt Mask + 10 + 1 + read-only + + + RXSYN + Rx Sync Interrupt Mask + 11 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + SPI + 6088R + Serial Peripheral Interface + SPI_ + 0x40008000 + + 0 + 0x4000 + registers + + + SPI + 21 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SPIEN + SPI Enable + 0 + 1 + write-only + + + SPIDIS + SPI Disable + 1 + 1 + write-only + + + SWRST + SPI Software Reset + 7 + 1 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + MSTR + Master/Slave Mode + 0 + 1 + read-write + + + PS + Peripheral Select + 1 + 1 + read-write + + + PCSDEC + Chip Select Decode + 2 + 1 + read-write + + + MODFDIS + Mode Fault Detection + 4 + 1 + read-write + + + WDRBT + Wait Data Read Before Transfer + 5 + 1 + read-write + + + LLB + Local Loopback Enable + 7 + 1 + read-write + + + PCS + Peripheral Chip Select + 16 + 4 + read-write + + + DLYBCS + Delay Between Chip Selects + 24 + 8 + read-write + + + + + RDR + Receive Data Register + 0x00000008 + 32 + read-only + 0x00000000 + + + RD + Receive Data + 0 + 16 + read-only + + + PCS + Peripheral Chip Select + 16 + 4 + read-only + + + + + TDR + Transmit Data Register + 0x0000000C + 32 + write-only + + + TD + Transmit Data + 0 + 16 + write-only + + + PCS + Peripheral Chip Select + 16 + 4 + write-only + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + SR + Status Register + 0x00000010 + 32 + read-only + 0x000000F0 + + + RDRF + Receive Data Register Full + 0 + 1 + read-only + + + TDRE + Transmit Data Register Empty + 1 + 1 + read-only + + + MODF + Mode Fault Error + 2 + 1 + read-only + + + OVRES + Overrun Error Status + 3 + 1 + read-only + + + ENDRX + End of RX buffer + 4 + 1 + read-only + + + ENDTX + End of TX buffer + 5 + 1 + read-only + + + RXBUFF + RX Buffer Full + 6 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 7 + 1 + read-only + + + NSSR + NSS Rising + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty + 9 + 1 + read-only + + + UNDES + Underrun Error Status (Slave Mode Only) + 10 + 1 + read-only + + + SPIENS + SPI Enable Status + 16 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000014 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Enable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Enable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Enable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Enable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Enable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000018 + 32 + write-only + + + RDRF + Receive Data Register Full Interrupt Disable + 0 + 1 + write-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Disable + 1 + 1 + write-only + + + MODF + Mode Fault Error Interrupt Disable + 2 + 1 + write-only + + + OVRES + Overrun Error Interrupt Disable + 3 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 4 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 5 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 6 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 7 + 1 + write-only + + + NSSR + NSS Rising Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + Transmission Registers Empty Disable + 9 + 1 + write-only + + + UNDES + Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + RDRF + Receive Data Register Full Interrupt Mask + 0 + 1 + read-only + + + TDRE + SPI Transmit Data Register Empty Interrupt Mask + 1 + 1 + read-only + + + MODF + Mode Fault Error Interrupt Mask + 2 + 1 + read-only + + + OVRES + Overrun Error Interrupt Mask + 3 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 4 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 5 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 6 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 7 + 1 + read-only + + + NSSR + NSS Rising Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + Transmission Registers Empty Mask + 9 + 1 + read-only + + + UNDES + Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + 4 + 4 + 0-3 + CSR[%s] + Chip Select Register + 0x00000030 + 32 + read-write + + + CPOL + Clock Polarity + 0 + 1 + read-write + + + NCPHA + Clock Phase + 1 + 1 + read-write + + + CSNAAT + Chip Select Not Active After Transfer (Ignored if CSAAT = 1) + 2 + 1 + read-write + + + CSAAT + Chip Select Active After Transfer + 3 + 1 + read-write + + + BITS + Bits Per Transfer + 4 + 4 + read-write + + + 8_BIT + 8 bits for transfer + 0x0 + + + 9_BIT + 9 bits for transfer + 0x1 + + + 10_BIT + 10 bits for transfer + 0x2 + + + 11_BIT + 11 bits for transfer + 0x3 + + + 12_BIT + 12 bits for transfer + 0x4 + + + 13_BIT + 13 bits for transfer + 0x5 + + + 14_BIT + 14 bits for transfer + 0x6 + + + 15_BIT + 15 bits for transfer + 0x7 + + + 16_BIT + 16 bits for transfer + 0x8 + + + + + SCBR + Serial Clock Baud Rate + 8 + 8 + read-write + + + DLYBS + Delay Before SPCK + 16 + 8 + read-write + + + DLYBCT + Delay Between Consecutive Transfers + 24 + 8 + read-write + + + + + WPMR + Write Protection Control Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protection Enable + 0 + 1 + read-write + + + WPKEY + Write Protection Key Password + 8 + 24 + read-write + + + + + WPSR + Write Protection Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protection Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protection Violation Source + 8 + 8 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TC0 + 6082Q + Timer Counter 0 + TC + TC0_ + 0x40010000 + + 0 + 0x4000 + registers + + + TC0 + 23 + + + TC1 + 24 + + + TC2 + 25 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + + + TC1 + 6082Q + Timer Counter 1 + TC + TC1_ + 0x40014000 + + 0 + 0x4000 + registers + + + TC3 + 26 + + + TC4 + 27 + + + TC5 + 28 + + + + CCR0 + Channel Control Register (channel = 0) + 0x00000000 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR0 + Channel Mode Register (channel = 0) + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR0_WAVE_EQ_1 + Channel Mode Register (channel = 0) + WAVE_EQ_1 + 0x00000004 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR0 + Stepper Motor Mode Register (channel = 0) + 0x00000008 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV0 + Counter Value (channel = 0) + 0x00000010 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA0 + Register A (channel = 0) + 0x00000014 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB0 + Register B (channel = 0) + 0x00000018 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC0 + Register C (channel = 0) + 0x0000001C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR0 + Status Register (channel = 0) + 0x00000020 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER0 + Interrupt Enable Register (channel = 0) + 0x00000024 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR0 + Interrupt Disable Register (channel = 0) + 0x00000028 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR0 + Interrupt Mask Register (channel = 0) + 0x0000002C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR1 + Channel Control Register (channel = 1) + 0x00000040 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR1 + Channel Mode Register (channel = 1) + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR1_WAVE_EQ_1 + Channel Mode Register (channel = 1) + WAVE_EQ_1 + 0x00000044 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR1 + Stepper Motor Mode Register (channel = 1) + 0x00000048 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV1 + Counter Value (channel = 1) + 0x00000050 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA1 + Register A (channel = 1) + 0x00000054 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB1 + Register B (channel = 1) + 0x00000058 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC1 + Register C (channel = 1) + 0x0000005C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR1 + Status Register (channel = 1) + 0x00000060 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER1 + Interrupt Enable Register (channel = 1) + 0x00000064 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR1 + Interrupt Disable Register (channel = 1) + 0x00000068 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR1 + Interrupt Mask Register (channel = 1) + 0x0000006C + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + CCR2 + Channel Control Register (channel = 2) + 0x00000080 + 32 + write-only + + + CLKEN + Counter Clock Enable Command + 0 + 1 + write-only + + + CLKDIS + Counter Clock Disable Command + 1 + 1 + write-only + + + SWTRG + Software Trigger Command + 2 + 1 + write-only + + + + + CMR2 + Channel Mode Register (channel = 2) + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + LDBSTOP + Counter Clock Stopped with RB Loading + 6 + 1 + read-write + + + LDBDIS + Counter Clock Disable with RB Loading + 7 + 1 + read-write + + + ETRGEDG + External Trigger Edge Selection + 8 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + ABETRG + TIOA or TIOB External Trigger Selection + 10 + 1 + read-write + + + CPCTRG + RC Compare Trigger Enable + 14 + 1 + read-write + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + LDRA + RA Loading Edge Selection + 16 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + LDRB + RB Loading Edge Selection + 18 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge of TIOA + 0x1 + + + FALLING + Falling edge of TIOA + 0x2 + + + EDGE + Each edge of TIOA + 0x3 + + + + + + + CMR2_WAVE_EQ_1 + Channel Mode Register (channel = 2) + WAVE_EQ_1 + 0x00000084 + 32 + read-write + 0x00000000 + + + TCCLKS + Clock Selection + 0 + 3 + read-write + + + TIMER_CLOCK1 + Clock selected: TCLK1 + 0x0 + + + TIMER_CLOCK2 + Clock selected: TCLK2 + 0x1 + + + TIMER_CLOCK3 + Clock selected: TCLK3 + 0x2 + + + TIMER_CLOCK4 + Clock selected: TCLK4 + 0x3 + + + TIMER_CLOCK5 + Clock selected: TCLK5 + 0x4 + + + XC0 + Clock selected: XC0 + 0x5 + + + XC1 + Clock selected: XC1 + 0x6 + + + XC2 + Clock selected: XC2 + 0x7 + + + + + CLKI + Clock Invert + 3 + 1 + read-write + + + BURST + Burst Signal Selection + 4 + 2 + read-write + + + NONE + The clock is not gated by an external signal. + 0x0 + + + XC0 + XC0 is ANDed with the selected clock. + 0x1 + + + XC1 + XC1 is ANDed with the selected clock. + 0x2 + + + XC2 + XC2 is ANDed with the selected clock. + 0x3 + + + + + CPCSTOP + Counter Clock Stopped with RC Compare + 6 + 1 + read-write + + + CPCDIS + Counter Clock Disable with RC Compare + 7 + 1 + read-write + + + EEVTEDG + External Event Edge Selection + 8 + 2 + read-write + + + NONE + None + 0x0 + + + RISING + Rising edge + 0x1 + + + FALLING + Falling edge + 0x2 + + + EDGE + Each edge + 0x3 + + + + + EEVT + External Event Selection + 10 + 2 + read-write + + + TIOB + TIOB + 0x0 + + + XC0 + XC0 + 0x1 + + + XC1 + XC1 + 0x2 + + + XC2 + XC2 + 0x3 + + + + + ENETRG + External Event Trigger Enable + 12 + 1 + read-write + + + WAVSEL + Waveform Selection + 13 + 2 + read-write + + + UP + UP mode without automatic trigger on RC Compare + 0x0 + + + UPDOWN + UPDOWN mode without automatic trigger on RC Compare + 0x1 + + + UP_RC + UP mode with automatic trigger on RC Compare + 0x2 + + + UPDOWN_RC + UPDOWN mode with automatic trigger on RC Compare + 0x3 + + + + + WAVE + Waveform Mode + 15 + 1 + read-write + + + ACPA + RA Compare Effect on TIOA + 16 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ACPC + RC Compare Effect on TIOA + 18 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + AEEVT + External Event Effect on TIOA + 20 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + ASWTRG + Software Trigger Effect on TIOA + 22 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPB + RB Compare Effect on TIOB + 24 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BCPC + RC Compare Effect on TIOB + 26 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BEEVT + External Event Effect on TIOB + 28 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + BSWTRG + Software Trigger Effect on TIOB + 30 + 2 + read-write + + + NONE + None + 0x0 + + + SET + Set + 0x1 + + + CLEAR + Clear + 0x2 + + + TOGGLE + Toggle + 0x3 + + + + + + + SMMR2 + Stepper Motor Mode Register (channel = 2) + 0x00000088 + 32 + read-write + 0x00000000 + + + GCEN + Gray Count Enable + 0 + 1 + read-write + + + DOWN + DOWN Count + 1 + 1 + read-write + + + + + CV2 + Counter Value (channel = 2) + 0x00000090 + 32 + read-only + 0x00000000 + + + CV + Counter Value + 0 + 32 + read-only + + + + + RA2 + Register A (channel = 2) + 0x00000094 + 32 + read-write + 0x00000000 + + + RA + Register A + 0 + 32 + read-write + + + + + RB2 + Register B (channel = 2) + 0x00000098 + 32 + read-write + 0x00000000 + + + RB + Register B + 0 + 32 + read-write + + + + + RC2 + Register C (channel = 2) + 0x0000009C + 32 + read-write + 0x00000000 + + + RC + Register C + 0 + 32 + read-write + + + + + SR2 + Status Register (channel = 2) + 0x000000A0 + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow Status + 0 + 1 + read-only + + + LOVRS + Load Overrun Status + 1 + 1 + read-only + + + CPAS + RA Compare Status + 2 + 1 + read-only + + + CPBS + RB Compare Status + 3 + 1 + read-only + + + CPCS + RC Compare Status + 4 + 1 + read-only + + + LDRAS + RA Loading Status + 5 + 1 + read-only + + + LDRBS + RB Loading Status + 6 + 1 + read-only + + + ETRGS + External Trigger Status + 7 + 1 + read-only + + + CLKSTA + Clock Enabling Status + 16 + 1 + read-only + + + MTIOA + TIOA Mirror + 17 + 1 + read-only + + + MTIOB + TIOB Mirror + 18 + 1 + read-only + + + + + IER2 + Interrupt Enable Register (channel = 2) + 0x000000A4 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IDR2 + Interrupt Disable Register (channel = 2) + 0x000000A8 + 32 + write-only + + + COVFS + Counter Overflow + 0 + 1 + write-only + + + LOVRS + Load Overrun + 1 + 1 + write-only + + + CPAS + RA Compare + 2 + 1 + write-only + + + CPBS + RB Compare + 3 + 1 + write-only + + + CPCS + RC Compare + 4 + 1 + write-only + + + LDRAS + RA Loading + 5 + 1 + write-only + + + LDRBS + RB Loading + 6 + 1 + write-only + + + ETRGS + External Trigger + 7 + 1 + write-only + + + + + IMR2 + Interrupt Mask Register (channel = 2) + 0x000000AC + 32 + read-only + 0x00000000 + + + COVFS + Counter Overflow + 0 + 1 + read-only + + + LOVRS + Load Overrun + 1 + 1 + read-only + + + CPAS + RA Compare + 2 + 1 + read-only + + + CPBS + RB Compare + 3 + 1 + read-only + + + CPCS + RC Compare + 4 + 1 + read-only + + + LDRAS + RA Loading + 5 + 1 + read-only + + + LDRBS + RB Loading + 6 + 1 + read-only + + + ETRGS + External Trigger + 7 + 1 + read-only + + + + + BCR + Block Control Register + 0x000000C0 + 32 + write-only + + + SYNC + Synchro Command + 0 + 1 + write-only + + + + + BMR + Block Mode Register + 0x000000C4 + 32 + read-write + 0x00000000 + + + TC0XC0S + External Clock Signal 0 Selection + 0 + 2 + read-write + + + TCLK0 + Signal connected to XC0: TCLK0 + 0x0 + + + TIOA1 + Signal connected to XC0: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC0: TIOA2 + 0x3 + + + + + TC1XC1S + External Clock Signal 1 Selection + 2 + 2 + read-write + + + TCLK1 + Signal connected to XC1: TCLK1 + 0x0 + + + TIOA0 + Signal connected to XC1: TIOA0 + 0x2 + + + TIOA2 + Signal connected to XC1: TIOA2 + 0x3 + + + + + TC2XC2S + External Clock Signal 2 Selection + 4 + 2 + read-write + + + TCLK2 + Signal connected to XC2: TCLK2 + 0x0 + + + TIOA1 + Signal connected to XC2: TIOA1 + 0x2 + + + TIOA2 + Signal connected to XC2: TIOA2 + 0x3 + + + + + QDEN + Quadrature Decoder ENabled + 8 + 1 + read-write + + + POSEN + POSition ENabled + 9 + 1 + read-write + + + SPEEDEN + SPEED ENabled + 10 + 1 + read-write + + + QDTRANS + Quadrature Decoding TRANSparent + 11 + 1 + read-write + + + EDGPHA + EDGe on PHA count mode + 12 + 1 + read-write + + + INVA + INVerted phA + 13 + 1 + read-write + + + INVB + INVerted phB + 14 + 1 + read-write + + + INVIDX + INVerted InDeX + 15 + 1 + read-write + + + SWAP + SWAP PHA and PHB + 16 + 1 + read-write + + + IDXPHB + InDeX pin is PHB pin + 17 + 1 + read-write + + + FILTER + 19 + 1 + read-write + + + MAXFILT + MAXimum FILTer + 20 + 6 + read-write + + + + + QIER + QDEC Interrupt Enable Register + 0x000000C8 + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIDR + QDEC Interrupt Disable Register + 0x000000CC + 32 + write-only + + + IDX + InDeX + 0 + 1 + write-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + write-only + + + QERR + Quadrature ERRor + 2 + 1 + write-only + + + + + QIMR + QDEC Interrupt Mask Register + 0x000000D0 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + + + QISR + QDEC Interrupt Status Register + 0x000000D4 + 32 + read-only + 0x00000000 + + + IDX + InDeX + 0 + 1 + read-only + + + DIRCHG + DIRection CHanGe + 1 + 1 + read-only + + + QERR + Quadrature ERRor + 2 + 1 + read-only + + + DIR + DIRection + 8 + 1 + read-only + + + + + FMR + Fault Mode Register + 0x000000D8 + 32 + read-write + 0x00000000 + + + ENCF0 + ENable Compare Fault Channel 0 + 0 + 1 + read-write + + + ENCF1 + ENable Compare Fault Channel 1 + 1 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + + + TWI0 + 6212L + Two-wire Interface 0 + TWI + TWI0_ + 0x40018000 + + 0 + 0x4000 + registers + + + TWI0 + 19 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + TWI1 + 6212L + Two-wire Interface 1 + TWI + TWI1_ + 0x4001C000 + + 0 + 0x4000 + registers + + + TWI1 + 20 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + START + Send a START Condition + 0 + 1 + write-only + + + STOP + Send a STOP Condition + 1 + 1 + write-only + + + MSEN + TWI Master Mode Enabled + 2 + 1 + write-only + + + MSDIS + TWI Master Mode Disabled + 3 + 1 + write-only + + + SVEN + TWI Slave Mode Enabled + 4 + 1 + write-only + + + SVDIS + TWI Slave Mode Disabled + 5 + 1 + write-only + + + QUICK + SMBUS Quick Command + 6 + 1 + write-only + + + SWRST + Software Reset + 7 + 1 + write-only + + + + + MMR + Master Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + IADRSZ + Internal Device Address Size + 8 + 2 + read-write + + + NONE + No internal device address + 0x0 + + + 1_BYTE + One-byte internal device address + 0x1 + + + 2_BYTE + Two-byte internal device address + 0x2 + + + 3_BYTE + Three-byte internal device address + 0x3 + + + + + MREAD + Master Read Direction + 12 + 1 + read-write + + + DADR + Device Address + 16 + 7 + read-write + + + + + SMR + Slave Mode Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SADR + Slave Address + 16 + 7 + read-write + + + + + IADR + Internal Address Register + 0x0000000C + 32 + read-write + 0x00000000 + + + IADR + Internal Address + 0 + 24 + read-write + + + + + CWGR + Clock Waveform Generator Register + 0x00000010 + 32 + read-write + 0x00000000 + + + CLDIV + Clock Low Divider + 0 + 8 + read-write + + + CHDIV + Clock High Divider + 8 + 8 + read-write + + + CKDIV + Clock Divider + 16 + 3 + read-write + + + + + SR + Status Register + 0x00000020 + 32 + read-only + 0x0000F009 + + + TXCOMP + Transmission Completed (automatically set / reset) + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready (automatically set / reset) + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready (automatically set / reset) + 2 + 1 + read-only + + + SVREAD + Slave Read (automatically set / reset) + 3 + 1 + read-only + + + SVACC + Slave Access (automatically set / reset) + 4 + 1 + read-only + + + GACC + General Call Access (clear on read) + 5 + 1 + read-only + + + OVRE + Overrun Error (clear on read) + 6 + 1 + read-only + + + NACK + Not Acknowledged (clear on read) + 8 + 1 + read-only + + + ARBLST + Arbitration Lost (clear on read) + 9 + 1 + read-only + + + SCLWS + Clock Wait State (automatically set / reset) + 10 + 1 + read-only + + + EOSACC + End Of Slave Access (clear on read) + 11 + 1 + read-only + + + ENDRX + End of RX buffer + 12 + 1 + read-only + + + ENDTX + End of TX buffer + 13 + 1 + read-only + + + RXBUFF + RX Buffer Full + 14 + 1 + read-only + + + TXBUFE + TX Buffer Empty + 15 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Enable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Enable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Enable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Enable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Enable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Enable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Enable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Enable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Enable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 15 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXCOMP + Transmission Completed Interrupt Disable + 0 + 1 + write-only + + + RXRDY + Receive Holding Register Ready Interrupt Disable + 1 + 1 + write-only + + + TXRDY + Transmit Holding Register Ready Interrupt Disable + 2 + 1 + write-only + + + SVACC + Slave Access Interrupt Disable + 4 + 1 + write-only + + + GACC + General Call Access Interrupt Disable + 5 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 6 + 1 + write-only + + + NACK + Not Acknowledge Interrupt Disable + 8 + 1 + write-only + + + ARBLST + Arbitration Lost Interrupt Disable + 9 + 1 + write-only + + + SCL_WS + Clock Wait State Interrupt Disable + 10 + 1 + write-only + + + EOSACC + End Of Slave Access Interrupt Disable + 11 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 12 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 13 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 14 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 15 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXCOMP + Transmission Completed Interrupt Mask + 0 + 1 + read-only + + + RXRDY + Receive Holding Register Ready Interrupt Mask + 1 + 1 + read-only + + + TXRDY + Transmit Holding Register Ready Interrupt Mask + 2 + 1 + read-only + + + SVACC + Slave Access Interrupt Mask + 4 + 1 + read-only + + + GACC + General Call Access Interrupt Mask + 5 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 6 + 1 + read-only + + + NACK + Not Acknowledge Interrupt Mask + 8 + 1 + read-only + + + ARBLST + Arbitration Lost Interrupt Mask + 9 + 1 + read-only + + + SCL_WS + Clock Wait State Interrupt Mask + 10 + 1 + read-only + + + EOSACC + End Of Slave Access Interrupt Mask + 11 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 12 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 13 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 14 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 15 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000030 + 32 + read-only + 0x00000000 + + + RXDATA + Master or Slave Receive Holding Data + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x00000034 + 32 + write-only + 0x00000000 + + + TXDATA + Master or Slave Transmit Holding Data + 0 + 8 + write-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PWM + 6343H + Pulse Width Modulation Controller + PWM_ + 0x40020000 + + 0 + 0x4000 + registers + + + PWM + 31 + + + + CLK + PWM Clock Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DIVA + CLKA, CLKB Divide Factor + 0 + 8 + read-write + + + PREA + CLKA, CLKB Source Clock Selection + 8 + 4 + read-write + + + DIVB + CLKA, CLKB Divide Factor + 16 + 8 + read-write + + + PREB + CLKA, CLKB Source Clock Selection + 24 + 4 + read-write + + + + + ENA + PWM Enable Register + 0x00000004 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + DIS + PWM Disable Register + 0x00000008 + 32 + write-only + + + CHID0 + Channel ID + 0 + 1 + write-only + + + CHID1 + Channel ID + 1 + 1 + write-only + + + CHID2 + Channel ID + 2 + 1 + write-only + + + CHID3 + Channel ID + 3 + 1 + write-only + + + + + SR + PWM Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + CHID0 + Channel ID + 0 + 1 + read-only + + + CHID1 + Channel ID + 1 + 1 + read-only + + + CHID2 + Channel ID + 2 + 1 + read-only + + + CHID3 + Channel ID + 3 + 1 + read-only + + + + + IER1 + PWM Interrupt Enable Register 1 + 0x00000010 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Enable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Enable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Enable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Enable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Enable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Enable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Enable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Enable + 19 + 1 + write-only + + + + + IDR1 + PWM Interrupt Disable Register 1 + 0x00000014 + 32 + write-only + + + CHID0 + Counter Event on Channel 0 Interrupt Disable + 0 + 1 + write-only + + + CHID1 + Counter Event on Channel 1 Interrupt Disable + 1 + 1 + write-only + + + CHID2 + Counter Event on Channel 2 Interrupt Disable + 2 + 1 + write-only + + + CHID3 + Counter Event on Channel 3 Interrupt Disable + 3 + 1 + write-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Disable + 16 + 1 + write-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Disable + 17 + 1 + write-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Disable + 18 + 1 + write-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Disable + 19 + 1 + write-only + + + + + IMR1 + PWM Interrupt Mask Register 1 + 0x00000018 + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 Interrupt Mask + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 Interrupt Mask + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 Interrupt Mask + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 Interrupt Mask + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 Interrupt Mask + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 Interrupt Mask + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 Interrupt Mask + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 Interrupt Mask + 19 + 1 + read-only + + + + + ISR1 + PWM Interrupt Status Register 1 + 0x0000001C + 32 + read-only + 0x00000000 + + + CHID0 + Counter Event on Channel 0 + 0 + 1 + read-only + + + CHID1 + Counter Event on Channel 1 + 1 + 1 + read-only + + + CHID2 + Counter Event on Channel 2 + 2 + 1 + read-only + + + CHID3 + Counter Event on Channel 3 + 3 + 1 + read-only + + + FCHID0 + Fault Protection Trigger on Channel 0 + 16 + 1 + read-only + + + FCHID1 + Fault Protection Trigger on Channel 1 + 17 + 1 + read-only + + + FCHID2 + Fault Protection Trigger on Channel 2 + 18 + 1 + read-only + + + FCHID3 + Fault Protection Trigger on Channel 3 + 19 + 1 + read-only + + + + + SCM + PWM Sync Channels Mode Register + 0x00000020 + 32 + read-write + 0x00000000 + + + SYNC0 + Synchronous Channel 0 + 0 + 1 + read-write + + + SYNC1 + Synchronous Channel 1 + 1 + 1 + read-write + + + SYNC2 + Synchronous Channel 2 + 2 + 1 + read-write + + + SYNC3 + Synchronous Channel 3 + 3 + 1 + read-write + + + UPDM + Synchronous Channels Update Mode + 16 + 2 + read-write + + + MODE0 + Manual write of double buffer registers and manual update of synchronous channels + 0x0 + + + MODE1 + Manual write of double buffer registers and automatic update of synchronous channels + 0x1 + + + MODE2 + Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels + 0x2 + + + + + PTRM + PDC Transfer Request Mode + 20 + 1 + read-write + + + PTRCS + PDC Transfer Request Comparison Selection + 21 + 3 + read-write + + + + + SCUC + PWM Sync Channels Update Control Register + 0x00000028 + 32 + read-write + 0x00000000 + + + UPDULOCK + Synchronous Channels Update Unlock + 0 + 1 + read-write + + + + + SCUP + PWM Sync Channels Update Period Register + 0x0000002C + 32 + read-write + 0x00000000 + + + UPR + Update Period + 0 + 4 + read-write + + + UPRCNT + Update Period Counter + 4 + 4 + read-write + + + + + SCUPUPD + PWM Sync Channels Update Period Update Register + 0x00000030 + 32 + write-only + 0x00000000 + + + UPRUPD + Update Period Update + 0 + 4 + write-only + + + + + IER2 + PWM Interrupt Enable Register 2 + 0x00000034 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Enable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Enable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Enable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Enable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Enable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Enable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Enable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Enable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Enable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Enable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Enable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Enable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Enable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Enable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Enable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Enable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Enable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Enable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Enable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Enable + 23 + 1 + write-only + + + + + IDR2 + PWM Interrupt Disable Register 2 + 0x00000038 + 32 + write-only + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Disable + 0 + 1 + write-only + + + ENDTX + PDC End of TX Buffer Interrupt Disable + 1 + 1 + write-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Disable + 2 + 1 + write-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Disable + 3 + 1 + write-only + + + CMPM0 + Comparison 0 Match Interrupt Disable + 8 + 1 + write-only + + + CMPM1 + Comparison 1 Match Interrupt Disable + 9 + 1 + write-only + + + CMPM2 + Comparison 2 Match Interrupt Disable + 10 + 1 + write-only + + + CMPM3 + Comparison 3 Match Interrupt Disable + 11 + 1 + write-only + + + CMPM4 + Comparison 4 Match Interrupt Disable + 12 + 1 + write-only + + + CMPM5 + Comparison 5 Match Interrupt Disable + 13 + 1 + write-only + + + CMPM6 + Comparison 6 Match Interrupt Disable + 14 + 1 + write-only + + + CMPM7 + Comparison 7 Match Interrupt Disable + 15 + 1 + write-only + + + CMPU0 + Comparison 0 Update Interrupt Disable + 16 + 1 + write-only + + + CMPU1 + Comparison 1 Update Interrupt Disable + 17 + 1 + write-only + + + CMPU2 + Comparison 2 Update Interrupt Disable + 18 + 1 + write-only + + + CMPU3 + Comparison 3 Update Interrupt Disable + 19 + 1 + write-only + + + CMPU4 + Comparison 4 Update Interrupt Disable + 20 + 1 + write-only + + + CMPU5 + Comparison 5 Update Interrupt Disable + 21 + 1 + write-only + + + CMPU6 + Comparison 6 Update Interrupt Disable + 22 + 1 + write-only + + + CMPU7 + Comparison 7 Update Interrupt Disable + 23 + 1 + write-only + + + + + IMR2 + PWM Interrupt Mask Register 2 + 0x0000003C + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update Interrupt Mask + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer Interrupt Mask + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty Interrupt Mask + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error Interrupt Mask + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match Interrupt Mask + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match Interrupt Mask + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match Interrupt Mask + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match Interrupt Mask + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match Interrupt Mask + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match Interrupt Mask + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match Interrupt Mask + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match Interrupt Mask + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update Interrupt Mask + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update Interrupt Mask + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update Interrupt Mask + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update Interrupt Mask + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update Interrupt Mask + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update Interrupt Mask + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update Interrupt Mask + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update Interrupt Mask + 23 + 1 + read-only + + + + + ISR2 + PWM Interrupt Status Register 2 + 0x00000040 + 32 + read-only + 0x00000000 + + + WRDY + Write Ready for Synchronous Channels Update + 0 + 1 + read-only + + + ENDTX + PDC End of TX Buffer + 1 + 1 + read-only + + + TXBUFE + PDC TX Buffer Empty + 2 + 1 + read-only + + + UNRE + Synchronous Channels Update Underrun Error + 3 + 1 + read-only + + + CMPM0 + Comparison 0 Match + 8 + 1 + read-only + + + CMPM1 + Comparison 1 Match + 9 + 1 + read-only + + + CMPM2 + Comparison 2 Match + 10 + 1 + read-only + + + CMPM3 + Comparison 3 Match + 11 + 1 + read-only + + + CMPM4 + Comparison 4 Match + 12 + 1 + read-only + + + CMPM5 + Comparison 5 Match + 13 + 1 + read-only + + + CMPM6 + Comparison 6 Match + 14 + 1 + read-only + + + CMPM7 + Comparison 7 Match + 15 + 1 + read-only + + + CMPU0 + Comparison 0 Update + 16 + 1 + read-only + + + CMPU1 + Comparison 1 Update + 17 + 1 + read-only + + + CMPU2 + Comparison 2 Update + 18 + 1 + read-only + + + CMPU3 + Comparison 3 Update + 19 + 1 + read-only + + + CMPU4 + Comparison 4 Update + 20 + 1 + read-only + + + CMPU5 + Comparison 5 Update + 21 + 1 + read-only + + + CMPU6 + Comparison 6 Update + 22 + 1 + read-only + + + CMPU7 + Comparison 7 Update + 23 + 1 + read-only + + + + + OOV + PWM Output Override Value Register + 0x00000044 + 32 + read-write + 0x00000000 + + + OOVH0 + Output Override Value for PWMH output of the channel 0 + 0 + 1 + read-write + + + OOVH1 + Output Override Value for PWMH output of the channel 1 + 1 + 1 + read-write + + + OOVH2 + Output Override Value for PWMH output of the channel 2 + 2 + 1 + read-write + + + OOVH3 + Output Override Value for PWMH output of the channel 3 + 3 + 1 + read-write + + + OOVL0 + Output Override Value for PWML output of the channel 0 + 16 + 1 + read-write + + + OOVL1 + Output Override Value for PWML output of the channel 1 + 17 + 1 + read-write + + + OOVL2 + Output Override Value for PWML output of the channel 2 + 18 + 1 + read-write + + + OOVL3 + Output Override Value for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OS + PWM Output Selection Register + 0x00000048 + 32 + read-write + 0x00000000 + + + OSH0 + Output Selection for PWMH output of the channel 0 + 0 + 1 + read-write + + + OSH1 + Output Selection for PWMH output of the channel 1 + 1 + 1 + read-write + + + OSH2 + Output Selection for PWMH output of the channel 2 + 2 + 1 + read-write + + + OSH3 + Output Selection for PWMH output of the channel 3 + 3 + 1 + read-write + + + OSL0 + Output Selection for PWML output of the channel 0 + 16 + 1 + read-write + + + OSL1 + Output Selection for PWML output of the channel 1 + 17 + 1 + read-write + + + OSL2 + Output Selection for PWML output of the channel 2 + 18 + 1 + read-write + + + OSL3 + Output Selection for PWML output of the channel 3 + 19 + 1 + read-write + + + + + OSS + PWM Output Selection Set Register + 0x0000004C + 32 + write-only + + + OSSH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSC + PWM Output Selection Clear Register + 0x00000050 + 32 + write-only + + + OSCH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSSUPD + PWM Output Selection Set Update Register + 0x00000054 + 32 + write-only + + + OSSUPH0 + Output Selection Set for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSSUPH1 + Output Selection Set for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSSUPH2 + Output Selection Set for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSSUPH3 + Output Selection Set for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSSUPL0 + Output Selection Set for PWML output of the channel 0 + 16 + 1 + write-only + + + OSSUPL1 + Output Selection Set for PWML output of the channel 1 + 17 + 1 + write-only + + + OSSUPL2 + Output Selection Set for PWML output of the channel 2 + 18 + 1 + write-only + + + OSSUPL3 + Output Selection Set for PWML output of the channel 3 + 19 + 1 + write-only + + + + + OSCUPD + PWM Output Selection Clear Update Register + 0x00000058 + 32 + write-only + + + OSCUPH0 + Output Selection Clear for PWMH output of the channel 0 + 0 + 1 + write-only + + + OSCUPH1 + Output Selection Clear for PWMH output of the channel 1 + 1 + 1 + write-only + + + OSCUPH2 + Output Selection Clear for PWMH output of the channel 2 + 2 + 1 + write-only + + + OSCUPH3 + Output Selection Clear for PWMH output of the channel 3 + 3 + 1 + write-only + + + OSCUPL0 + Output Selection Clear for PWML output of the channel 0 + 16 + 1 + write-only + + + OSCUPL1 + Output Selection Clear for PWML output of the channel 1 + 17 + 1 + write-only + + + OSCUPL2 + Output Selection Clear for PWML output of the channel 2 + 18 + 1 + write-only + + + OSCUPL3 + Output Selection Clear for PWML output of the channel 3 + 19 + 1 + write-only + + + + + FMR + PWM Fault Mode Register + 0x0000005C + 32 + read-write + 0x00000000 + + + FPOL + Fault Polarity (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FMOD + Fault Activation Mode (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FFIL + Fault Filtering (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + + + FSR + PWM Fault Status Register + 0x00000060 + 32 + read-only + 0x00000000 + + + FIV + Fault Input Value (fault input bit varies from 0 to 5) + 0 + 8 + read-only + + + FS + Fault Status (fault input bit varies from 0 to 5) + 8 + 8 + read-only + + + + + FCR + PWM Fault Clear Register + 0x00000064 + 32 + write-only + + + FCLR + Fault Clear (fault input bit varies from 0 to 5) + 0 + 8 + write-only + + + + + FPV + PWM Fault Protection Value Register + 0x00000068 + 32 + read-write + 0x00000000 + + + FPVH0 + Fault Protection Value for PWMH output on channel 0 + 0 + 1 + read-write + + + FPVH1 + Fault Protection Value for PWMH output on channel 1 + 1 + 1 + read-write + + + FPVH2 + Fault Protection Value for PWMH output on channel 2 + 2 + 1 + read-write + + + FPVH3 + Fault Protection Value for PWMH output on channel 3 + 3 + 1 + read-write + + + FPVL0 + Fault Protection Value for PWML output on channel 0 + 16 + 1 + read-write + + + FPVL1 + Fault Protection Value for PWML output on channel 1 + 17 + 1 + read-write + + + FPVL2 + Fault Protection Value for PWML output on channel 2 + 18 + 1 + read-write + + + FPVL3 + Fault Protection Value for PWML output on channel 3 + 19 + 1 + read-write + + + + + FPE + PWM Fault Protection Enable Register + 0x0000006C + 32 + read-write + 0x00000000 + + + FPE0 + Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5) + 0 + 8 + read-write + + + FPE1 + Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5) + 8 + 8 + read-write + + + FPE2 + Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5) + 16 + 8 + read-write + + + FPE3 + Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5) + 24 + 8 + read-write + + + + + 2 + 4 + 0-1 + ELMR[%s] + PWM Event Line 0 Mode Register + 0x0000007C + 32 + read-write + + + CSEL0 + Comparison 0 Selection + 0 + 1 + read-write + + + CSEL1 + Comparison 1 Selection + 1 + 1 + read-write + + + CSEL2 + Comparison 2 Selection + 2 + 1 + read-write + + + CSEL3 + Comparison 3 Selection + 3 + 1 + read-write + + + CSEL4 + Comparison 4 Selection + 4 + 1 + read-write + + + CSEL5 + Comparison 5 Selection + 5 + 1 + read-write + + + CSEL6 + Comparison 6 Selection + 6 + 1 + read-write + + + CSEL7 + Comparison 7 Selection + 7 + 1 + read-write + + + + + WPCR + PWM Write Protect Control Register + 0x000000E4 + 32 + write-only + + + WPCMD + Write Protect Command + 0 + 2 + write-only + + + WPRG0 + Write Protect Register Group 0 + 2 + 1 + write-only + + + WPRG1 + Write Protect Register Group 1 + 3 + 1 + write-only + + + WPRG2 + Write Protect Register Group 2 + 4 + 1 + write-only + + + WPRG3 + Write Protect Register Group 3 + 5 + 1 + write-only + + + WPRG4 + Write Protect Register Group 4 + 6 + 1 + write-only + + + WPRG5 + Write Protect Register Group 5 + 7 + 1 + write-only + + + WPKEY + Write Protect Key + 8 + 24 + write-only + + + + + WPSR + PWM Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPSWS0 + Write Protect SW Status + 0 + 1 + read-only + + + WPSWS1 + Write Protect SW Status + 1 + 1 + read-only + + + WPSWS2 + Write Protect SW Status + 2 + 1 + read-only + + + WPSWS3 + Write Protect SW Status + 3 + 1 + read-only + + + WPSWS4 + Write Protect SW Status + 4 + 1 + read-only + + + WPSWS5 + Write Protect SW Status + 5 + 1 + read-only + + + WPVS + Write Protect Violation Status + 7 + 1 + read-only + + + WPHWS0 + Write Protect HW Status + 8 + 1 + read-only + + + WPHWS1 + Write Protect HW Status + 9 + 1 + read-only + + + WPHWS2 + Write Protect HW Status + 10 + 1 + read-only + + + WPHWS3 + Write Protect HW Status + 11 + 1 + read-only + + + WPHWS4 + Write Protect HW Status + 12 + 1 + read-only + + + WPHWS5 + Write Protect HW Status + 13 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 16 + 16 + read-only + + + + + CMPV0 + PWM Comparison 0 Value Register + 0x00000130 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD0 + PWM Comparison 0 Value Update Register + 0x00000134 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM0 + PWM Comparison 0 Mode Register + 0x00000138 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD0 + PWM Comparison 0 Mode Update Register + 0x0000013C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV1 + PWM Comparison 1 Value Register + 0x00000140 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD1 + PWM Comparison 1 Value Update Register + 0x00000144 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM1 + PWM Comparison 1 Mode Register + 0x00000148 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD1 + PWM Comparison 1 Mode Update Register + 0x0000014C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV2 + PWM Comparison 2 Value Register + 0x00000150 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD2 + PWM Comparison 2 Value Update Register + 0x00000154 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM2 + PWM Comparison 2 Mode Register + 0x00000158 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD2 + PWM Comparison 2 Mode Update Register + 0x0000015C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV3 + PWM Comparison 3 Value Register + 0x00000160 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD3 + PWM Comparison 3 Value Update Register + 0x00000164 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM3 + PWM Comparison 3 Mode Register + 0x00000168 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD3 + PWM Comparison 3 Mode Update Register + 0x0000016C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV4 + PWM Comparison 4 Value Register + 0x00000170 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD4 + PWM Comparison 4 Value Update Register + 0x00000174 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM4 + PWM Comparison 4 Mode Register + 0x00000178 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD4 + PWM Comparison 4 Mode Update Register + 0x0000017C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV5 + PWM Comparison 5 Value Register + 0x00000180 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD5 + PWM Comparison 5 Value Update Register + 0x00000184 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM5 + PWM Comparison 5 Mode Register + 0x00000188 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD5 + PWM Comparison 5 Mode Update Register + 0x0000018C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV6 + PWM Comparison 6 Value Register + 0x00000190 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD6 + PWM Comparison 6 Value Update Register + 0x00000194 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM6 + PWM Comparison 6 Mode Register + 0x00000198 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD6 + PWM Comparison 6 Mode Update Register + 0x0000019C + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMPV7 + PWM Comparison 7 Value Register + 0x000001A0 + 32 + read-write + 0x00000000 + + + CV + Comparison x Value + 0 + 24 + read-write + + + CVM + Comparison x Value Mode + 24 + 1 + read-write + + + + + CMPVUPD7 + PWM Comparison 7 Value Update Register + 0x000001A4 + 32 + write-only + + + CVUPD + Comparison x Value Update + 0 + 24 + write-only + + + CVMUPD + Comparison x Value Mode Update + 24 + 1 + write-only + + + + + CMPM7 + PWM Comparison 7 Mode Register + 0x000001A8 + 32 + read-write + 0x00000000 + + + CEN + Comparison x Enable + 0 + 1 + read-write + + + CTR + Comparison x Trigger + 4 + 4 + read-write + + + CPR + Comparison x Period + 8 + 4 + read-write + + + CPRCNT + Comparison x Period Counter + 12 + 4 + read-write + + + CUPR + Comparison x Update Period + 16 + 4 + read-write + + + CUPRCNT + Comparison x Update Period Counter + 20 + 4 + read-write + + + + + CMPMUPD7 + PWM Comparison 7 Mode Update Register + 0x000001AC + 32 + write-only + + + CENUPD + Comparison x Enable Update + 0 + 1 + write-only + + + CTRUPD + Comparison x Trigger Update + 4 + 4 + write-only + + + CPRUPD + Comparison x Period Update + 8 + 4 + write-only + + + CUPRUPD + Comparison x Update Period Update + 16 + 4 + write-only + + + + + CMR0 + PWM Channel Mode Register (ch_num = 0) + 0x00000200 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY0 + PWM Channel Duty Cycle Register (ch_num = 0) + 0x00000204 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD0 + PWM Channel Duty Cycle Update Register (ch_num = 0) + 0x00000208 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD0 + PWM Channel Period Register (ch_num = 0) + 0x0000020C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD0 + PWM Channel Period Update Register (ch_num = 0) + 0x00000210 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT0 + PWM Channel Counter Register (ch_num = 0) + 0x00000214 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT0 + PWM Channel Dead Time Register (ch_num = 0) + 0x00000218 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD0 + PWM Channel Dead Time Update Register (ch_num = 0) + 0x0000021C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR1 + PWM Channel Mode Register (ch_num = 1) + 0x00000220 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY1 + PWM Channel Duty Cycle Register (ch_num = 1) + 0x00000224 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD1 + PWM Channel Duty Cycle Update Register (ch_num = 1) + 0x00000228 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD1 + PWM Channel Period Register (ch_num = 1) + 0x0000022C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD1 + PWM Channel Period Update Register (ch_num = 1) + 0x00000230 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT1 + PWM Channel Counter Register (ch_num = 1) + 0x00000234 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT1 + PWM Channel Dead Time Register (ch_num = 1) + 0x00000238 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD1 + PWM Channel Dead Time Update Register (ch_num = 1) + 0x0000023C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR2 + PWM Channel Mode Register (ch_num = 2) + 0x00000240 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY2 + PWM Channel Duty Cycle Register (ch_num = 2) + 0x00000244 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD2 + PWM Channel Duty Cycle Update Register (ch_num = 2) + 0x00000248 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD2 + PWM Channel Period Register (ch_num = 2) + 0x0000024C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD2 + PWM Channel Period Update Register (ch_num = 2) + 0x00000250 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT2 + PWM Channel Counter Register (ch_num = 2) + 0x00000254 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT2 + PWM Channel Dead Time Register (ch_num = 2) + 0x00000258 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD2 + PWM Channel Dead Time Update Register (ch_num = 2) + 0x0000025C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + CMR3 + PWM Channel Mode Register (ch_num = 3) + 0x00000260 + 32 + read-write + 0x00000000 + + + CPRE + Channel Pre-scaler + 0 + 4 + read-write + + + MCK + Master clock + 0x0 + + + MCK_DIV_2 + Master clock/2 + 0x1 + + + MCK_DIV_4 + Master clock/4 + 0x2 + + + MCK_DIV_8 + Master clock/8 + 0x3 + + + MCK_DIV_16 + Master clock/16 + 0x4 + + + MCK_DIV_32 + Master clock/32 + 0x5 + + + MCK_DIV_64 + Master clock/64 + 0x6 + + + MCK_DIV_128 + Master clock/128 + 0x7 + + + MCK_DIV_256 + Master clock/256 + 0x8 + + + MCK_DIV_512 + Master clock/512 + 0x9 + + + MCK_DIV_1024 + Master clock/1024 + 0xA + + + CLKA + Clock A + 0xB + + + CLKB + Clock B + 0xC + + + + + CALG + Channel Alignment + 8 + 1 + read-write + + + CPOL + Channel Polarity + 9 + 1 + read-write + + + CES + Counter Event Selection + 10 + 1 + read-write + + + DTE + Dead-Time Generator Enable + 16 + 1 + read-write + + + DTHI + Dead-Time PWMHx Output Inverted + 17 + 1 + read-write + + + DTLI + Dead-Time PWMLx Output Inverted + 18 + 1 + read-write + + + + + CDTY3 + PWM Channel Duty Cycle Register (ch_num = 3) + 0x00000264 + 32 + read-write + 0x00000000 + + + CDTY + Channel Duty-Cycle + 0 + 24 + read-write + + + + + CDTYUPD3 + PWM Channel Duty Cycle Update Register (ch_num = 3) + 0x00000268 + 32 + write-only + + + CDTYUPD + Channel Duty-Cycle Update + 0 + 24 + write-only + + + + + CPRD3 + PWM Channel Period Register (ch_num = 3) + 0x0000026C + 32 + read-write + 0x00000000 + + + CPRD + Channel Period + 0 + 24 + read-write + + + + + CPRDUPD3 + PWM Channel Period Update Register (ch_num = 3) + 0x00000270 + 32 + write-only + + + CPRDUPD + Channel Period Update + 0 + 24 + write-only + + + + + CCNT3 + PWM Channel Counter Register (ch_num = 3) + 0x00000274 + 32 + read-only + 0x00000000 + + + CNT + Channel Counter Register + 0 + 24 + read-only + + + + + DT3 + PWM Channel Dead Time Register (ch_num = 3) + 0x00000278 + 32 + read-write + 0x00000000 + + + DTH + Dead-Time Value for PWMHx Output + 0 + 16 + read-write + + + DTL + Dead-Time Value for PWMLx Output + 16 + 16 + read-write + + + + + DTUPD3 + PWM Channel Dead Time Update Register (ch_num = 3) + 0x0000027C + 32 + write-only + + + DTHUPD + Dead-Time Value Update for PWMHx Output + 0 + 16 + write-only + + + DTLUPD + Dead-Time Value Update for PWMLx Output + 16 + 16 + write-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART0 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 0 + USART + USART0_ + 0x40024000 + + 0 + 0x4000 + registers + + + USART0 + 14 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART1 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 1 + USART + USART1_ + 0x40028000 + + 0 + 0x4000 + registers + + + USART1 + 15 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + USART2 + 6089Y + Universal Synchronous Asynchronous Receiver Transmitter 2 + USART + USART2_ + 0x4002C000 + + 0 + 0x4000 + registers + + + USART2 + 16 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + STTBRK + Start Break + 9 + 1 + write-only + + + STPBRK + Stop Break + 10 + 1 + write-only + + + STTTO + Start Time-out + 11 + 1 + write-only + + + SENDA + Send Address + 12 + 1 + write-only + + + RSTIT + Reset Iterations + 13 + 1 + write-only + + + RSTNACK + Reset Non Acknowledge + 14 + 1 + write-only + + + RETTO + Rearm Time-out + 15 + 1 + write-only + + + DTREN + Data Terminal Ready Enable + 16 + 1 + write-only + + + DTRDIS + Data Terminal Ready Disable + 17 + 1 + write-only + + + RTSEN + Request to Send Enable + 18 + 1 + write-only + + + RTSDIS + Request to Send Disable + 19 + 1 + write-only + + + + + CR_SPI_MODE + Control Register + SPI_MODE + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + FCS + Force SPI Chip Select + 18 + 1 + write-only + + + RCS + Release SPI Chip Select + 19 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + NORMAL + Normal mode + 0x0 + + + RS485 + RS485 + 0x1 + + + HW_HANDSHAKING + Hardware Handshaking + 0x2 + + + MODEM + Modem + 0x3 + + + IS07816_T_0 + IS07816 Protocol: T = 0 + 0x4 + + + IS07816_T_1 + IS07816 Protocol: T = 1 + 0x6 + + + IRDA + IrDA + 0x8 + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 5_BIT + Character length is 5 bits + 0x0 + + + 6_BIT + Character length is 6 bits + 0x1 + + + 7_BIT + Character length is 7 bits + 0x2 + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + SYNC + Synchronous Mode Select + 8 + 1 + read-write + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Parity forced to 0 (Space) + 0x2 + + + MARK + Parity forced to 1 (Mark) + 0x3 + + + NO + No parity + 0x4 + + + MULTIDROP + Multidrop mode + 0x6 + + + + + NBSTOP + Number of Stop Bits + 12 + 2 + read-write + + + 1_BIT + 1 stop bit + 0x0 + + + 1_5_BIT + 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + 0x1 + + + 2_BIT + 2 stop bits + 0x2 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo. Receiver input is connected to the TXD pin. + 0x1 + + + LOCAL_LOOPBACK + Local Loopback. Transmitter output is connected to the Receiver Input. + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback. RXD pin is internally connected to the TXD pin. + 0x3 + + + + + MSBF + Bit Order + 16 + 1 + read-write + + + MODE9 + 9-bit Character Length + 17 + 1 + read-write + + + CLKO + Clock Output Select + 18 + 1 + read-write + + + OVER + Oversampling Mode + 19 + 1 + read-write + + + INACK + Inhibit Non Acknowledge + 20 + 1 + read-write + + + DSNACK + Disable Successive NACK + 21 + 1 + read-write + + + VAR_SYNC + Variable Synchronization of Command/Data Sync Start Frame Delimiter + 22 + 1 + read-write + + + INVDATA + INverted Data + 23 + 1 + read-write + + + MAX_ITERATION + Maximum Number of Automatic Iteration + 24 + 3 + read-write + + + FILTER + Infrared Receive Line Filter + 28 + 1 + read-write + + + MAN + Manchester Encoder/Decoder Enable + 29 + 1 + read-write + + + MODSYNC + Manchester Synchronization Mode + 30 + 1 + read-write + + + ONEBIT + Start Frame Delimiter Selector + 31 + 1 + read-write + + + + + MR_SPI_MODE + Mode Register + SPI_MODE + 0x00000004 + 32 + read-write + + + USART_MODE + USART Mode of Operation + 0 + 4 + read-write + + + SPI_MASTER + SPI Master + 0xE + + + SPI_SLAVE + SPI Slave + 0xF + + + + + USCLKS + Clock Selection + 4 + 2 + read-write + + + MCK + Master Clock MCK is selected + 0x0 + + + DIV + Internal Clock Divided MCK/DIV (DIV=8) is selected + 0x1 + + + SCK + Serial Clock SLK is selected + 0x3 + + + + + CHRL + Character Length. + 6 + 2 + read-write + + + 8_BIT + Character length is 8 bits + 0x3 + + + + + CPHA + SPI Clock Phase + 8 + 1 + read-write + + + CPOL + SPI Clock Polarity + 16 + 1 + read-write + + + WRDBT + Wait Read Data Before Transfer + 20 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Enable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Enable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Enable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Enable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Enable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Enable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Enable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Enable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Enable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Enable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Enable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Enable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Enable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Enable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Enable + 24 + 1 + write-only + + + + + IER_SPI_MODE + Interrupt Enable Register + SPI_MODE + 0x00000008 + 32 + write-only + + + RXRDY + RXRDY Interrupt Enable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Enable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Enable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Enable + 10 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + RXBRK + Receiver Break Interrupt Disable + 2 + 1 + write-only + + + ENDRX + End of Receive Transfer Interrupt Disable (available in all USART modes of operation) + 3 + 1 + write-only + + + ENDTX + End of Transmit Interrupt Disable (available in all USART modes of operation) + 4 + 1 + write-only + + + OVRE + Overrun Error Interrupt Enable + 5 + 1 + write-only + + + FRAME + Framing Error Interrupt Disable + 6 + 1 + write-only + + + PARE + Parity Error Interrupt Disable + 7 + 1 + write-only + + + TIMEOUT + Time-out Interrupt Disable + 8 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + ITER + Max number of Repetitions Reached Interrupt Disable + 10 + 1 + write-only + + + TXBUFE + Buffer Empty Interrupt Disable (available in all USART modes of operation) + 11 + 1 + write-only + + + RXBUFF + Buffer Full Interrupt Disable (available in all USART modes of operation) + 12 + 1 + write-only + + + NACK + Non AcknowledgeInterrupt Disable + 13 + 1 + write-only + + + RIIC + Ring Indicator Input Change Disable + 16 + 1 + write-only + + + DSRIC + Data Set Ready Input Change Disable + 17 + 1 + write-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Disable + 18 + 1 + write-only + + + CTSIC + Clear to Send Input Change Interrupt Disable + 19 + 1 + write-only + + + MANE + Manchester Error Interrupt Disable + 24 + 1 + write-only + + + + + IDR_SPI_MODE + Interrupt Disable Register + SPI_MODE + 0x0000000C + 32 + write-only + + + RXRDY + RXRDY Interrupt Disable + 0 + 1 + write-only + + + TXRDY + TXRDY Interrupt Disable + 1 + 1 + write-only + + + OVRE + Overrun Error Interrupt Disable + 5 + 1 + write-only + + + TXEMPTY + TXEMPTY Interrupt Disable + 9 + 1 + write-only + + + UNRE + SPI Underrun Error Interrupt Disable + 10 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + RXBRK + Receiver Break Interrupt Mask + 2 + 1 + read-only + + + ENDRX + End of Receive Transfer Interrupt Mask (available in all USART modes of operation) + 3 + 1 + read-only + + + ENDTX + End of Transmit Interrupt Mask (available in all USART modes of operation) + 4 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + FRAME + Framing Error Interrupt Mask + 6 + 1 + read-only + + + PARE + Parity Error Interrupt Mask + 7 + 1 + read-only + + + TIMEOUT + Time-out Interrupt Mask + 8 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached Interrupt Mask + 10 + 1 + read-only + + + TXBUFE + Buffer Empty Interrupt Mask (available in all USART modes of operation) + 11 + 1 + read-only + + + RXBUFF + Buffer Full Interrupt Mask (available in all USART modes of operation) + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt Mask + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Mask + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Mask + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Interrupt Mask + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Interrupt Mask + 19 + 1 + read-only + + + MANE + Manchester Error Interrupt Mask + 24 + 1 + read-only + + + + + IMR_SPI_MODE + Interrupt Mask Register + SPI_MODE + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + RXRDY Interrupt Mask + 0 + 1 + read-only + + + TXRDY + TXRDY Interrupt Mask + 1 + 1 + read-only + + + OVRE + Overrun Error Interrupt Mask + 5 + 1 + read-only + + + TXEMPTY + TXEMPTY Interrupt Mask + 9 + 1 + read-only + + + UNRE + SPI Underrun Error Interrupt Mask + 10 + 1 + read-only + + + + + CSR + Channel Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + RXBRK + Break Received/End of Break + 2 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TIMEOUT + Receiver Time-out + 8 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + ITER + Max number of Repetitions Reached + 10 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 12 + 1 + read-only + + + NACK + Non AcknowledgeInterrupt + 13 + 1 + read-only + + + RIIC + Ring Indicator Input Change Flag + 16 + 1 + read-only + + + DSRIC + Data Set Ready Input Change Flag + 17 + 1 + read-only + + + DCDIC + Data Carrier Detect Input Change Flag + 18 + 1 + read-only + + + CTSIC + Clear to Send Input Change Flag + 19 + 1 + read-only + + + RI + Image of RI Input + 20 + 1 + read-only + + + DSR + Image of DSR Input + 21 + 1 + read-only + + + DCD + Image of DCD Input + 22 + 1 + read-only + + + CTS + Image of CTS Input + 23 + 1 + read-only + + + MANERR + Manchester Error + 24 + 1 + read-only + + + + + CSR_SPI_MODE + Channel Status Register + SPI_MODE + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + UNRE + Underrun Error + 10 + 1 + read-only + + + + + RHR + Receiver Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 9 + read-only + + + RXSYNH + Received Sync + 15 + 1 + read-only + + + + + THR + Transmitter Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 9 + write-only + + + TXSYNH + Sync Field to be transmitted + 15 + 1 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divider + 0 + 16 + read-write + + + FP + Fractional Part + 16 + 3 + read-write + + + + + RTOR + Receiver Time-out Register + 0x00000024 + 32 + read-write + 0x00000000 + + + TO + Time-out Value + 0 + 16 + read-write + + + + + TTGR + Transmitter Timeguard Register + 0x00000028 + 32 + read-write + 0x00000000 + + + TG + Timeguard Value + 0 + 8 + read-write + + + + + FIDI + FI DI Ratio Register + 0x00000040 + 32 + read-write + 0x00000174 + + + FI_DI_RATIO + FI Over DI Ratio Value + 0 + 11 + read-write + + + + + NER + Number of Errors Register + 0x00000044 + 32 + read-only + + + NB_ERRORS + Number of Errors + 0 + 8 + read-only + + + + + IF + IrDA Filter Register + 0x0000004C + 32 + read-write + 0x00000000 + + + IRDA_FILTER + IrDA Filter + 0 + 8 + read-write + + + + + MAN + Manchester Encoder Decoder Register + 0x00000050 + 32 + read-write + 0xB0011004 + + + TX_PL + Transmitter Preamble Length + 0 + 4 + read-write + + + TX_PP + Transmitter Preamble Pattern + 8 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + TX_MPOL + Transmitter Manchester Polarity + 12 + 1 + read-write + + + RX_PL + Receiver Preamble Length + 16 + 4 + read-write + + + RX_PP + Receiver Preamble Pattern detected + 24 + 2 + read-write + + + ALL_ONE + The preamble is composed of '1's + 0x0 + + + ALL_ZERO + The preamble is composed of '0's + 0x1 + + + ZERO_ONE + The preamble is composed of '01's + 0x2 + + + ONE_ZERO + The preamble is composed of '10's + 0x3 + + + + + RX_MPOL + Receiver Manchester Polarity + 28 + 1 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + DRIFT + Drift compensation + 30 + 1 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + VERSION + Version Register + 0x000000FC + 32 + read-only + + + VERSION + Harware Module Version + 0 + 12 + read-only + + + MFN + Metal Fix Number + 16 + 3 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + UDP + 6083V + USB Device Port + UDP_ + 0x40034000 + + 0 + 0x4000 + registers + + + UDP + 34 + + + + FRM_NUM + Frame Number Register + 0x00000000 + 32 + read-only + 0x00000000 + + + FRM_NUM + Frame Number as Defined in the Packet Field Formats + 0 + 11 + read-only + + + FRM_ERR + Frame Error + 16 + 1 + read-only + + + FRM_OK + Frame OK + 17 + 1 + read-only + + + + + GLB_STAT + Global State Register + 0x00000004 + 32 + read-write + 0x00000010 + + + FADDEN + Function Address Enable + 0 + 1 + read-write + + + CONFG + Configured + 1 + 1 + read-write + + + ESR + Enable Send Resume + 2 + 1 + read-write + + + RSMINPR + 3 + 1 + read-write + + + RMWUPE + Remote Wake Up Enable + 4 + 1 + read-write + + + + + FADDR + Function Address Register + 0x00000008 + 32 + read-write + 0x00000100 + + + FADD + Function Address Value + 0 + 7 + read-write + + + FEN + Function Enable + 8 + 1 + read-write + + + + + IER + Interrupt Enable Register + 0x00000010 + 32 + write-only + + + EP0INT + Enable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Enable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Enable Endpoint 2Interrupt + 2 + 1 + write-only + + + EP3INT + Enable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Enable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Enable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Enable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Enable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Enable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Enable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Enable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Enable UDP bus Wakeup Interrupt + 13 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000014 + 32 + write-only + + + EP0INT + Disable Endpoint 0 Interrupt + 0 + 1 + write-only + + + EP1INT + Disable Endpoint 1 Interrupt + 1 + 1 + write-only + + + EP2INT + Disable Endpoint 2 Interrupt + 2 + 1 + write-only + + + EP3INT + Disable Endpoint 3 Interrupt + 3 + 1 + write-only + + + EP4INT + Disable Endpoint 4 Interrupt + 4 + 1 + write-only + + + EP5INT + Disable Endpoint 5 Interrupt + 5 + 1 + write-only + + + EP6INT + Disable Endpoint 6 Interrupt + 6 + 1 + write-only + + + EP7INT + Disable Endpoint 7 Interrupt + 7 + 1 + write-only + + + RXSUSP + Disable UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Disable UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Disable Start Of Frame Interrupt + 11 + 1 + write-only + + + WAKEUP + Disable USB Bus Interrupt + 13 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000018 + 32 + read-only + 0x00001200 + + + EP0INT + Mask Endpoint 0 Interrupt + 0 + 1 + read-only + + + EP1INT + Mask Endpoint 1 Interrupt + 1 + 1 + read-only + + + EP2INT + Mask Endpoint 2 Interrupt + 2 + 1 + read-only + + + EP3INT + Mask Endpoint 3 Interrupt + 3 + 1 + read-only + + + EP4INT + Mask Endpoint 4 Interrupt + 4 + 1 + read-only + + + EP5INT + Mask Endpoint 5 Interrupt + 5 + 1 + read-only + + + EP6INT + Mask Endpoint 6 Interrupt + 6 + 1 + read-only + + + EP7INT + Mask Endpoint 7 Interrupt + 7 + 1 + read-only + + + RXSUSP + Mask UDP Suspend Interrupt + 8 + 1 + read-only + + + RXRSM + Mask UDP Resume Interrupt. + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Mask Start Of Frame Interrupt + 11 + 1 + read-only + + + BIT12 + UDP_IMR Bit 12 + 12 + 1 + read-only + + + WAKEUP + USB Bus WAKEUP Interrupt + 13 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000001C + 32 + read-only + + + EP0INT + Endpoint 0 Interrupt Status + 0 + 1 + read-only + + + EP1INT + Endpoint 1 Interrupt Status + 1 + 1 + read-only + + + EP2INT + Endpoint 2 Interrupt Status + 2 + 1 + read-only + + + EP3INT + Endpoint 3 Interrupt Status + 3 + 1 + read-only + + + EP4INT + Endpoint 4 Interrupt Status + 4 + 1 + read-only + + + EP5INT + Endpoint 5 Interrupt Status + 5 + 1 + read-only + + + EP6INT + Endpoint 6 Interrupt Status + 6 + 1 + read-only + + + EP7INT + Endpoint 7Interrupt Status + 7 + 1 + read-only + + + RXSUSP + UDP Suspend Interrupt Status + 8 + 1 + read-only + + + RXRSM + UDP Resume Interrupt Status + 9 + 1 + read-only + + + EXTRSM + 10 + 1 + read-only + + + SOFINT + Start of Frame Interrupt Status + 11 + 1 + read-only + + + ENDBUSRES + End of BUS Reset Interrupt Status + 12 + 1 + read-only + + + WAKEUP + UDP Resume Interrupt Status + 13 + 1 + read-only + + + + + ICR + Interrupt Clear Register + 0x00000020 + 32 + write-only + + + RXSUSP + Clear UDP Suspend Interrupt + 8 + 1 + write-only + + + RXRSM + Clear UDP Resume Interrupt + 9 + 1 + write-only + + + EXTRSM + 10 + 1 + write-only + + + SOFINT + Clear Start Of Frame Interrupt + 11 + 1 + write-only + + + ENDBUSRES + Clear End of Bus Reset Interrupt + 12 + 1 + write-only + + + WAKEUP + Clear Wakeup Interrupt + 13 + 1 + write-only + + + + + RST_EP + Reset Endpoint Register + 0x00000028 + 32 + read-write + 0x00000000 + + + EP0 + Reset Endpoint 0 + 0 + 1 + read-write + + + EP1 + Reset Endpoint 1 + 1 + 1 + read-write + + + EP2 + Reset Endpoint 2 + 2 + 1 + read-write + + + EP3 + Reset Endpoint 3 + 3 + 1 + read-write + + + EP4 + Reset Endpoint 4 + 4 + 1 + read-write + + + EP5 + Reset Endpoint 5 + 5 + 1 + read-write + + + EP6 + Reset Endpoint 6 + 6 + 1 + read-write + + + EP7 + Reset Endpoint 7 + 7 + 1 + read-write + + + + + 8 + 4 + 0-7 + CSR[%s] + Endpoint Control and Status Register + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + STALLSENT + Stall Sent + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + BULK_OUT + Bulk OUT + 0x2 + + + INT_OUT + Interrupt OUT + 0x3 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_IN + Bulk IN + 0x6 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + CSR0_ISOENDPT + Endpoint Control and Status Register + ISOENDPT + 0x00000030 + 32 + read-write + + + TXCOMP + Generates an IN Packet with Data Previously Written in the DPR + 0 + 1 + read-write + + + RX_DATA_BK0 + Receive Data Bank 0 + 1 + 1 + read-write + + + RXSETUP + Received Setup + 2 + 1 + read-write + + + ISOERROR + A CRC error has been detected in an isochronous transfer + 3 + 1 + read-write + + + TXPKTRDY + Transmit Packet Ready + 4 + 1 + read-write + + + FORCESTALL + Force Stall (used by Control, Bulk and Isochronous Endpoints) + 5 + 1 + read-write + + + RX_DATA_BK1 + Receive Data Bank 1 (only used by endpoints with ping-pong attributes) + 6 + 1 + read-write + + + DIR + Transfer Direction (only available for control endpoints) + 7 + 1 + read-write + + + EPTYPE + Endpoint Type + 8 + 3 + read-write + + + CTRL + Control + 0x0 + + + ISO_OUT + Isochronous OUT + 0x1 + + + ISO_IN + Isochronous IN + 0x5 + + + BULK_OUT + Bulk OUT + 0x2 + + + BULK_IN + Bulk IN + 0x6 + + + INT_OUT + Interrupt OUT + 0x3 + + + INT_IN + Interrupt IN + 0x7 + + + + + DTGLE + Data Toggle + 11 + 1 + read-write + + + EPEDS + Endpoint Enable Disable + 15 + 1 + read-write + + + RXBYTECNT + Number of Bytes Available in the FIFO + 16 + 11 + read-write + + + + + 8 + 4 + 0-7 + FDR[%s] + Endpoint FIFO Data Register + 0x00000050 + 32 + read-write + + + FIFO_DATA + FIFO Data Value + 0 + 8 + read-write + + + + + TXVC + Transceiver Control Register + 0x00000074 + 32 + read-write + 0x00000100 + + + TXVDIS + Transceiver Disable + 8 + 1 + read-write + + + PUON + Pull-up On + 9 + 1 + read-write + + + + + + + ADC + 6489I + Analog-to-Digital Converter + ADC_ + 0x40038000 + + 0 + 0x4000 + registers + + + ADC + 29 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + START + Start Conversion + 1 + 1 + write-only + + + AUTOCAL + Automatic Calibration of ADC + 3 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + Hardware triggers are disabled. Starting a conversion is only possible by software. + 0 + + + EN + Hardware trigger selected by TRGSEL field is enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + ADC_TRIG0 + External trigger + 0x0 + + + ADC_TRIG1 + TIO Output of the Timer Counter Channel 0 + 0x1 + + + ADC_TRIG2 + TIO Output of the Timer Counter Channel 1 + 0x2 + + + ADC_TRIG3 + TIO Output of the Timer Counter Channel 2 + 0x3 + + + ADC_TRIG4 + PWM Event Line 0 + 0x4 + + + ADC_TRIG5 + PWM Event Line 1 + 0x5 + + + + + LOWRES + Resolution + 4 + 1 + read-write + + + BITS_12 + 12-bit resolution + 0 + + + BITS_10 + 10-bit resolution + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + NORMAL + Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions + 0 + + + SLEEP + Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions + 1 + + + + + FWUP + Fast Wake Up + 6 + 1 + read-write + + + OFF + Normal Sleep Mode: The sleep mode is defined by the SLEEP bit + 0 + + + ON + Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF + 1 + + + + + FREERUN + Free Run Mode + 7 + 1 + read-write + + + OFF + Normal Mode + 0 + + + ON + Free Run Mode: Never wait for any trigger. + 1 + + + + + PRESCAL + Prescaler Rate Selection + 8 + 8 + read-write + + + STARTUP + Start Up Time + 16 + 4 + read-write + + + SUT0 + 0 periods of ADCClock + 0x0 + + + SUT8 + 8 periods of ADCClock + 0x1 + + + SUT16 + 16 periods of ADCClock + 0x2 + + + SUT24 + 24 periods of ADCClock + 0x3 + + + SUT64 + 64 periods of ADCClock + 0x4 + + + SUT80 + 80 periods of ADCClock + 0x5 + + + SUT96 + 96 periods of ADCClock + 0x6 + + + SUT112 + 112 periods of ADCClock + 0x7 + + + SUT512 + 512 periods of ADCClock + 0x8 + + + SUT576 + 576 periods of ADCClock + 0x9 + + + SUT640 + 640 periods of ADCClock + 0xA + + + SUT704 + 704 periods of ADCClock + 0xB + + + SUT768 + 768 periods of ADCClock + 0xC + + + SUT832 + 832 periods of ADCClock + 0xD + + + SUT896 + 896 periods of ADCClock + 0xE + + + SUT960 + 960 periods of ADCClock + 0xF + + + + + SETTLING + Analog Settling Time + 20 + 2 + read-write + + + AST3 + 3 periods of ADCClock + 0x0 + + + AST5 + 5 periods of ADCClock + 0x1 + + + AST9 + 9 periods of ADCClock + 0x2 + + + AST17 + 17 periods of ADCClock + 0x3 + + + + + ANACH + Analog Change + 23 + 1 + read-write + + + NONE + No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels + 0 + + + ALLOWED + Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers + 1 + + + + + TRACKTIM + Tracking Time + 24 + 4 + read-write + + + TRANSFER + Transfer Period + 28 + 2 + read-write + + + USEQ + Use Sequence Enable + 31 + 1 + read-write + + + NUM_ORDER + Normal Mode: The controller converts channels in a simple numeric order. + 0 + + + REG_ORDER + User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. + 1 + + + + + + + SEQR1 + Channel Sequence Register 1 + 0x00000008 + 32 + read-write + 0x00000000 + + + USCH1 + User Sequence Number 1 + 0 + 3 + read-write + + + USCH2 + User Sequence Number 2 + 4 + 3 + read-write + + + USCH3 + User Sequence Number 3 + 8 + 3 + read-write + + + USCH4 + User Sequence Number 4 + 12 + 3 + read-write + + + USCH5 + User Sequence Number 5 + 16 + 3 + read-write + + + USCH6 + User Sequence Number 6 + 20 + 3 + read-write + + + USCH7 + User Sequence Number 7 + 24 + 3 + read-write + + + USCH8 + User Sequence Number 8 + 28 + 3 + read-write + + + + + SEQR2 + Channel Sequence Register 2 + 0x0000000C + 32 + read-write + 0x00000000 + + + USCH9 + User Sequence Number 9 + 0 + 3 + read-write + + + USCH10 + User Sequence Number 10 + 4 + 3 + read-write + + + USCH11 + User Sequence Number 11 + 8 + 3 + read-write + + + USCH12 + User Sequence Number 12 + 12 + 3 + read-write + + + USCH13 + User Sequence Number 13 + 16 + 3 + read-write + + + USCH14 + User Sequence Number 14 + 20 + 3 + read-write + + + USCH15 + User Sequence Number 15 + 24 + 3 + read-write + + + USCH16 + User Sequence Number 16 + 28 + 3 + read-write + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + CH2 + Channel 2 Enable + 2 + 1 + write-only + + + CH3 + Channel 3 Enable + 3 + 1 + write-only + + + CH4 + Channel 4 Enable + 4 + 1 + write-only + + + CH5 + Channel 5 Enable + 5 + 1 + write-only + + + CH6 + Channel 6 Enable + 6 + 1 + write-only + + + CH7 + Channel 7 Enable + 7 + 1 + write-only + + + CH8 + Channel 8 Enable + 8 + 1 + write-only + + + CH9 + Channel 9 Enable + 9 + 1 + write-only + + + CH10 + Channel 10 Enable + 10 + 1 + write-only + + + CH11 + Channel 11 Enable + 11 + 1 + write-only + + + CH12 + Channel 12 Enable + 12 + 1 + write-only + + + CH13 + Channel 13 Enable + 13 + 1 + write-only + + + CH14 + Channel 14 Enable + 14 + 1 + write-only + + + CH15 + Channel 15 Enable + 15 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + CH2 + Channel 2 Disable + 2 + 1 + write-only + + + CH3 + Channel 3 Disable + 3 + 1 + write-only + + + CH4 + Channel 4 Disable + 4 + 1 + write-only + + + CH5 + Channel 5 Disable + 5 + 1 + write-only + + + CH6 + Channel 6 Disable + 6 + 1 + write-only + + + CH7 + Channel 7 Disable + 7 + 1 + write-only + + + CH8 + Channel 8 Disable + 8 + 1 + write-only + + + CH9 + Channel 9 Disable + 9 + 1 + write-only + + + CH10 + Channel 10 Disable + 10 + 1 + write-only + + + CH11 + Channel 11 Disable + 11 + 1 + write-only + + + CH12 + Channel 12 Disable + 12 + 1 + write-only + + + CH13 + Channel 13 Disable + 13 + 1 + write-only + + + CH14 + Channel 14 Disable + 14 + 1 + write-only + + + CH15 + Channel 15 Disable + 15 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + CH2 + Channel 2 Status + 2 + 1 + read-only + + + CH3 + Channel 3 Status + 3 + 1 + read-only + + + CH4 + Channel 4 Status + 4 + 1 + read-only + + + CH5 + Channel 5 Status + 5 + 1 + read-only + + + CH6 + Channel 6 Status + 6 + 1 + read-only + + + CH7 + Channel 7 Status + 7 + 1 + read-only + + + CH8 + Channel 8 Status + 8 + 1 + read-only + + + CH9 + Channel 9 Status + 9 + 1 + read-only + + + CH10 + Channel 10 Status + 10 + 1 + read-only + + + CH11 + Channel 11 Status + 11 + 1 + read-only + + + CH12 + Channel 12 Status + 12 + 1 + read-only + + + CH13 + Channel 13 Status + 13 + 1 + read-only + + + CH14 + Channel 14 Status + 14 + 1 + read-only + + + CH15 + Channel 15 Status + 15 + 1 + read-only + + + + + LCDR + Last Converted Data Register + 0x00000020 + 32 + read-only + 0x00000000 + + + LDATA + Last Data Converted + 0 + 12 + read-only + + + CHNB + Channel Number + 12 + 4 + read-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Enable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Enable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Enable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Enable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Enable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Enable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Enable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Enable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Enable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Enable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Enable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Enable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Enable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Enable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Enable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Enable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Enable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Enable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Enable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Enable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Enable + 28 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + EOC0 + End of Conversion Interrupt Disable 0 + 0 + 1 + write-only + + + EOC1 + End of Conversion Interrupt Disable 1 + 1 + 1 + write-only + + + EOC2 + End of Conversion Interrupt Disable 2 + 2 + 1 + write-only + + + EOC3 + End of Conversion Interrupt Disable 3 + 3 + 1 + write-only + + + EOC4 + End of Conversion Interrupt Disable 4 + 4 + 1 + write-only + + + EOC5 + End of Conversion Interrupt Disable 5 + 5 + 1 + write-only + + + EOC6 + End of Conversion Interrupt Disable 6 + 6 + 1 + write-only + + + EOC7 + End of Conversion Interrupt Disable 7 + 7 + 1 + write-only + + + EOC8 + End of Conversion Interrupt Disable 8 + 8 + 1 + write-only + + + EOC9 + End of Conversion Interrupt Disable 9 + 9 + 1 + write-only + + + EOC10 + End of Conversion Interrupt Disable 10 + 10 + 1 + write-only + + + EOC11 + End of Conversion Interrupt Disable 11 + 11 + 1 + write-only + + + EOC12 + End of Conversion Interrupt Disable 12 + 12 + 1 + write-only + + + EOC13 + End of Conversion Interrupt Disable 13 + 13 + 1 + write-only + + + EOC14 + End of Conversion Interrupt Disable 14 + 14 + 1 + write-only + + + EOC15 + End of Conversion Interrupt Disable 15 + 15 + 1 + write-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + write-only + + + DRDY + Data Ready Interrupt Disable + 24 + 1 + write-only + + + GOVRE + General Overrun Error Interrupt Disable + 25 + 1 + write-only + + + COMPE + Comparison Event Interrupt Disable + 26 + 1 + write-only + + + ENDRX + End of Receive Buffer Interrupt Disable + 27 + 1 + write-only + + + RXBUFF + Receive Buffer Full Interrupt Disable + 28 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion Interrupt Mask 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion Interrupt Mask 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion Interrupt Mask 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion Interrupt Mask 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion Interrupt Mask 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion Interrupt Mask 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion Interrupt Mask 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion Interrupt Mask 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion Interrupt Mask 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion Interrupt Mask 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion Interrupt Mask 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion Interrupt Mask 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion Interrupt Mask 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion Interrupt Mask 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion Interrupt Mask 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion Interrupt Mask 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready Interrupt Mask + 24 + 1 + read-only + + + GOVRE + General Overrun Error Interrupt Mask + 25 + 1 + read-only + + + COMPE + Comparison Event Interrupt Mask + 26 + 1 + read-only + + + ENDRX + End of Receive Buffer Interrupt Mask + 27 + 1 + read-only + + + RXBUFF + Receive Buffer Full Interrupt Mask + 28 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + EOC0 + End of Conversion 0 + 0 + 1 + read-only + + + EOC1 + End of Conversion 1 + 1 + 1 + read-only + + + EOC2 + End of Conversion 2 + 2 + 1 + read-only + + + EOC3 + End of Conversion 3 + 3 + 1 + read-only + + + EOC4 + End of Conversion 4 + 4 + 1 + read-only + + + EOC5 + End of Conversion 5 + 5 + 1 + read-only + + + EOC6 + End of Conversion 6 + 6 + 1 + read-only + + + EOC7 + End of Conversion 7 + 7 + 1 + read-only + + + EOC8 + End of Conversion 8 + 8 + 1 + read-only + + + EOC9 + End of Conversion 9 + 9 + 1 + read-only + + + EOC10 + End of Conversion 10 + 10 + 1 + read-only + + + EOC11 + End of Conversion 11 + 11 + 1 + read-only + + + EOC12 + End of Conversion 12 + 12 + 1 + read-only + + + EOC13 + End of Conversion 13 + 13 + 1 + read-only + + + EOC14 + End of Conversion 14 + 14 + 1 + read-only + + + EOC15 + End of Conversion 15 + 15 + 1 + read-only + + + EOCAL + End of Calibration Sequence + 23 + 1 + read-only + + + DRDY + Data Ready + 24 + 1 + read-only + + + GOVRE + General Overrun Error + 25 + 1 + read-only + + + COMPE + Comparison Error + 26 + 1 + read-only + + + ENDRX + End of RX Buffer + 27 + 1 + read-only + + + RXBUFF + RX Buffer Full + 28 + 1 + read-only + + + + + OVER + Overrun Status Register + 0x0000003C + 32 + read-only + 0x00000000 + + + OVRE0 + Overrun Error 0 + 0 + 1 + read-only + + + OVRE1 + Overrun Error 1 + 1 + 1 + read-only + + + OVRE2 + Overrun Error 2 + 2 + 1 + read-only + + + OVRE3 + Overrun Error 3 + 3 + 1 + read-only + + + OVRE4 + Overrun Error 4 + 4 + 1 + read-only + + + OVRE5 + Overrun Error 5 + 5 + 1 + read-only + + + OVRE6 + Overrun Error 6 + 6 + 1 + read-only + + + OVRE7 + Overrun Error 7 + 7 + 1 + read-only + + + OVRE8 + Overrun Error 8 + 8 + 1 + read-only + + + OVRE9 + Overrun Error 9 + 9 + 1 + read-only + + + OVRE10 + Overrun Error 10 + 10 + 1 + read-only + + + OVRE11 + Overrun Error 11 + 11 + 1 + read-only + + + OVRE12 + Overrun Error 12 + 12 + 1 + read-only + + + OVRE13 + Overrun Error 13 + 13 + 1 + read-only + + + OVRE14 + Overrun Error 14 + 14 + 1 + read-only + + + OVRE15 + Overrun Error 15 + 15 + 1 + read-only + + + + + EMR + Extended Mode Register + 0x00000040 + 32 + read-write + 0x00000000 + + + CMPMODE + Comparison Mode + 0 + 2 + read-write + + + LOW + Generates an event when the converted data is lower than the low threshold of the window. + 0x0 + + + HIGH + Generates an event when the converted data is higher than the high threshold of the window. + 0x1 + + + IN + Generates an event when the converted data is in the comparison window. + 0x2 + + + OUT + Generates an event when the converted data is out of the comparison window. + 0x3 + + + + + CMPSEL + Comparison Selected Channel + 4 + 4 + read-write + + + CMPALL + Compare All Channels + 9 + 1 + read-write + + + CMPFILTER + Compare Event Filtering + 12 + 2 + read-write + + + TAG + TAG of ADC_LDCR register + 24 + 1 + read-write + + + + + CWR + Compare Window Register + 0x00000044 + 32 + read-write + 0x00000000 + + + LOWTHRES + Low Threshold + 0 + 12 + read-write + + + HIGHTHRES + High Threshold + 16 + 12 + read-write + + + + + CGR + Channel Gain Register + 0x00000048 + 32 + read-write + 0x00000000 + + + GAIN0 + Gain for channel 0 + 0 + 2 + read-write + + + GAIN1 + Gain for channel 1 + 2 + 2 + read-write + + + GAIN2 + Gain for channel 2 + 4 + 2 + read-write + + + GAIN3 + Gain for channel 3 + 6 + 2 + read-write + + + GAIN4 + Gain for channel 4 + 8 + 2 + read-write + + + GAIN5 + Gain for channel 5 + 10 + 2 + read-write + + + GAIN6 + Gain for channel 6 + 12 + 2 + read-write + + + GAIN7 + Gain for channel 7 + 14 + 2 + read-write + + + GAIN8 + Gain for channel 8 + 16 + 2 + read-write + + + GAIN9 + Gain for channel 9 + 18 + 2 + read-write + + + GAIN10 + Gain for channel 10 + 20 + 2 + read-write + + + GAIN11 + Gain for channel 11 + 22 + 2 + read-write + + + GAIN12 + Gain for channel 12 + 24 + 2 + read-write + + + GAIN13 + Gain for channel 13 + 26 + 2 + read-write + + + GAIN14 + Gain for channel 14 + 28 + 2 + read-write + + + GAIN15 + Gain for channel 15 + 30 + 2 + read-write + + + + + COR + Channel Offset Register + 0x0000004C + 32 + read-write + 0x00000000 + + + OFF0 + Offset for channel 0 + 0 + 1 + read-write + + + OFF1 + Offset for channel 1 + 1 + 1 + read-write + + + OFF2 + Offset for channel 2 + 2 + 1 + read-write + + + OFF3 + Offset for channel 3 + 3 + 1 + read-write + + + OFF4 + Offset for channel 4 + 4 + 1 + read-write + + + OFF5 + Offset for channel 5 + 5 + 1 + read-write + + + OFF6 + Offset for channel 6 + 6 + 1 + read-write + + + OFF7 + Offset for channel 7 + 7 + 1 + read-write + + + OFF8 + Offset for channel 8 + 8 + 1 + read-write + + + OFF9 + Offset for channel 9 + 9 + 1 + read-write + + + OFF10 + Offset for channel 10 + 10 + 1 + read-write + + + OFF11 + Offset for channel 11 + 11 + 1 + read-write + + + OFF12 + Offset for channel 12 + 12 + 1 + read-write + + + OFF13 + Offset for channel 13 + 13 + 1 + read-write + + + OFF14 + Offset for channel 14 + 14 + 1 + read-write + + + OFF15 + Offset for channel 15 + 15 + 1 + read-write + + + DIFF0 + Differential inputs for channel 0 + 16 + 1 + read-write + + + DIFF1 + Differential inputs for channel 1 + 17 + 1 + read-write + + + DIFF2 + Differential inputs for channel 2 + 18 + 1 + read-write + + + DIFF3 + Differential inputs for channel 3 + 19 + 1 + read-write + + + DIFF4 + Differential inputs for channel 4 + 20 + 1 + read-write + + + DIFF5 + Differential inputs for channel 5 + 21 + 1 + read-write + + + DIFF6 + Differential inputs for channel 6 + 22 + 1 + read-write + + + DIFF7 + Differential inputs for channel 7 + 23 + 1 + read-write + + + DIFF8 + Differential inputs for channel 8 + 24 + 1 + read-write + + + DIFF9 + Differential inputs for channel 9 + 25 + 1 + read-write + + + DIFF10 + Differential inputs for channel 10 + 26 + 1 + read-write + + + DIFF11 + Differential inputs for channel 11 + 27 + 1 + read-write + + + DIFF12 + Differential inputs for channel 12 + 28 + 1 + read-write + + + DIFF13 + Differential inputs for channel 13 + 29 + 1 + read-write + + + DIFF14 + Differential inputs for channel 14 + 30 + 1 + read-write + + + DIFF15 + Differential inputs for channel 15 + 31 + 1 + read-write + + + + + 15 + 4 + 0-14 + CDR[%s] + Channel Data Register + 0x00000050 + 32 + read-only + + + DATA + Converted Data + 0 + 12 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000100 + + + TSON + Temperature Sensor On + 4 + 1 + read-write + + + IBCTL + ADC Bias Current Control + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + DACC + 6461F + Digital-to-Analog Converter Controller + DACC_ + 0x4003C000 + + 0 + 0x4000 + registers + + + DACC + 30 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + TRGEN + Trigger Enable + 0 + 1 + read-write + + + DIS + External trigger mode disabled. DACC in free running mode. + 0 + + + EN + External trigger mode enabled. + 1 + + + + + TRGSEL + Trigger Selection + 1 + 3 + read-write + + + WORD + Word Transfer + 4 + 1 + read-write + + + HALF + Half-Word transfer + 0 + + + WORD + Word Transfer + 1 + + + + + SLEEP + Sleep Mode + 5 + 1 + read-write + + + FASTWKUP + Fast Wake up Mode + 6 + 1 + read-write + + + REFRESH + Refresh Period + 8 + 8 + read-write + + + USER_SEL + User Channel Selection + 16 + 2 + read-write + + + CHANNEL0 + Channel 0 + 0 + + + CHANNEL1 + Channel 1 + 1 + + + + + TAG + Tag Selection Mode + 20 + 1 + read-write + + + DIS + Tag selection mode disabled. Using USER_SEL to select the channel for the conversion. + 0 + + + EN + Tag selection mode enabled + 1 + + + + + MAXS + Max Speed Mode + 21 + 1 + read-write + + + NORMAL + Normal Mode + 0 + + + MAXIMUM + Max Speed Mode enabled + 1 + + + + + STARTUP + Startup Time Selection + 24 + 6 + read-write + + + 0 + 0 periods of DACClock + 0x0 + + + 8 + 8 periods of DACClock + 0x1 + + + 16 + 16 periods of DACClock + 0x2 + + + 24 + 24 periods of DACClock + 0x3 + + + 64 + 64 periods of DACClock + 0x4 + + + 80 + 80 periods of DACClock + 0x5 + + + 96 + 96 periods of DACClock + 0x6 + + + 112 + 112 periods of DACClock + 0x7 + + + 512 + 512 periods of DACClock + 0x8 + + + 576 + 576 periods of DACClock + 0x9 + + + 640 + 640 periods of DACClock + 0xA + + + 704 + 704 periods of DACClock + 0xB + + + 768 + 768 periods of DACClock + 0xC + + + 832 + 832 periods of DACClock + 0xD + + + 896 + 896 periods of DACClock + 0xE + + + 960 + 960 periods of DACClock + 0xF + + + 1024 + 1024 periods of DACClock + 0x10 + + + 1088 + 1088 periods of DACClock + 0x11 + + + 1152 + 1152 periods of DACClock + 0x12 + + + 1216 + 1216 periods of DACClock + 0x13 + + + 1280 + 1280 periods of DACClock + 0x14 + + + 1344 + 1344 periods of DACClock + 0x15 + + + 1408 + 1408 periods of DACClock + 0x16 + + + 1472 + 1472 periods of DACClock + 0x17 + + + 1536 + 1536 periods of DACClock + 0x18 + + + 1600 + 1600 periods of DACClock + 0x19 + + + 1664 + 1664 periods of DACClock + 0x1A + + + 1728 + 1728 periods of DACClock + 0x1B + + + 1792 + 1792 periods of DACClock + 0x1C + + + 1856 + 1856 periods of DACClock + 0x1D + + + 1920 + 1920 periods of DACClock + 0x1E + + + 1984 + 1984 periods of DACClock + 0x1F + + + + + + + CHER + Channel Enable Register + 0x00000010 + 32 + write-only + + + CH0 + Channel 0 Enable + 0 + 1 + write-only + + + CH1 + Channel 1 Enable + 1 + 1 + write-only + + + + + CHDR + Channel Disable Register + 0x00000014 + 32 + write-only + + + CH0 + Channel 0 Disable + 0 + 1 + write-only + + + CH1 + Channel 1 Disable + 1 + 1 + write-only + + + + + CHSR + Channel Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + CH0 + Channel 0 Status + 0 + 1 + read-only + + + CH1 + Channel 1 Status + 1 + 1 + read-only + + + + + CDR + Conversion Data Register + 0x00000020 + 32 + write-only + 0x00000000 + + + DATA + Data to Convert + 0 + 32 + write-only + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Enable + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Enable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Enable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Enable + 3 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + TXRDY + Transmit Ready Interrupt Disable. + 0 + 1 + write-only + + + EOC + End of Conversion Interrupt Disable + 1 + 1 + write-only + + + ENDTX + End of Transmit Buffer Interrupt Disable + 2 + 1 + write-only + + + TXBUFE + Transmit Buffer Empty Interrupt Disable + 3 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Mask + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Mask + 1 + 1 + read-only + + + ENDTX + End of Transmit Buffer Interrupt Mask + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty Interrupt Mask + 3 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + TXRDY + Transmit Ready Interrupt Flag + 0 + 1 + read-only + + + EOC + End of Conversion Interrupt Flag + 1 + 1 + read-only + + + ENDTX + End of DMA Interrupt Flag + 2 + 1 + read-only + + + TXBUFE + Transmit Buffer Empty + 3 + 1 + read-only + + + + + ACR + Analog Current Register + 0x00000094 + 32 + read-write + 0x00000000 + + + IBCTLCH0 + Analog Output Current Control + 0 + 2 + read-write + + + IBCTLCH1 + Analog Output Current Control + 2 + 2 + read-write + + + IBCTLDACCORE + Bias Current Control for DAC Core + 8 + 2 + read-write + + + + + WPMR + Write Protect Mode register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write protection error + 0 + 1 + read-only + + + WPROTADDR + Write protection error address + 8 + 8 + read-only + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + ACC + 6490C + Analog Comparator Controller + ACC_ + 0x40040000 + + 0 + 0x4000 + registers + + + ACC + 33 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + SWRST + SoftWare ReSeT + 0 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SELMINUS + SELection for MINUS comparator input + 0 + 3 + read-write + + + TS + SelectTS + 0x0 + + + ADVREF + Select ADVREF + 0x1 + + + DAC0 + Select DAC0 + 0x2 + + + DAC1 + Select DAC1 + 0x3 + + + AD0 + Select AD0 + 0x4 + + + AD1 + Select AD1 + 0x5 + + + AD2 + Select AD2 + 0x6 + + + AD3 + Select AD3 + 0x7 + + + + + SELPLUS + SELection for PLUS comparator input + 4 + 3 + read-write + + + AD0 + Select AD0 + 0x0 + + + AD1 + Select AD1 + 0x1 + + + AD2 + Select AD2 + 0x2 + + + AD3 + Select AD3 + 0x3 + + + AD4 + Select AD4 + 0x4 + + + AD5 + Select AD5 + 0x5 + + + AD6 + Select AD6 + 0x6 + + + AD7 + Select AD7 + 0x7 + + + + + ACEN + Analog Comparator ENable + 8 + 1 + read-write + + + DIS + Analog Comparator Disabled. + 0 + + + EN + Analog Comparator Enabled. + 1 + + + + + EDGETYP + EDGE TYPe + 9 + 2 + read-write + + + RISING + only rising edge of comparator output + 0x0 + + + FALLING + falling edge of comparator output + 0x1 + + + ANY + any edge of comparator output + 0x2 + + + + + INV + INVert comparator output + 12 + 1 + read-write + + + DIS + Analog Comparator output is directly processed. + 0 + + + EN + Analog Comparator output is inverted prior to being processed. + 1 + + + + + SELFS + SELection of Fault Source + 13 + 1 + read-write + + + CF + the CF flag is used to drive the FAULT output. + 0 + + + OUTPUT + the output of the Analog Comparator flag is used to drive the FAULT output. + 1 + + + + + FE + Fault Enable + 14 + 1 + read-write + + + DIS + the FAULT output is tied to 0. + 0 + + + EN + the FAULT output is driven by the signal defined by SELFS. + 1 + + + + + + + IER + Interrupt Enable Register + 0x00000024 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000028 + 32 + write-only + + + CE + Comparison Edge + 0 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x0000002C + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x00000030 + 32 + read-only + 0x00000000 + + + CE + Comparison Edge + 0 + 1 + read-only + + + SCO + Synchronized Comparator Output + 1 + 1 + read-only + + + MASK + 31 + 1 + read-only + + + + + ACR + Analog Control Register + 0x00000094 + 32 + read-write + 0x00000000 + + + ISEL + Current SELection + 0 + 1 + read-write + + + LOPW + low power option. + 0 + + + HISP + high speed option. + 1 + + + + + HYST + HYSTeresis selection + 1 + 2 + read-write + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPROTERR + Write PROTection ERRor + 0 + 1 + read-only + + + + + + + CRCCU + 11001D + Cyclic Redundancy Check Calculation Unit + CRCCU_ + 0x40044000 + + 0 + 0x4000 + registers + + + CRCCU + 32 + + + + DSCR + CRCCU Descriptor Base Register + 0x00000000 + 32 + read-write + 0x00000000 + + + DSCR + Descriptor Base Address + 9 + 23 + read-write + + + + + DMA_EN + CRCCU DMA Enable Register + 0x00000008 + 32 + write-only + 0x00000000 + + + DMAEN + DMA Enable Register + 0 + 1 + write-only + + + + + DMA_DIS + CRCCU DMA Disable Register + 0x0000000C + 32 + write-only + 0x00000000 + + + DMADIS + DMA Disable Register + 0 + 1 + write-only + + + + + DMA_SR + CRCCU DMA Status Register + 0x00000010 + 32 + read-only + 0x00000000 + + + DMASR + DMA Status Register + 0 + 1 + read-only + + + + + DMA_IER + CRCCU DMA Interrupt Enable Register + 0x00000014 + 32 + write-only + 0x00000000 + + + DMAIER + Interrupt Enable register + 0 + 1 + write-only + + + + + DMA_IDR + CRCCU DMA Interrupt Disable Register + 0x00000018 + 32 + write-only + 0x00000000 + + + DMAIDR + Interrupt Disable register + 0 + 1 + write-only + + + + + DMA_IMR + CRCCU DMA Interrupt Mask Register + 0x0000001C + 32 + read-only + 0x00000000 + + + DMAIMR + Interrupt Mask Register + 0 + 1 + read-only + + + + + DMA_ISR + CRCCU DMA Interrupt Status Register + 0x00000020 + 32 + read-only + 0x00000000 + + + DMAISR + Interrupt Status register + 0 + 1 + read-only + + + + + CR + CRCCU Control Register + 0x00000034 + 32 + write-only + 0x00000000 + + + RESET + CRC Computation Reset + 0 + 1 + write-only + + + + + MR + CRCCU Mode Register + 0x00000038 + 32 + read-write + 0x00000000 + + + ENABLE + CRC Enable + 0 + 1 + read-write + + + COMPARE + CRC Compare + 1 + 1 + read-write + + + PTYPE + Primitive Polynomial + 2 + 2 + read-write + + + CCITT8023 + Polynom 0x04C11DB7 + 0x0 + + + CASTAGNOLI + Polynom 0x1EDC6F41 + 0x1 + + + CCITT16 + Polynom 0x1021 + 0x2 + + + + + DIVIDER + Request Divider + 4 + 4 + read-write + + + + + SR + CRCCU Status Register + 0x0000003C + 32 + read-only + 0xFFFFFFFF + + + CRC + Cyclic Redundancy Check Value + 0 + 32 + read-only + + + + + IER + CRCCU Interrupt Enable Register + 0x00000040 + 32 + write-only + 0x00000000 + + + ERRIER + CRC Error Interrupt Enable + 0 + 1 + write-only + + + + + IDR + CRCCU Interrupt Disable Register + 0x00000044 + 32 + write-only + 0x00000000 + + + ERRIDR + CRC Error Interrupt Disable + 0 + 1 + write-only + + + + + IMR + CRCCU Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + ERRIMR + CRC Error Interrupt Mask + 0 + 1 + read-only + + + + + ISR + CRCCU Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + ERRISR + CRC Error Interrupt Status + 0 + 1 + read-only + + + + + + + SMC + 6498E + Static Memory Controller + EBI + SMC_ + 0x400E0000 + + 0 + 0x200 + registers + + + + SETUP0 + SMC Setup Register (CS_number = 0) + 0x00000000 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE0 + SMC Pulse Register (CS_number = 0) + 0x00000004 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE0 + SMC Cycle Register (CS_number = 0) + 0x00000008 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE0 + SMC Mode Register (CS_number = 0) + 0x0000000C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP1 + SMC Setup Register (CS_number = 1) + 0x00000010 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE1 + SMC Pulse Register (CS_number = 1) + 0x00000014 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE1 + SMC Cycle Register (CS_number = 1) + 0x00000018 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE1 + SMC Mode Register (CS_number = 1) + 0x0000001C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP2 + SMC Setup Register (CS_number = 2) + 0x00000020 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE2 + SMC Pulse Register (CS_number = 2) + 0x00000024 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE2 + SMC Cycle Register (CS_number = 2) + 0x00000028 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE2 + SMC Mode Register (CS_number = 2) + 0x0000002C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + SETUP3 + SMC Setup Register (CS_number = 3) + 0x00000030 + 32 + read-write + 0x01010101 + + + NWE_SETUP + NWE Setup Length + 0 + 6 + read-write + + + NCS_WR_SETUP + NCS Setup Length in WRITE Access + 8 + 6 + read-write + + + NRD_SETUP + NRD Setup Length + 16 + 6 + read-write + + + NCS_RD_SETUP + NCS Setup Length in READ Access + 24 + 6 + read-write + + + + + PULSE3 + SMC Pulse Register (CS_number = 3) + 0x00000034 + 32 + read-write + 0x01010101 + + + NWE_PULSE + NWE Pulse Length + 0 + 7 + read-write + + + NCS_WR_PULSE + NCS Pulse Length in WRITE Access + 8 + 7 + read-write + + + NRD_PULSE + NRD Pulse Length + 16 + 7 + read-write + + + NCS_RD_PULSE + NCS Pulse Length in READ Access + 24 + 7 + read-write + + + + + CYCLE3 + SMC Cycle Register (CS_number = 3) + 0x00000038 + 32 + read-write + 0x00030003 + + + NWE_CYCLE + Total Write Cycle Length + 0 + 9 + read-write + + + NRD_CYCLE + Total Read Cycle Length + 16 + 9 + read-write + + + + + MODE3 + SMC Mode Register (CS_number = 3) + 0x0000003C + 32 + read-write + 0x10000003 + + + READ_MODE + 0 + 1 + read-write + + + WRITE_MODE + 1 + 1 + read-write + + + EXNW_MODE + NWAIT Mode + 4 + 2 + read-write + + + DISABLED + Disabled + 0x0 + + + FROZEN + Frozen Mode + 0x2 + + + READY + Ready Mode + 0x3 + + + + + TDF_CYCLES + Data Float Time + 16 + 4 + read-write + + + TDF_MODE + TDF Optimization + 20 + 1 + read-write + + + PMEN + Page Mode Enabled + 24 + 1 + read-write + + + PS + Page Size + 28 + 2 + read-write + + + 4_BYTE + 4-byte page + 0x0 + + + 8_BYTE + 8-byte page + 0x1 + + + 16_BYTE + 16-byte page + 0x2 + + + 32_BYTE + 32-byte page + 0x3 + + + + + + + OCMS + SMC OCMS MODE Register + 0x00000080 + 32 + read-write + 0x00000000 + + + SMSE + Static Memory Controller Scrambling Enable + 0 + 1 + read-write + + + CS0SE + Chip Select (x = 0 to 3) Scrambling Enable + 16 + 1 + read-write + + + CS1SE + Chip Select (x = 0 to 3) Scrambling Enable + 17 + 1 + read-write + + + CS2SE + Chip Select (x = 0 to 3) Scrambling Enable + 18 + 1 + read-write + + + CS3SE + Chip Select (x = 0 to 3) Scrambling Enable + 19 + 1 + read-write + + + + + KEY1 + SMC OCMS KEY1 Register + 0x00000084 + 32 + write-only + 0x00000000 + + + KEY1 + Off Chip Memory Scrambling (OCMS) Key Part 1 + 0 + 32 + write-only + + + + + KEY2 + SMC OCMS KEY2 Register + 0x00000088 + 32 + write-only + 0x00000000 + + + KEY2 + Off Chip Memory Scrambling (OCMS) Key Part 2 + 0 + 32 + write-only + + + + + WPMR + SMC Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + SMC Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Enable + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + MATRIX + 6499A + AHB Bus Matrix + 0x400E0200 + + 0 + 0x200 + registers + + + + 4 + 4 + 0-3 + MATRIX_MCFG[%s] + Master Configuration Register + 0x00000000 + 32 + read-write + + + ULBT + Undefined Length Burst Type + 0 + 3 + read-write + + + + + 5 + 4 + 0-4 + MATRIX_SCFG[%s] + Slave Configuration Register + 0x00000040 + 32 + read-write + + + SLOT_CYCLE + Maximum Number of Allowed Cycles for a Burst + 0 + 8 + read-write + + + DEFMSTR_TYPE + Default Master Type + 16 + 2 + read-write + + + FIXED_DEFMSTR + Fixed Default Master + 18 + 3 + read-write + + + ARBT + Arbitration Type + 24 + 2 + read-write + + + + + MATRIX_PRAS0 + Priority Register A for Slave 0 + 0x00000080 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS1 + Priority Register A for Slave 1 + 0x00000088 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS2 + Priority Register A for Slave 2 + 0x00000090 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS3 + Priority Register A for Slave 3 + 0x00000098 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + MATRIX_PRAS4 + Priority Register A for Slave 4 + 0x000000A0 + 32 + read-write + 0x00000000 + + + M0PR + Master 0 Priority + 0 + 2 + read-write + + + M1PR + Master 1 Priority + 4 + 2 + read-write + + + M2PR + Master 2 Priority + 8 + 2 + read-write + + + M3PR + Master 3 Priority + 12 + 2 + read-write + + + M4PR + Master 4 Priority + 16 + 2 + read-write + + + + + CCFG_SYSIO + System I/O Configuration register + 0x00000114 + 32 + read-write + 0x00000000 + + + SYSIO4 + PB4 or TDI Assignment + 4 + 1 + read-write + + + SYSIO5 + PB5 or TDO/TRACESWO Assignment + 5 + 1 + read-write + + + SYSIO6 + PB6 or TMS/SWDIO Assignment + 6 + 1 + read-write + + + SYSIO7 + PB7 or TCK/SWCLK Assignment + 7 + 1 + read-write + + + SYSIO10 + PB10 or DDM Assignment + 10 + 1 + read-write + + + SYSIO11 + PB11 or DDP Assignment + 11 + 1 + read-write + + + SYSIO12 + PB12 or ERASE Assignment + 12 + 1 + read-write + + + + + CCFG_SMCNFCS + SMC Chip Select NAND Flash Assignment Register + 0x0000011C + 32 + read-write + 0x00000000 + + + SMC_NFCS0 + SMC NAND Flash Chip Select 0 Assignment + 0 + 1 + read-write + + + SMC_NFCS1 + SMC NAND Flash Chip Select 1 Assignment + 1 + 1 + read-write + + + SMC_NFCS2 + SMC NAND Flash Chip Select 2 Assignment + 2 + 1 + read-write + + + SMC_NFCS3 + SMC NAND Flash Chip Select 3 Assignment + 3 + 1 + read-write + + + + + MATRIX_WPMR + Write Protect Mode Register + 0x000001E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect ENable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY (Write-only) + 8 + 24 + read-write + + + + + MATRIX_WPSR + Write Protect Status Register + 0x000001E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + + + PMC + 11116D + Power Management Controller + 0x400E0400 + + 0 + 0x140 + registers + + + PMC + 5 + + + + PMC_SCER + System Clock Enable Register + 0x00000000 + 32 + write-only + + + UDP + USB Device Port Clock Enable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Enable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Enable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Enable + 10 + 1 + write-only + + + + + PMC_SCDR + System Clock Disable Register + 0x00000004 + 32 + write-only + + + UDP + USB Device Port Clock Disable + 7 + 1 + write-only + + + PCK0 + Programmable Clock 0 Output Disable + 8 + 1 + write-only + + + PCK1 + Programmable Clock 1 Output Disable + 9 + 1 + write-only + + + PCK2 + Programmable Clock 2 Output Disable + 10 + 1 + write-only + + + + + PMC_SCSR + System Clock Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + UDP + USB Device Port Clock Status + 7 + 1 + read-only + + + PCK0 + Programmable Clock 0 Output Status + 8 + 1 + read-only + + + PCK1 + Programmable Clock 1 Output Status + 9 + 1 + read-only + + + PCK2 + Programmable Clock 2 Output Status + 10 + 1 + read-only + + + + + PMC_PCER0 + Peripheral Clock Enable Register 0 + 0x00000010 + 32 + write-only + + + PID2 + Peripheral Clock 2 Enable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Enable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Enable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Enable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Enable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Enable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Enable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Enable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Enable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Enable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Enable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Enable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Enable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Enable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Enable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Enable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Enable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Enable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Enable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Enable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Enable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Enable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Enable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Enable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Enable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Enable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Enable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Enable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Enable + 31 + 1 + write-only + + + + + PMC_PCDR0 + Peripheral Clock Disable Register 0 + 0x00000014 + 32 + write-only + + + PID2 + Peripheral Clock 2 Disable + 2 + 1 + write-only + + + PID3 + Peripheral Clock 3 Disable + 3 + 1 + write-only + + + PID4 + Peripheral Clock 4 Disable + 4 + 1 + write-only + + + PID5 + Peripheral Clock 5 Disable + 5 + 1 + write-only + + + PID6 + Peripheral Clock 6 Disable + 6 + 1 + write-only + + + PID7 + Peripheral Clock 7 Disable + 7 + 1 + write-only + + + PID8 + Peripheral Clock 8 Disable + 8 + 1 + write-only + + + PID9 + Peripheral Clock 9 Disable + 9 + 1 + write-only + + + PID10 + Peripheral Clock 10 Disable + 10 + 1 + write-only + + + PID11 + Peripheral Clock 11 Disable + 11 + 1 + write-only + + + PID12 + Peripheral Clock 12 Disable + 12 + 1 + write-only + + + PID13 + Peripheral Clock 13 Disable + 13 + 1 + write-only + + + PID14 + Peripheral Clock 14 Disable + 14 + 1 + write-only + + + PID15 + Peripheral Clock 15 Disable + 15 + 1 + write-only + + + PID16 + Peripheral Clock 16 Disable + 16 + 1 + write-only + + + PID18 + Peripheral Clock 18 Disable + 18 + 1 + write-only + + + PID19 + Peripheral Clock 19 Disable + 19 + 1 + write-only + + + PID20 + Peripheral Clock 20 Disable + 20 + 1 + write-only + + + PID21 + Peripheral Clock 21 Disable + 21 + 1 + write-only + + + PID22 + Peripheral Clock 22 Disable + 22 + 1 + write-only + + + PID23 + Peripheral Clock 23 Disable + 23 + 1 + write-only + + + PID24 + Peripheral Clock 24 Disable + 24 + 1 + write-only + + + PID25 + Peripheral Clock 25 Disable + 25 + 1 + write-only + + + PID26 + Peripheral Clock 26 Disable + 26 + 1 + write-only + + + PID27 + Peripheral Clock 27 Disable + 27 + 1 + write-only + + + PID28 + Peripheral Clock 28 Disable + 28 + 1 + write-only + + + PID29 + Peripheral Clock 29 Disable + 29 + 1 + write-only + + + PID30 + Peripheral Clock 30 Disable + 30 + 1 + write-only + + + PID31 + Peripheral Clock 31 Disable + 31 + 1 + write-only + + + + + PMC_PCSR0 + Peripheral Clock Status Register 0 + 0x00000018 + 32 + read-only + 0x00000000 + + + PID2 + Peripheral Clock 2 Status + 2 + 1 + read-only + + + PID3 + Peripheral Clock 3 Status + 3 + 1 + read-only + + + PID4 + Peripheral Clock 4 Status + 4 + 1 + read-only + + + PID5 + Peripheral Clock 5 Status + 5 + 1 + read-only + + + PID6 + Peripheral Clock 6 Status + 6 + 1 + read-only + + + PID7 + Peripheral Clock 7 Status + 7 + 1 + read-only + + + PID8 + Peripheral Clock 8 Status + 8 + 1 + read-only + + + PID9 + Peripheral Clock 9 Status + 9 + 1 + read-only + + + PID10 + Peripheral Clock 10 Status + 10 + 1 + read-only + + + PID11 + Peripheral Clock 11 Status + 11 + 1 + read-only + + + PID12 + Peripheral Clock 12 Status + 12 + 1 + read-only + + + PID13 + Peripheral Clock 13 Status + 13 + 1 + read-only + + + PID14 + Peripheral Clock 14 Status + 14 + 1 + read-only + + + PID15 + Peripheral Clock 15 Status + 15 + 1 + read-only + + + PID16 + Peripheral Clock 16 Status + 16 + 1 + read-only + + + PID18 + Peripheral Clock 18 Status + 18 + 1 + read-only + + + PID19 + Peripheral Clock 19 Status + 19 + 1 + read-only + + + PID20 + Peripheral Clock 20 Status + 20 + 1 + read-only + + + PID21 + Peripheral Clock 21 Status + 21 + 1 + read-only + + + PID22 + Peripheral Clock 22 Status + 22 + 1 + read-only + + + PID23 + Peripheral Clock 23 Status + 23 + 1 + read-only + + + PID24 + Peripheral Clock 24 Status + 24 + 1 + read-only + + + PID25 + Peripheral Clock 25 Status + 25 + 1 + read-only + + + PID26 + Peripheral Clock 26 Status + 26 + 1 + read-only + + + PID27 + Peripheral Clock 27 Status + 27 + 1 + read-only + + + PID28 + Peripheral Clock 28 Status + 28 + 1 + read-only + + + PID29 + Peripheral Clock 29 Status + 29 + 1 + read-only + + + PID30 + Peripheral Clock 30 Status + 30 + 1 + read-only + + + PID31 + Peripheral Clock 31 Status + 31 + 1 + read-only + + + + + CKGR_MOR + Main Oscillator Register + 0x00000020 + 32 + read-write + 0x00000001 + + + MOSCXTEN + Main Crystal Oscillator Enable + 0 + 1 + read-write + + + MOSCXTBY + Main Crystal Oscillator Bypass + 1 + 1 + read-write + + + MOSCRCEN + Main On-Chip RC Oscillator Enable + 3 + 1 + read-write + + + MOSCRCF + Main On-Chip RC Oscillator Frequency Selection + 4 + 3 + read-write + + + 4_MHz + The Fast RC Oscillator Frequency is at 4 MHz (default) + 0x0 + + + 8_MHz + The Fast RC Oscillator Frequency is at 8 MHz + 0x1 + + + 12_MHz + The Fast RC Oscillator Frequency is at 12 MHz + 0x2 + + + + + MOSCXTST + Main Crystal Oscillator Start-up Time + 8 + 8 + read-write + + + KEY + Password + 16 + 8 + read-write + + + MOSCSEL + Main Oscillator Selection + 24 + 1 + read-write + + + CFDEN + Clock Failure Detector Enable + 25 + 1 + read-write + + + + + CKGR_MCFR + Main Clock Frequency Register + 0x00000024 + 32 + read-write + 0x00000000 + + + MAINF + Main Clock Frequency + 0 + 16 + read-write + + + MAINFRDY + Main Clock Ready + 16 + 1 + read-write + + + RCMEAS + RC Oscillator Frequency Measure (write-only) + 20 + 1 + read-write + + + + + CKGR_PLLAR + PLLA Register + 0x00000028 + 32 + read-write + 0x00003F00 + + + DIVA + Divider + 0 + 8 + read-write + + + PLLACOUNT + PLLA Counter + 8 + 6 + read-write + + + MULA + PLLA Multiplier + 16 + 11 + read-write + + + ONE + Must Be Set to 1 + 29 + 1 + read-write + + + + + CKGR_PLLBR + PLLB Register + 0x0000002C + 32 + read-write + 0x00003F00 + + + DIVB + Divider + 0 + 8 + read-write + + + PLLBCOUNT + PLLB Counter + 8 + 6 + read-write + + + MULB + PLLB Multiplier + 16 + 11 + read-write + + + + + PMC_MCKR + Master Clock Register + 0x00000030 + 32 + read-write + 0x00000001 + + + CSS + Master Clock Source Selection + 0 + 2 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLBClock is selected + 0x3 + + + + + PRES + Processor Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + CLK_3 + Selected clock divided by 3 + 0x7 + + + + + PLLADIV2 + PLLA Divisor by 2 + 12 + 1 + read-write + + + PLLBDIV2 + PLLB Divisor by 2 + 13 + 1 + read-write + + + + + PMC_USB + USB Clock Register + 0x00000038 + 32 + read-write + 0x00000000 + + + USBS + USB Input Clock Selection + 0 + 1 + read-write + + + USBDIV + Divider for USB Clock. + 8 + 4 + read-write + + + + + 3 + 4 + 0-2 + PMC_PCK[%s] + Programmable Clock 0 Register + 0x00000040 + 32 + read-write + + + CSS + Master Clock Source Selection + 0 + 3 + read-write + + + SLOW_CLK + Slow Clock is selected + 0x0 + + + MAIN_CLK + Main Clock is selected + 0x1 + + + PLLA_CLK + PLLA Clock is selected + 0x2 + + + PLLB_CLK + PLLB Clock is selected + 0x3 + + + MCK + Master Clock is selected + 0x4 + + + + + PRES + Programmable Clock Prescaler + 4 + 3 + read-write + + + CLK_1 + Selected clock + 0x0 + + + CLK_2 + Selected clock divided by 2 + 0x1 + + + CLK_4 + Selected clock divided by 4 + 0x2 + + + CLK_8 + Selected clock divided by 8 + 0x3 + + + CLK_16 + Selected clock divided by 16 + 0x4 + + + CLK_32 + Selected clock divided by 32 + 0x5 + + + CLK_64 + Selected clock divided by 64 + 0x6 + + + + + + + PMC_IER + Interrupt Enable Register + 0x00000060 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Enable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Enable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Enable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Enable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Enable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Enable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Enable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Enable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Enable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Enable + 18 + 1 + write-only + + + + + PMC_IDR + Interrupt Disable Register + 0x00000064 + 32 + write-only + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Disable + 0 + 1 + write-only + + + LOCKA + PLLA Lock Interrupt Disable + 1 + 1 + write-only + + + LOCKB + PLLB Lock Interrupt Disable + 2 + 1 + write-only + + + MCKRDY + Master Clock Ready Interrupt Disable + 3 + 1 + write-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Disable + 8 + 1 + write-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Disable + 9 + 1 + write-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Disable + 10 + 1 + write-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Disable + 16 + 1 + write-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Disable + 17 + 1 + write-only + + + CFDEV + Clock Failure Detector Event Interrupt Disable + 18 + 1 + write-only + + + + + PMC_SR + Status Register + 0x00000068 + 32 + read-only + 0x00010008 + + + MOSCXTS + Main XTAL Oscillator Status + 0 + 1 + read-only + + + LOCKA + PLLA Lock Status + 1 + 1 + read-only + + + LOCKB + PLLB Lock Status + 2 + 1 + read-only + + + MCKRDY + Master Clock Status + 3 + 1 + read-only + + + OSCSELS + Slow Clock Oscillator Selection + 7 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready Status + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready Status + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready Status + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Oscillator Status + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event + 18 + 1 + read-only + + + CFDS + Clock Failure Detector Status + 19 + 1 + read-only + + + FOS + Clock Failure Detector Fault Output Status + 20 + 1 + read-only + + + + + PMC_IMR + Interrupt Mask Register + 0x0000006C + 32 + read-only + 0x00000000 + + + MOSCXTS + Main Crystal Oscillator Status Interrupt Mask + 0 + 1 + read-only + + + LOCKA + PLLA Lock Interrupt Mask + 1 + 1 + read-only + + + LOCKB + PLLB Lock Interrupt Mask + 2 + 1 + read-only + + + MCKRDY + Master Clock Ready Interrupt Mask + 3 + 1 + read-only + + + PCKRDY0 + Programmable Clock Ready 0 Interrupt Mask + 8 + 1 + read-only + + + PCKRDY1 + Programmable Clock Ready 1 Interrupt Mask + 9 + 1 + read-only + + + PCKRDY2 + Programmable Clock Ready 2 Interrupt Mask + 10 + 1 + read-only + + + MOSCSELS + Main Oscillator Selection Status Interrupt Mask + 16 + 1 + read-only + + + MOSCRCS + Main On-Chip RC Status Interrupt Mask + 17 + 1 + read-only + + + CFDEV + Clock Failure Detector Event Interrupt Mask + 18 + 1 + read-only + + + + + PMC_FSMR + Fast Startup Mode Register + 0x00000070 + 32 + read-write + 0x00000000 + + + FSTT0 + Fast Startup Input Enable 0 + 0 + 1 + read-write + + + FSTT1 + Fast Startup Input Enable 1 + 1 + 1 + read-write + + + FSTT2 + Fast Startup Input Enable 2 + 2 + 1 + read-write + + + FSTT3 + Fast Startup Input Enable 3 + 3 + 1 + read-write + + + FSTT4 + Fast Startup Input Enable 4 + 4 + 1 + read-write + + + FSTT5 + Fast Startup Input Enable 5 + 5 + 1 + read-write + + + FSTT6 + Fast Startup Input Enable 6 + 6 + 1 + read-write + + + FSTT7 + Fast Startup Input Enable 7 + 7 + 1 + read-write + + + FSTT8 + Fast Startup Input Enable 8 + 8 + 1 + read-write + + + FSTT9 + Fast Startup Input Enable 9 + 9 + 1 + read-write + + + FSTT10 + Fast Startup Input Enable 10 + 10 + 1 + read-write + + + FSTT11 + Fast Startup Input Enable 11 + 11 + 1 + read-write + + + FSTT12 + Fast Startup Input Enable 12 + 12 + 1 + read-write + + + FSTT13 + Fast Startup Input Enable 13 + 13 + 1 + read-write + + + FSTT14 + Fast Startup Input Enable 14 + 14 + 1 + read-write + + + FSTT15 + Fast Startup Input Enable 15 + 15 + 1 + read-write + + + RTTAL + RTT Alarm Enable + 16 + 1 + read-write + + + RTCAL + RTC Alarm Enable + 17 + 1 + read-write + + + USBAL + USB Alarm Enable + 18 + 1 + read-write + + + LPM + Low Power Mode + 20 + 1 + read-write + + + + + PMC_FSPR + Fast Startup Polarity Register + 0x00000074 + 32 + read-write + 0x00000000 + + + FSTP0 + Fast Startup Input Polarityx + 0 + 1 + read-write + + + FSTP1 + Fast Startup Input Polarityx + 1 + 1 + read-write + + + FSTP2 + Fast Startup Input Polarityx + 2 + 1 + read-write + + + FSTP3 + Fast Startup Input Polarityx + 3 + 1 + read-write + + + FSTP4 + Fast Startup Input Polarityx + 4 + 1 + read-write + + + FSTP5 + Fast Startup Input Polarityx + 5 + 1 + read-write + + + FSTP6 + Fast Startup Input Polarityx + 6 + 1 + read-write + + + FSTP7 + Fast Startup Input Polarityx + 7 + 1 + read-write + + + FSTP8 + Fast Startup Input Polarityx + 8 + 1 + read-write + + + FSTP9 + Fast Startup Input Polarityx + 9 + 1 + read-write + + + FSTP10 + Fast Startup Input Polarityx + 10 + 1 + read-write + + + FSTP11 + Fast Startup Input Polarityx + 11 + 1 + read-write + + + FSTP12 + Fast Startup Input Polarityx + 12 + 1 + read-write + + + FSTP13 + Fast Startup Input Polarityx + 13 + 1 + read-write + + + FSTP14 + Fast Startup Input Polarityx + 14 + 1 + read-write + + + FSTP15 + Fast Startup Input Polarityx + 15 + 1 + read-write + + + + + PMC_FOCR + Fault Output Clear Register + 0x00000078 + 32 + write-only + + + FOCLR + Fault Output Clear + 0 + 1 + write-only + + + + + PMC_WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + PMC_WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + PMC_PCER1 + Peripheral Clock Enable Register 1 + 0x00000100 + 32 + write-only + + + PID32 + Peripheral Clock 32 Enable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Enable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Enable + 2 + 1 + write-only + + + + + PMC_PCDR1 + Peripheral Clock Disable Register 1 + 0x00000104 + 32 + write-only + + + PID32 + Peripheral Clock 32 Disable + 0 + 1 + write-only + + + PID33 + Peripheral Clock 33 Disable + 1 + 1 + write-only + + + PID34 + Peripheral Clock 34 Disable + 2 + 1 + write-only + + + + + PMC_PCSR1 + Peripheral Clock Status Register 1 + 0x00000108 + 32 + read-only + 0x00000000 + + + PID32 + Peripheral Clock 32 Status + 0 + 1 + read-only + + + PID33 + Peripheral Clock 33 Status + 1 + 1 + read-only + + + PID34 + Peripheral Clock 34 Status + 2 + 1 + read-only + + + + + PMC_OCR + Oscillator Calibration Register + 0x00000110 + 32 + read-write + 0x00404040 + + + CAL4 + RC Oscillator Calibration bits for 4 Mhz + 0 + 7 + read-write + + + SEL4 + Selection of RC Oscillator Calibration bits for 4 Mhz + 7 + 1 + read-write + + + CAL8 + RC Oscillator Calibration bits for 8 Mhz + 8 + 7 + read-write + + + SEL8 + Selection of RC Oscillator Calibration bits for 8 Mhz + 15 + 1 + read-write + + + CAL12 + RC Oscillator Calibration bits for 12 Mhz + 16 + 7 + read-write + + + SEL12 + Selection of RC Oscillator Calibration bits for 12 Mhz + 23 + 1 + read-write + + + + + + + UART0 + 6418E + Universal Asynchronous Receiver Transmitter 0 + UART + UART0_ + 0x400E0600 + + 0 + 0x128 + registers + + + UART0 + 8 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + CHIPID + 6417K + Chip Identifier + CHIPID_ + 0x400E0740 + + 0 + 0x200 + registers + + + + CIDR + Chip ID Register + 0x00000000 + 32 + read-only + + + VERSION + Version of the Device + 0 + 5 + read-only + + + EPROC + Embedded Processor + 5 + 3 + read-only + + + ARM946ES + ARM946ES + 0x1 + + + ARM7TDMI + ARM7TDMI + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + ARM920T + ARM920T + 0x4 + + + ARM926EJS + ARM926EJS + 0x5 + + + CA5 + Cortex-A5 + 0x6 + + + CM4 + Cortex-M4 + 0x7 + + + + + NVPSIZ + Nonvolatile Program Memory Size + 8 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + NVPSIZ2 + Second Nonvolatile Program Memory Size + 12 + 4 + read-only + + + NONE + None + 0x0 + + + 8K + 8K bytes + 0x1 + + + 16K + 16K bytes + 0x2 + + + 32K + 32K bytes + 0x3 + + + 64K + 64K bytes + 0x5 + + + 128K + 128K bytes + 0x7 + + + 256K + 256K bytes + 0x9 + + + 512K + 512K bytes + 0xA + + + 1024K + 1024K bytes + 0xC + + + 2048K + 2048K bytes + 0xE + + + + + SRAMSIZ + Internal SRAM Size + 16 + 4 + read-only + + + 48K + 48K bytes + 0x0 + + + 1K + 1K bytes + 0x1 + + + 2K + 2K bytes + 0x2 + + + 6K + 6K bytes + 0x3 + + + 24K + 24K bytes + 0x4 + + + 4K + 4K bytes + 0x5 + + + 80K + 80K bytes + 0x6 + + + 160K + 160K bytes + 0x7 + + + 8K + 8K bytes + 0x8 + + + 16K + 16K bytes + 0x9 + + + 32K + 32K bytes + 0xA + + + 64K + 64K bytes + 0xB + + + 128K + 128K bytes + 0xC + + + 256K + 256K bytes + 0xD + + + 96K + 96K bytes + 0xE + + + 512K + 512K bytes + 0xF + + + + + ARCH + Architecture Identifier + 20 + 8 + read-only + + + AT91SAM9xx + AT91SAM9xx Series + 0x19 + + + AT91SAM9XExx + AT91SAM9XExx Series + 0x29 + + + AT91x34 + AT91x34 Series + 0x34 + + + CAP7 + CAP7 Series + 0x37 + + + CAP9 + CAP9 Series + 0x39 + + + CAP11 + CAP11 Series + 0x3B + + + AT91x40 + AT91x40 Series + 0x40 + + + AT91x42 + AT91x42 Series + 0x42 + + + AT91x55 + AT91x55 Series + 0x55 + + + AT91SAM7Axx + AT91SAM7Axx Series + 0x60 + + + AT91SAM7AQxx + AT91SAM7AQxx Series + 0x61 + + + AT91x63 + AT91x63 Series + 0x63 + + + AT91SAM7Sxx + AT91SAM7Sxx Series + 0x70 + + + AT91SAM7XCxx + AT91SAM7XCxx Series + 0x71 + + + AT91SAM7SExx + AT91SAM7SExx Series + 0x72 + + + AT91SAM7Lxx + AT91SAM7Lxx Series + 0x73 + + + AT91SAM7Xxx + AT91SAM7Xxx Series + 0x75 + + + AT91SAM7SLxx + AT91SAM7SLxx Series + 0x76 + + + SAM3UxC + SAM3UxC Series (100-pin version) + 0x80 + + + SAM3UxE + SAM3UxE Series (144-pin version) + 0x81 + + + SAM3AxC + SAM3AxC Series (100-pin version) + 0x83 + + + SAM4AxC + SAM4AxC Series (100-pin version) + 0x83 + + + SAM3XxC + SAM3XxC Series (100-pin version) + 0x84 + + + SAM4XxC + SAM4XxC Series (100-pin version) + 0x84 + + + SAM3XxE + SAM3XxE Series (144-pin version) + 0x85 + + + SAM4XxE + SAM4XxE Series (144-pin version) + 0x85 + + + SAM3XxG + SAM3XxG Series (208/217-pin version) + 0x86 + + + SAM4XxG + SAM4XxG Series (208/217-pin version) + 0x86 + + + SAM3SxA + SAM3SxASeries (48-pin version) + 0x88 + + + SAM4SxA + SAM4SxA Series (48-pin version) + 0x88 + + + SAM3SxB + SAM3SxB Series (64-pin version) + 0x89 + + + SAM4SxB + SAM4SxB Series (64-pin version) + 0x89 + + + SAM3SxC + SAM3SxC Series (100-pin version) + 0x8A + + + SAM4SxC + SAM4SxC Series (100-pin version) + 0x8A + + + AT91x92 + AT91x92 Series + 0x92 + + + SAM3NxA + SAM3NxA Series (48-pin version) + 0x93 + + + SAM3NxB + SAM3NxB Series (64-pin version) + 0x94 + + + SAM3NxC + SAM3NxC Series (100-pin version) + 0x95 + + + SAM3SDxB + SAM3SDxB Series (64-pin version) + 0x99 + + + SAM3SDxC + SAM3SDxC Series (100-pin version) + 0x9A + + + SAM5A + SAM5A + 0xA5 + + + AT75Cxx + AT75Cxx Series + 0xF0 + + + + + NVPTYP + Nonvolatile Program Memory Type + 28 + 3 + read-only + + + ROM + ROM + 0x0 + + + ROMLESS + ROMless or on-chip Flash + 0x1 + + + FLASH + Embedded Flash Memory + 0x2 + + + ROM_FLASH + ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size + 0x3 + + + SRAM + SRAM emulating ROM + 0x4 + + + + + EXT + Extension Flag + 31 + 1 + read-only + + + + + EXID + Chip ID Extension Register + 0x00000004 + 32 + read-only + + + EXID + Chip ID Extension + 0 + 32 + read-only + + + + + + + UART1 + 6418E + Universal Asynchronous Receiver Transmitter 1 + UART + UART1_ + 0x400E0800 + + 0 + 0x128 + registers + + + UART1 + 9 + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + RSTRX + Reset Receiver + 2 + 1 + write-only + + + RSTTX + Reset Transmitter + 3 + 1 + write-only + + + RXEN + Receiver Enable + 4 + 1 + write-only + + + RXDIS + Receiver Disable + 5 + 1 + write-only + + + TXEN + Transmitter Enable + 6 + 1 + write-only + + + TXDIS + Transmitter Disable + 7 + 1 + write-only + + + RSTSTA + Reset Status Bits + 8 + 1 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + PAR + Parity Type + 9 + 3 + read-write + + + EVEN + Even parity + 0x0 + + + ODD + Odd parity + 0x1 + + + SPACE + Space: parity forced to 0 + 0x2 + + + MARK + Mark: parity forced to 1 + 0x3 + + + NO + No parity + 0x4 + + + + + CHMODE + Channel Mode + 14 + 2 + read-write + + + NORMAL + Normal Mode + 0x0 + + + AUTOMATIC + Automatic Echo + 0x1 + + + LOCAL_LOOPBACK + Local Loopback + 0x2 + + + REMOTE_LOOPBACK + Remote Loopback + 0x3 + + + + + + + IER + Interrupt Enable Register + 0x00000008 + 32 + write-only + + + RXRDY + Enable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Enable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Enable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Enable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Enable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Enable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Enable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Enable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Enable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Enable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x0000000C + 32 + write-only + + + RXRDY + Disable RXRDY Interrupt + 0 + 1 + write-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + write-only + + + ENDRX + Disable End of Receive Transfer Interrupt + 3 + 1 + write-only + + + ENDTX + Disable End of Transmit Interrupt + 4 + 1 + write-only + + + OVRE + Disable Overrun Error Interrupt + 5 + 1 + write-only + + + FRAME + Disable Framing Error Interrupt + 6 + 1 + write-only + + + PARE + Disable Parity Error Interrupt + 7 + 1 + write-only + + + TXEMPTY + Disable TXEMPTY Interrupt + 9 + 1 + write-only + + + TXBUFE + Disable Buffer Empty Interrupt + 11 + 1 + write-only + + + RXBUFF + Disable Buffer Full Interrupt + 12 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000010 + 32 + read-only + 0x00000000 + + + RXRDY + Mask RXRDY Interrupt + 0 + 1 + read-only + + + TXRDY + Disable TXRDY Interrupt + 1 + 1 + read-only + + + ENDRX + Mask End of Receive Transfer Interrupt + 3 + 1 + read-only + + + ENDTX + Mask End of Transmit Interrupt + 4 + 1 + read-only + + + OVRE + Mask Overrun Error Interrupt + 5 + 1 + read-only + + + FRAME + Mask Framing Error Interrupt + 6 + 1 + read-only + + + PARE + Mask Parity Error Interrupt + 7 + 1 + read-only + + + TXEMPTY + Mask TXEMPTY Interrupt + 9 + 1 + read-only + + + TXBUFE + Mask TXBUFE Interrupt + 11 + 1 + read-only + + + RXBUFF + Mask RXBUFF Interrupt + 12 + 1 + read-only + + + + + SR + Status Register + 0x00000014 + 32 + read-only + + + RXRDY + Receiver Ready + 0 + 1 + read-only + + + TXRDY + Transmitter Ready + 1 + 1 + read-only + + + ENDRX + End of Receiver Transfer + 3 + 1 + read-only + + + ENDTX + End of Transmitter Transfer + 4 + 1 + read-only + + + OVRE + Overrun Error + 5 + 1 + read-only + + + FRAME + Framing Error + 6 + 1 + read-only + + + PARE + Parity Error + 7 + 1 + read-only + + + TXEMPTY + Transmitter Empty + 9 + 1 + read-only + + + TXBUFE + Transmission Buffer Empty + 11 + 1 + read-only + + + RXBUFF + Receive Buffer Full + 12 + 1 + read-only + + + + + RHR + Receive Holding Register + 0x00000018 + 32 + read-only + 0x00000000 + + + RXCHR + Received Character + 0 + 8 + read-only + + + + + THR + Transmit Holding Register + 0x0000001C + 32 + write-only + + + TXCHR + Character to be Transmitted + 0 + 8 + write-only + + + + + BRGR + Baud Rate Generator Register + 0x00000020 + 32 + read-write + 0x00000000 + + + CD + Clock Divisor + 0 + 16 + read-write + + + + + RPR + Receive Pointer Register + 0x00000100 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x00000104 + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + TPR + Transmit Pointer Register + 0x00000108 + 32 + read-write + 0x00000000 + + + TXPTR + Transmit Counter Register + 0 + 32 + read-write + + + + + TCR + Transmit Counter Register + 0x0000010C + 32 + read-write + 0x00000000 + + + TXCTR + Transmit Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000110 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x00000114 + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + TNPR + Transmit Next Pointer Register + 0x00000118 + 32 + read-write + 0x00000000 + + + TXNPTR + Transmit Next Pointer + 0 + 32 + read-write + + + + + TNCR + Transmit Next Counter Register + 0x0000011C + 32 + read-write + 0x00000000 + + + TXNCTR + Transmit Counter Next + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000120 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x00000124 + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + EFC + 6450G + Embedded Flash Controller + EFC_ + 0x400E0A00 + + 0 + 0x200 + registers + + + EFC + 6 + + + + FMR + EEFC Flash Mode Register + 0x00000000 + 32 + read-write + 0x00000000 + + + FRDY + Ready Interrupt Enable + 0 + 1 + read-write + + + FWS + Flash Wait State + 8 + 4 + read-write + + + SCOD + Sequential Code Optimization Disable + 16 + 1 + read-write + + + FAM + Flash Access Mode + 24 + 1 + read-write + + + + + FCR + EEFC Flash Command Register + 0x00000004 + 32 + write-only + + + FCMD + Flash Command + 0 + 8 + write-only + + + GETD + Get Flash Descriptor + 0x00 + + + WP + Write page + 0x01 + + + WPL + Write page and lock + 0x02 + + + EWP + Erase page and write page + 0x03 + + + EWPL + Erase page and write page then lock + 0x04 + + + EA + Erase all + 0x05 + + + SLB + Set Lock Bit + 0x08 + + + CLB + Clear Lock Bit + 0x09 + + + GLB + Get Lock Bit + 0x0A + + + SGPB + Set GPNVM Bit + 0x0B + + + CGPB + Clear GPNVM Bit + 0x0C + + + GGPB + Get GPNVM Bit + 0x0D + + + STUI + Start Read Unique Identifier + 0x0E + + + SPUI + Stop Read Unique Identifier + 0x0F + + + + + FARG + Flash Command Argument + 8 + 16 + write-only + + + FKEY + Flash Writing Protection Key + 24 + 8 + write-only + + + PASSWD + The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. + 0x5A + + + + + + + FSR + EEFC Flash Status Register + 0x00000008 + 32 + read-only + 0x00000001 + + + FRDY + Flash Ready Status + 0 + 1 + read-only + + + FCMDE + Flash Command Error Status + 1 + 1 + read-only + + + FLOCKE + Flash Lock Error Status + 2 + 1 + read-only + + + + + FRR + EEFC Flash Result Register + 0x0000000C + 32 + read-only + 0x00000000 + + + FVALUE + Flash Result Value + 0 + 32 + read-only + + + + + + + PIOA + 11004F + Parallel Input/Output Controller A + PIO + PIOA_ + 0x400E0E00 + + 0 + 0x200 + registers + + + PIOA + 11 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + RPR + Receive Pointer Register + 0x00000168 + 32 + read-write + 0x00000000 + + + RXPTR + Receive Pointer Register + 0 + 32 + read-write + + + + + RCR + Receive Counter Register + 0x0000016C + 32 + read-write + 0x00000000 + + + RXCTR + Receive Counter Register + 0 + 16 + read-write + + + + + RNPR + Receive Next Pointer Register + 0x00000178 + 32 + read-write + 0x00000000 + + + RXNPTR + Receive Next Pointer + 0 + 32 + read-write + + + + + RNCR + Receive Next Counter Register + 0x0000017C + 32 + read-write + 0x00000000 + + + RXNCTR + Receive Next Counter + 0 + 16 + read-write + + + + + PTCR + Transfer Control Register + 0x00000188 + 32 + write-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + write-only + + + RXTDIS + Receiver Transfer Disable + 1 + 1 + write-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + write-only + + + TXTDIS + Transmitter Transfer Disable + 9 + 1 + write-only + + + + + PTSR + Transfer Status Register + 0x0000018C + 32 + read-only + 0x00000000 + + + RXTEN + Receiver Transfer Enable + 0 + 1 + read-only + + + TXTEN + Transmitter Transfer Enable + 8 + 1 + read-only + + + + + + + PIOB + 11004F + Parallel Input/Output Controller B + PIO + PIOB_ + 0x400E1000 + + 0 + 0x200 + registers + + + PIOB + 12 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + + + PIOC + 11004F + Parallel Input/Output Controller C + PIO + PIOC_ + 0x400E1200 + + 0 + 0x200 + registers + + + PIOC + 13 + + + + PER + PIO Enable Register + 0x00000000 + 32 + write-only + + + P0 + PIO Enable + 0 + 1 + write-only + + + P1 + PIO Enable + 1 + 1 + write-only + + + P2 + PIO Enable + 2 + 1 + write-only + + + P3 + PIO Enable + 3 + 1 + write-only + + + P4 + PIO Enable + 4 + 1 + write-only + + + P5 + PIO Enable + 5 + 1 + write-only + + + P6 + PIO Enable + 6 + 1 + write-only + + + P7 + PIO Enable + 7 + 1 + write-only + + + P8 + PIO Enable + 8 + 1 + write-only + + + P9 + PIO Enable + 9 + 1 + write-only + + + P10 + PIO Enable + 10 + 1 + write-only + + + P11 + PIO Enable + 11 + 1 + write-only + + + P12 + PIO Enable + 12 + 1 + write-only + + + P13 + PIO Enable + 13 + 1 + write-only + + + P14 + PIO Enable + 14 + 1 + write-only + + + P15 + PIO Enable + 15 + 1 + write-only + + + P16 + PIO Enable + 16 + 1 + write-only + + + P17 + PIO Enable + 17 + 1 + write-only + + + P18 + PIO Enable + 18 + 1 + write-only + + + P19 + PIO Enable + 19 + 1 + write-only + + + P20 + PIO Enable + 20 + 1 + write-only + + + P21 + PIO Enable + 21 + 1 + write-only + + + P22 + PIO Enable + 22 + 1 + write-only + + + P23 + PIO Enable + 23 + 1 + write-only + + + P24 + PIO Enable + 24 + 1 + write-only + + + P25 + PIO Enable + 25 + 1 + write-only + + + P26 + PIO Enable + 26 + 1 + write-only + + + P27 + PIO Enable + 27 + 1 + write-only + + + P28 + PIO Enable + 28 + 1 + write-only + + + P29 + PIO Enable + 29 + 1 + write-only + + + P30 + PIO Enable + 30 + 1 + write-only + + + P31 + PIO Enable + 31 + 1 + write-only + + + + + PDR + PIO Disable Register + 0x00000004 + 32 + write-only + + + P0 + PIO Disable + 0 + 1 + write-only + + + P1 + PIO Disable + 1 + 1 + write-only + + + P2 + PIO Disable + 2 + 1 + write-only + + + P3 + PIO Disable + 3 + 1 + write-only + + + P4 + PIO Disable + 4 + 1 + write-only + + + P5 + PIO Disable + 5 + 1 + write-only + + + P6 + PIO Disable + 6 + 1 + write-only + + + P7 + PIO Disable + 7 + 1 + write-only + + + P8 + PIO Disable + 8 + 1 + write-only + + + P9 + PIO Disable + 9 + 1 + write-only + + + P10 + PIO Disable + 10 + 1 + write-only + + + P11 + PIO Disable + 11 + 1 + write-only + + + P12 + PIO Disable + 12 + 1 + write-only + + + P13 + PIO Disable + 13 + 1 + write-only + + + P14 + PIO Disable + 14 + 1 + write-only + + + P15 + PIO Disable + 15 + 1 + write-only + + + P16 + PIO Disable + 16 + 1 + write-only + + + P17 + PIO Disable + 17 + 1 + write-only + + + P18 + PIO Disable + 18 + 1 + write-only + + + P19 + PIO Disable + 19 + 1 + write-only + + + P20 + PIO Disable + 20 + 1 + write-only + + + P21 + PIO Disable + 21 + 1 + write-only + + + P22 + PIO Disable + 22 + 1 + write-only + + + P23 + PIO Disable + 23 + 1 + write-only + + + P24 + PIO Disable + 24 + 1 + write-only + + + P25 + PIO Disable + 25 + 1 + write-only + + + P26 + PIO Disable + 26 + 1 + write-only + + + P27 + PIO Disable + 27 + 1 + write-only + + + P28 + PIO Disable + 28 + 1 + write-only + + + P29 + PIO Disable + 29 + 1 + write-only + + + P30 + PIO Disable + 30 + 1 + write-only + + + P31 + PIO Disable + 31 + 1 + write-only + + + + + PSR + PIO Status Register + 0x00000008 + 32 + read-only + + + P0 + PIO Status + 0 + 1 + read-only + + + P1 + PIO Status + 1 + 1 + read-only + + + P2 + PIO Status + 2 + 1 + read-only + + + P3 + PIO Status + 3 + 1 + read-only + + + P4 + PIO Status + 4 + 1 + read-only + + + P5 + PIO Status + 5 + 1 + read-only + + + P6 + PIO Status + 6 + 1 + read-only + + + P7 + PIO Status + 7 + 1 + read-only + + + P8 + PIO Status + 8 + 1 + read-only + + + P9 + PIO Status + 9 + 1 + read-only + + + P10 + PIO Status + 10 + 1 + read-only + + + P11 + PIO Status + 11 + 1 + read-only + + + P12 + PIO Status + 12 + 1 + read-only + + + P13 + PIO Status + 13 + 1 + read-only + + + P14 + PIO Status + 14 + 1 + read-only + + + P15 + PIO Status + 15 + 1 + read-only + + + P16 + PIO Status + 16 + 1 + read-only + + + P17 + PIO Status + 17 + 1 + read-only + + + P18 + PIO Status + 18 + 1 + read-only + + + P19 + PIO Status + 19 + 1 + read-only + + + P20 + PIO Status + 20 + 1 + read-only + + + P21 + PIO Status + 21 + 1 + read-only + + + P22 + PIO Status + 22 + 1 + read-only + + + P23 + PIO Status + 23 + 1 + read-only + + + P24 + PIO Status + 24 + 1 + read-only + + + P25 + PIO Status + 25 + 1 + read-only + + + P26 + PIO Status + 26 + 1 + read-only + + + P27 + PIO Status + 27 + 1 + read-only + + + P28 + PIO Status + 28 + 1 + read-only + + + P29 + PIO Status + 29 + 1 + read-only + + + P30 + PIO Status + 30 + 1 + read-only + + + P31 + PIO Status + 31 + 1 + read-only + + + + + OER + Output Enable Register + 0x00000010 + 32 + write-only + + + P0 + Output Enable + 0 + 1 + write-only + + + P1 + Output Enable + 1 + 1 + write-only + + + P2 + Output Enable + 2 + 1 + write-only + + + P3 + Output Enable + 3 + 1 + write-only + + + P4 + Output Enable + 4 + 1 + write-only + + + P5 + Output Enable + 5 + 1 + write-only + + + P6 + Output Enable + 6 + 1 + write-only + + + P7 + Output Enable + 7 + 1 + write-only + + + P8 + Output Enable + 8 + 1 + write-only + + + P9 + Output Enable + 9 + 1 + write-only + + + P10 + Output Enable + 10 + 1 + write-only + + + P11 + Output Enable + 11 + 1 + write-only + + + P12 + Output Enable + 12 + 1 + write-only + + + P13 + Output Enable + 13 + 1 + write-only + + + P14 + Output Enable + 14 + 1 + write-only + + + P15 + Output Enable + 15 + 1 + write-only + + + P16 + Output Enable + 16 + 1 + write-only + + + P17 + Output Enable + 17 + 1 + write-only + + + P18 + Output Enable + 18 + 1 + write-only + + + P19 + Output Enable + 19 + 1 + write-only + + + P20 + Output Enable + 20 + 1 + write-only + + + P21 + Output Enable + 21 + 1 + write-only + + + P22 + Output Enable + 22 + 1 + write-only + + + P23 + Output Enable + 23 + 1 + write-only + + + P24 + Output Enable + 24 + 1 + write-only + + + P25 + Output Enable + 25 + 1 + write-only + + + P26 + Output Enable + 26 + 1 + write-only + + + P27 + Output Enable + 27 + 1 + write-only + + + P28 + Output Enable + 28 + 1 + write-only + + + P29 + Output Enable + 29 + 1 + write-only + + + P30 + Output Enable + 30 + 1 + write-only + + + P31 + Output Enable + 31 + 1 + write-only + + + + + ODR + Output Disable Register + 0x00000014 + 32 + write-only + + + P0 + Output Disable + 0 + 1 + write-only + + + P1 + Output Disable + 1 + 1 + write-only + + + P2 + Output Disable + 2 + 1 + write-only + + + P3 + Output Disable + 3 + 1 + write-only + + + P4 + Output Disable + 4 + 1 + write-only + + + P5 + Output Disable + 5 + 1 + write-only + + + P6 + Output Disable + 6 + 1 + write-only + + + P7 + Output Disable + 7 + 1 + write-only + + + P8 + Output Disable + 8 + 1 + write-only + + + P9 + Output Disable + 9 + 1 + write-only + + + P10 + Output Disable + 10 + 1 + write-only + + + P11 + Output Disable + 11 + 1 + write-only + + + P12 + Output Disable + 12 + 1 + write-only + + + P13 + Output Disable + 13 + 1 + write-only + + + P14 + Output Disable + 14 + 1 + write-only + + + P15 + Output Disable + 15 + 1 + write-only + + + P16 + Output Disable + 16 + 1 + write-only + + + P17 + Output Disable + 17 + 1 + write-only + + + P18 + Output Disable + 18 + 1 + write-only + + + P19 + Output Disable + 19 + 1 + write-only + + + P20 + Output Disable + 20 + 1 + write-only + + + P21 + Output Disable + 21 + 1 + write-only + + + P22 + Output Disable + 22 + 1 + write-only + + + P23 + Output Disable + 23 + 1 + write-only + + + P24 + Output Disable + 24 + 1 + write-only + + + P25 + Output Disable + 25 + 1 + write-only + + + P26 + Output Disable + 26 + 1 + write-only + + + P27 + Output Disable + 27 + 1 + write-only + + + P28 + Output Disable + 28 + 1 + write-only + + + P29 + Output Disable + 29 + 1 + write-only + + + P30 + Output Disable + 30 + 1 + write-only + + + P31 + Output Disable + 31 + 1 + write-only + + + + + OSR + Output Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + P0 + Output Status + 0 + 1 + read-only + + + P1 + Output Status + 1 + 1 + read-only + + + P2 + Output Status + 2 + 1 + read-only + + + P3 + Output Status + 3 + 1 + read-only + + + P4 + Output Status + 4 + 1 + read-only + + + P5 + Output Status + 5 + 1 + read-only + + + P6 + Output Status + 6 + 1 + read-only + + + P7 + Output Status + 7 + 1 + read-only + + + P8 + Output Status + 8 + 1 + read-only + + + P9 + Output Status + 9 + 1 + read-only + + + P10 + Output Status + 10 + 1 + read-only + + + P11 + Output Status + 11 + 1 + read-only + + + P12 + Output Status + 12 + 1 + read-only + + + P13 + Output Status + 13 + 1 + read-only + + + P14 + Output Status + 14 + 1 + read-only + + + P15 + Output Status + 15 + 1 + read-only + + + P16 + Output Status + 16 + 1 + read-only + + + P17 + Output Status + 17 + 1 + read-only + + + P18 + Output Status + 18 + 1 + read-only + + + P19 + Output Status + 19 + 1 + read-only + + + P20 + Output Status + 20 + 1 + read-only + + + P21 + Output Status + 21 + 1 + read-only + + + P22 + Output Status + 22 + 1 + read-only + + + P23 + Output Status + 23 + 1 + read-only + + + P24 + Output Status + 24 + 1 + read-only + + + P25 + Output Status + 25 + 1 + read-only + + + P26 + Output Status + 26 + 1 + read-only + + + P27 + Output Status + 27 + 1 + read-only + + + P28 + Output Status + 28 + 1 + read-only + + + P29 + Output Status + 29 + 1 + read-only + + + P30 + Output Status + 30 + 1 + read-only + + + P31 + Output Status + 31 + 1 + read-only + + + + + IFER + Glitch Input Filter Enable Register + 0x00000020 + 32 + write-only + + + P0 + Input Filter Enable + 0 + 1 + write-only + + + P1 + Input Filter Enable + 1 + 1 + write-only + + + P2 + Input Filter Enable + 2 + 1 + write-only + + + P3 + Input Filter Enable + 3 + 1 + write-only + + + P4 + Input Filter Enable + 4 + 1 + write-only + + + P5 + Input Filter Enable + 5 + 1 + write-only + + + P6 + Input Filter Enable + 6 + 1 + write-only + + + P7 + Input Filter Enable + 7 + 1 + write-only + + + P8 + Input Filter Enable + 8 + 1 + write-only + + + P9 + Input Filter Enable + 9 + 1 + write-only + + + P10 + Input Filter Enable + 10 + 1 + write-only + + + P11 + Input Filter Enable + 11 + 1 + write-only + + + P12 + Input Filter Enable + 12 + 1 + write-only + + + P13 + Input Filter Enable + 13 + 1 + write-only + + + P14 + Input Filter Enable + 14 + 1 + write-only + + + P15 + Input Filter Enable + 15 + 1 + write-only + + + P16 + Input Filter Enable + 16 + 1 + write-only + + + P17 + Input Filter Enable + 17 + 1 + write-only + + + P18 + Input Filter Enable + 18 + 1 + write-only + + + P19 + Input Filter Enable + 19 + 1 + write-only + + + P20 + Input Filter Enable + 20 + 1 + write-only + + + P21 + Input Filter Enable + 21 + 1 + write-only + + + P22 + Input Filter Enable + 22 + 1 + write-only + + + P23 + Input Filter Enable + 23 + 1 + write-only + + + P24 + Input Filter Enable + 24 + 1 + write-only + + + P25 + Input Filter Enable + 25 + 1 + write-only + + + P26 + Input Filter Enable + 26 + 1 + write-only + + + P27 + Input Filter Enable + 27 + 1 + write-only + + + P28 + Input Filter Enable + 28 + 1 + write-only + + + P29 + Input Filter Enable + 29 + 1 + write-only + + + P30 + Input Filter Enable + 30 + 1 + write-only + + + P31 + Input Filter Enable + 31 + 1 + write-only + + + + + IFDR + Glitch Input Filter Disable Register + 0x00000024 + 32 + write-only + + + P0 + Input Filter Disable + 0 + 1 + write-only + + + P1 + Input Filter Disable + 1 + 1 + write-only + + + P2 + Input Filter Disable + 2 + 1 + write-only + + + P3 + Input Filter Disable + 3 + 1 + write-only + + + P4 + Input Filter Disable + 4 + 1 + write-only + + + P5 + Input Filter Disable + 5 + 1 + write-only + + + P6 + Input Filter Disable + 6 + 1 + write-only + + + P7 + Input Filter Disable + 7 + 1 + write-only + + + P8 + Input Filter Disable + 8 + 1 + write-only + + + P9 + Input Filter Disable + 9 + 1 + write-only + + + P10 + Input Filter Disable + 10 + 1 + write-only + + + P11 + Input Filter Disable + 11 + 1 + write-only + + + P12 + Input Filter Disable + 12 + 1 + write-only + + + P13 + Input Filter Disable + 13 + 1 + write-only + + + P14 + Input Filter Disable + 14 + 1 + write-only + + + P15 + Input Filter Disable + 15 + 1 + write-only + + + P16 + Input Filter Disable + 16 + 1 + write-only + + + P17 + Input Filter Disable + 17 + 1 + write-only + + + P18 + Input Filter Disable + 18 + 1 + write-only + + + P19 + Input Filter Disable + 19 + 1 + write-only + + + P20 + Input Filter Disable + 20 + 1 + write-only + + + P21 + Input Filter Disable + 21 + 1 + write-only + + + P22 + Input Filter Disable + 22 + 1 + write-only + + + P23 + Input Filter Disable + 23 + 1 + write-only + + + P24 + Input Filter Disable + 24 + 1 + write-only + + + P25 + Input Filter Disable + 25 + 1 + write-only + + + P26 + Input Filter Disable + 26 + 1 + write-only + + + P27 + Input Filter Disable + 27 + 1 + write-only + + + P28 + Input Filter Disable + 28 + 1 + write-only + + + P29 + Input Filter Disable + 29 + 1 + write-only + + + P30 + Input Filter Disable + 30 + 1 + write-only + + + P31 + Input Filter Disable + 31 + 1 + write-only + + + + + IFSR + Glitch Input Filter Status Register + 0x00000028 + 32 + read-only + 0x00000000 + + + P0 + Input Filer Status + 0 + 1 + read-only + + + P1 + Input Filer Status + 1 + 1 + read-only + + + P2 + Input Filer Status + 2 + 1 + read-only + + + P3 + Input Filer Status + 3 + 1 + read-only + + + P4 + Input Filer Status + 4 + 1 + read-only + + + P5 + Input Filer Status + 5 + 1 + read-only + + + P6 + Input Filer Status + 6 + 1 + read-only + + + P7 + Input Filer Status + 7 + 1 + read-only + + + P8 + Input Filer Status + 8 + 1 + read-only + + + P9 + Input Filer Status + 9 + 1 + read-only + + + P10 + Input Filer Status + 10 + 1 + read-only + + + P11 + Input Filer Status + 11 + 1 + read-only + + + P12 + Input Filer Status + 12 + 1 + read-only + + + P13 + Input Filer Status + 13 + 1 + read-only + + + P14 + Input Filer Status + 14 + 1 + read-only + + + P15 + Input Filer Status + 15 + 1 + read-only + + + P16 + Input Filer Status + 16 + 1 + read-only + + + P17 + Input Filer Status + 17 + 1 + read-only + + + P18 + Input Filer Status + 18 + 1 + read-only + + + P19 + Input Filer Status + 19 + 1 + read-only + + + P20 + Input Filer Status + 20 + 1 + read-only + + + P21 + Input Filer Status + 21 + 1 + read-only + + + P22 + Input Filer Status + 22 + 1 + read-only + + + P23 + Input Filer Status + 23 + 1 + read-only + + + P24 + Input Filer Status + 24 + 1 + read-only + + + P25 + Input Filer Status + 25 + 1 + read-only + + + P26 + Input Filer Status + 26 + 1 + read-only + + + P27 + Input Filer Status + 27 + 1 + read-only + + + P28 + Input Filer Status + 28 + 1 + read-only + + + P29 + Input Filer Status + 29 + 1 + read-only + + + P30 + Input Filer Status + 30 + 1 + read-only + + + P31 + Input Filer Status + 31 + 1 + read-only + + + + + SODR + Set Output Data Register + 0x00000030 + 32 + write-only + + + P0 + Set Output Data + 0 + 1 + write-only + + + P1 + Set Output Data + 1 + 1 + write-only + + + P2 + Set Output Data + 2 + 1 + write-only + + + P3 + Set Output Data + 3 + 1 + write-only + + + P4 + Set Output Data + 4 + 1 + write-only + + + P5 + Set Output Data + 5 + 1 + write-only + + + P6 + Set Output Data + 6 + 1 + write-only + + + P7 + Set Output Data + 7 + 1 + write-only + + + P8 + Set Output Data + 8 + 1 + write-only + + + P9 + Set Output Data + 9 + 1 + write-only + + + P10 + Set Output Data + 10 + 1 + write-only + + + P11 + Set Output Data + 11 + 1 + write-only + + + P12 + Set Output Data + 12 + 1 + write-only + + + P13 + Set Output Data + 13 + 1 + write-only + + + P14 + Set Output Data + 14 + 1 + write-only + + + P15 + Set Output Data + 15 + 1 + write-only + + + P16 + Set Output Data + 16 + 1 + write-only + + + P17 + Set Output Data + 17 + 1 + write-only + + + P18 + Set Output Data + 18 + 1 + write-only + + + P19 + Set Output Data + 19 + 1 + write-only + + + P20 + Set Output Data + 20 + 1 + write-only + + + P21 + Set Output Data + 21 + 1 + write-only + + + P22 + Set Output Data + 22 + 1 + write-only + + + P23 + Set Output Data + 23 + 1 + write-only + + + P24 + Set Output Data + 24 + 1 + write-only + + + P25 + Set Output Data + 25 + 1 + write-only + + + P26 + Set Output Data + 26 + 1 + write-only + + + P27 + Set Output Data + 27 + 1 + write-only + + + P28 + Set Output Data + 28 + 1 + write-only + + + P29 + Set Output Data + 29 + 1 + write-only + + + P30 + Set Output Data + 30 + 1 + write-only + + + P31 + Set Output Data + 31 + 1 + write-only + + + + + CODR + Clear Output Data Register + 0x00000034 + 32 + write-only + + + P0 + Clear Output Data + 0 + 1 + write-only + + + P1 + Clear Output Data + 1 + 1 + write-only + + + P2 + Clear Output Data + 2 + 1 + write-only + + + P3 + Clear Output Data + 3 + 1 + write-only + + + P4 + Clear Output Data + 4 + 1 + write-only + + + P5 + Clear Output Data + 5 + 1 + write-only + + + P6 + Clear Output Data + 6 + 1 + write-only + + + P7 + Clear Output Data + 7 + 1 + write-only + + + P8 + Clear Output Data + 8 + 1 + write-only + + + P9 + Clear Output Data + 9 + 1 + write-only + + + P10 + Clear Output Data + 10 + 1 + write-only + + + P11 + Clear Output Data + 11 + 1 + write-only + + + P12 + Clear Output Data + 12 + 1 + write-only + + + P13 + Clear Output Data + 13 + 1 + write-only + + + P14 + Clear Output Data + 14 + 1 + write-only + + + P15 + Clear Output Data + 15 + 1 + write-only + + + P16 + Clear Output Data + 16 + 1 + write-only + + + P17 + Clear Output Data + 17 + 1 + write-only + + + P18 + Clear Output Data + 18 + 1 + write-only + + + P19 + Clear Output Data + 19 + 1 + write-only + + + P20 + Clear Output Data + 20 + 1 + write-only + + + P21 + Clear Output Data + 21 + 1 + write-only + + + P22 + Clear Output Data + 22 + 1 + write-only + + + P23 + Clear Output Data + 23 + 1 + write-only + + + P24 + Clear Output Data + 24 + 1 + write-only + + + P25 + Clear Output Data + 25 + 1 + write-only + + + P26 + Clear Output Data + 26 + 1 + write-only + + + P27 + Clear Output Data + 27 + 1 + write-only + + + P28 + Clear Output Data + 28 + 1 + write-only + + + P29 + Clear Output Data + 29 + 1 + write-only + + + P30 + Clear Output Data + 30 + 1 + write-only + + + P31 + Clear Output Data + 31 + 1 + write-only + + + + + ODSR + Output Data Status Register + 0x00000038 + 32 + read-write + + + P0 + Output Data Status + 0 + 1 + read-write + + + P1 + Output Data Status + 1 + 1 + read-write + + + P2 + Output Data Status + 2 + 1 + read-write + + + P3 + Output Data Status + 3 + 1 + read-write + + + P4 + Output Data Status + 4 + 1 + read-write + + + P5 + Output Data Status + 5 + 1 + read-write + + + P6 + Output Data Status + 6 + 1 + read-write + + + P7 + Output Data Status + 7 + 1 + read-write + + + P8 + Output Data Status + 8 + 1 + read-write + + + P9 + Output Data Status + 9 + 1 + read-write + + + P10 + Output Data Status + 10 + 1 + read-write + + + P11 + Output Data Status + 11 + 1 + read-write + + + P12 + Output Data Status + 12 + 1 + read-write + + + P13 + Output Data Status + 13 + 1 + read-write + + + P14 + Output Data Status + 14 + 1 + read-write + + + P15 + Output Data Status + 15 + 1 + read-write + + + P16 + Output Data Status + 16 + 1 + read-write + + + P17 + Output Data Status + 17 + 1 + read-write + + + P18 + Output Data Status + 18 + 1 + read-write + + + P19 + Output Data Status + 19 + 1 + read-write + + + P20 + Output Data Status + 20 + 1 + read-write + + + P21 + Output Data Status + 21 + 1 + read-write + + + P22 + Output Data Status + 22 + 1 + read-write + + + P23 + Output Data Status + 23 + 1 + read-write + + + P24 + Output Data Status + 24 + 1 + read-write + + + P25 + Output Data Status + 25 + 1 + read-write + + + P26 + Output Data Status + 26 + 1 + read-write + + + P27 + Output Data Status + 27 + 1 + read-write + + + P28 + Output Data Status + 28 + 1 + read-write + + + P29 + Output Data Status + 29 + 1 + read-write + + + P30 + Output Data Status + 30 + 1 + read-write + + + P31 + Output Data Status + 31 + 1 + read-write + + + + + PDSR + Pin Data Status Register + 0x0000003C + 32 + read-only + + + P0 + Output Data Status + 0 + 1 + read-only + + + P1 + Output Data Status + 1 + 1 + read-only + + + P2 + Output Data Status + 2 + 1 + read-only + + + P3 + Output Data Status + 3 + 1 + read-only + + + P4 + Output Data Status + 4 + 1 + read-only + + + P5 + Output Data Status + 5 + 1 + read-only + + + P6 + Output Data Status + 6 + 1 + read-only + + + P7 + Output Data Status + 7 + 1 + read-only + + + P8 + Output Data Status + 8 + 1 + read-only + + + P9 + Output Data Status + 9 + 1 + read-only + + + P10 + Output Data Status + 10 + 1 + read-only + + + P11 + Output Data Status + 11 + 1 + read-only + + + P12 + Output Data Status + 12 + 1 + read-only + + + P13 + Output Data Status + 13 + 1 + read-only + + + P14 + Output Data Status + 14 + 1 + read-only + + + P15 + Output Data Status + 15 + 1 + read-only + + + P16 + Output Data Status + 16 + 1 + read-only + + + P17 + Output Data Status + 17 + 1 + read-only + + + P18 + Output Data Status + 18 + 1 + read-only + + + P19 + Output Data Status + 19 + 1 + read-only + + + P20 + Output Data Status + 20 + 1 + read-only + + + P21 + Output Data Status + 21 + 1 + read-only + + + P22 + Output Data Status + 22 + 1 + read-only + + + P23 + Output Data Status + 23 + 1 + read-only + + + P24 + Output Data Status + 24 + 1 + read-only + + + P25 + Output Data Status + 25 + 1 + read-only + + + P26 + Output Data Status + 26 + 1 + read-only + + + P27 + Output Data Status + 27 + 1 + read-only + + + P28 + Output Data Status + 28 + 1 + read-only + + + P29 + Output Data Status + 29 + 1 + read-only + + + P30 + Output Data Status + 30 + 1 + read-only + + + P31 + Output Data Status + 31 + 1 + read-only + + + + + IER + Interrupt Enable Register + 0x00000040 + 32 + write-only + + + P0 + Input Change Interrupt Enable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Enable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Enable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Enable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Enable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Enable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Enable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Enable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Enable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Enable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Enable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Enable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Enable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Enable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Enable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Enable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Enable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Enable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Enable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Enable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Enable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Enable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Enable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Enable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Enable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Enable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Enable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Enable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Enable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Enable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Enable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Enable + 31 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000044 + 32 + write-only + + + P0 + Input Change Interrupt Disable + 0 + 1 + write-only + + + P1 + Input Change Interrupt Disable + 1 + 1 + write-only + + + P2 + Input Change Interrupt Disable + 2 + 1 + write-only + + + P3 + Input Change Interrupt Disable + 3 + 1 + write-only + + + P4 + Input Change Interrupt Disable + 4 + 1 + write-only + + + P5 + Input Change Interrupt Disable + 5 + 1 + write-only + + + P6 + Input Change Interrupt Disable + 6 + 1 + write-only + + + P7 + Input Change Interrupt Disable + 7 + 1 + write-only + + + P8 + Input Change Interrupt Disable + 8 + 1 + write-only + + + P9 + Input Change Interrupt Disable + 9 + 1 + write-only + + + P10 + Input Change Interrupt Disable + 10 + 1 + write-only + + + P11 + Input Change Interrupt Disable + 11 + 1 + write-only + + + P12 + Input Change Interrupt Disable + 12 + 1 + write-only + + + P13 + Input Change Interrupt Disable + 13 + 1 + write-only + + + P14 + Input Change Interrupt Disable + 14 + 1 + write-only + + + P15 + Input Change Interrupt Disable + 15 + 1 + write-only + + + P16 + Input Change Interrupt Disable + 16 + 1 + write-only + + + P17 + Input Change Interrupt Disable + 17 + 1 + write-only + + + P18 + Input Change Interrupt Disable + 18 + 1 + write-only + + + P19 + Input Change Interrupt Disable + 19 + 1 + write-only + + + P20 + Input Change Interrupt Disable + 20 + 1 + write-only + + + P21 + Input Change Interrupt Disable + 21 + 1 + write-only + + + P22 + Input Change Interrupt Disable + 22 + 1 + write-only + + + P23 + Input Change Interrupt Disable + 23 + 1 + write-only + + + P24 + Input Change Interrupt Disable + 24 + 1 + write-only + + + P25 + Input Change Interrupt Disable + 25 + 1 + write-only + + + P26 + Input Change Interrupt Disable + 26 + 1 + write-only + + + P27 + Input Change Interrupt Disable + 27 + 1 + write-only + + + P28 + Input Change Interrupt Disable + 28 + 1 + write-only + + + P29 + Input Change Interrupt Disable + 29 + 1 + write-only + + + P30 + Input Change Interrupt Disable + 30 + 1 + write-only + + + P31 + Input Change Interrupt Disable + 31 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000048 + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Mask + 0 + 1 + read-only + + + P1 + Input Change Interrupt Mask + 1 + 1 + read-only + + + P2 + Input Change Interrupt Mask + 2 + 1 + read-only + + + P3 + Input Change Interrupt Mask + 3 + 1 + read-only + + + P4 + Input Change Interrupt Mask + 4 + 1 + read-only + + + P5 + Input Change Interrupt Mask + 5 + 1 + read-only + + + P6 + Input Change Interrupt Mask + 6 + 1 + read-only + + + P7 + Input Change Interrupt Mask + 7 + 1 + read-only + + + P8 + Input Change Interrupt Mask + 8 + 1 + read-only + + + P9 + Input Change Interrupt Mask + 9 + 1 + read-only + + + P10 + Input Change Interrupt Mask + 10 + 1 + read-only + + + P11 + Input Change Interrupt Mask + 11 + 1 + read-only + + + P12 + Input Change Interrupt Mask + 12 + 1 + read-only + + + P13 + Input Change Interrupt Mask + 13 + 1 + read-only + + + P14 + Input Change Interrupt Mask + 14 + 1 + read-only + + + P15 + Input Change Interrupt Mask + 15 + 1 + read-only + + + P16 + Input Change Interrupt Mask + 16 + 1 + read-only + + + P17 + Input Change Interrupt Mask + 17 + 1 + read-only + + + P18 + Input Change Interrupt Mask + 18 + 1 + read-only + + + P19 + Input Change Interrupt Mask + 19 + 1 + read-only + + + P20 + Input Change Interrupt Mask + 20 + 1 + read-only + + + P21 + Input Change Interrupt Mask + 21 + 1 + read-only + + + P22 + Input Change Interrupt Mask + 22 + 1 + read-only + + + P23 + Input Change Interrupt Mask + 23 + 1 + read-only + + + P24 + Input Change Interrupt Mask + 24 + 1 + read-only + + + P25 + Input Change Interrupt Mask + 25 + 1 + read-only + + + P26 + Input Change Interrupt Mask + 26 + 1 + read-only + + + P27 + Input Change Interrupt Mask + 27 + 1 + read-only + + + P28 + Input Change Interrupt Mask + 28 + 1 + read-only + + + P29 + Input Change Interrupt Mask + 29 + 1 + read-only + + + P30 + Input Change Interrupt Mask + 30 + 1 + read-only + + + P31 + Input Change Interrupt Mask + 31 + 1 + read-only + + + + + ISR + Interrupt Status Register + 0x0000004C + 32 + read-only + 0x00000000 + + + P0 + Input Change Interrupt Status + 0 + 1 + read-only + + + P1 + Input Change Interrupt Status + 1 + 1 + read-only + + + P2 + Input Change Interrupt Status + 2 + 1 + read-only + + + P3 + Input Change Interrupt Status + 3 + 1 + read-only + + + P4 + Input Change Interrupt Status + 4 + 1 + read-only + + + P5 + Input Change Interrupt Status + 5 + 1 + read-only + + + P6 + Input Change Interrupt Status + 6 + 1 + read-only + + + P7 + Input Change Interrupt Status + 7 + 1 + read-only + + + P8 + Input Change Interrupt Status + 8 + 1 + read-only + + + P9 + Input Change Interrupt Status + 9 + 1 + read-only + + + P10 + Input Change Interrupt Status + 10 + 1 + read-only + + + P11 + Input Change Interrupt Status + 11 + 1 + read-only + + + P12 + Input Change Interrupt Status + 12 + 1 + read-only + + + P13 + Input Change Interrupt Status + 13 + 1 + read-only + + + P14 + Input Change Interrupt Status + 14 + 1 + read-only + + + P15 + Input Change Interrupt Status + 15 + 1 + read-only + + + P16 + Input Change Interrupt Status + 16 + 1 + read-only + + + P17 + Input Change Interrupt Status + 17 + 1 + read-only + + + P18 + Input Change Interrupt Status + 18 + 1 + read-only + + + P19 + Input Change Interrupt Status + 19 + 1 + read-only + + + P20 + Input Change Interrupt Status + 20 + 1 + read-only + + + P21 + Input Change Interrupt Status + 21 + 1 + read-only + + + P22 + Input Change Interrupt Status + 22 + 1 + read-only + + + P23 + Input Change Interrupt Status + 23 + 1 + read-only + + + P24 + Input Change Interrupt Status + 24 + 1 + read-only + + + P25 + Input Change Interrupt Status + 25 + 1 + read-only + + + P26 + Input Change Interrupt Status + 26 + 1 + read-only + + + P27 + Input Change Interrupt Status + 27 + 1 + read-only + + + P28 + Input Change Interrupt Status + 28 + 1 + read-only + + + P29 + Input Change Interrupt Status + 29 + 1 + read-only + + + P30 + Input Change Interrupt Status + 30 + 1 + read-only + + + P31 + Input Change Interrupt Status + 31 + 1 + read-only + + + + + MDER + Multi-driver Enable Register + 0x00000050 + 32 + write-only + + + P0 + Multi Drive Enable. + 0 + 1 + write-only + + + P1 + Multi Drive Enable. + 1 + 1 + write-only + + + P2 + Multi Drive Enable. + 2 + 1 + write-only + + + P3 + Multi Drive Enable. + 3 + 1 + write-only + + + P4 + Multi Drive Enable. + 4 + 1 + write-only + + + P5 + Multi Drive Enable. + 5 + 1 + write-only + + + P6 + Multi Drive Enable. + 6 + 1 + write-only + + + P7 + Multi Drive Enable. + 7 + 1 + write-only + + + P8 + Multi Drive Enable. + 8 + 1 + write-only + + + P9 + Multi Drive Enable. + 9 + 1 + write-only + + + P10 + Multi Drive Enable. + 10 + 1 + write-only + + + P11 + Multi Drive Enable. + 11 + 1 + write-only + + + P12 + Multi Drive Enable. + 12 + 1 + write-only + + + P13 + Multi Drive Enable. + 13 + 1 + write-only + + + P14 + Multi Drive Enable. + 14 + 1 + write-only + + + P15 + Multi Drive Enable. + 15 + 1 + write-only + + + P16 + Multi Drive Enable. + 16 + 1 + write-only + + + P17 + Multi Drive Enable. + 17 + 1 + write-only + + + P18 + Multi Drive Enable. + 18 + 1 + write-only + + + P19 + Multi Drive Enable. + 19 + 1 + write-only + + + P20 + Multi Drive Enable. + 20 + 1 + write-only + + + P21 + Multi Drive Enable. + 21 + 1 + write-only + + + P22 + Multi Drive Enable. + 22 + 1 + write-only + + + P23 + Multi Drive Enable. + 23 + 1 + write-only + + + P24 + Multi Drive Enable. + 24 + 1 + write-only + + + P25 + Multi Drive Enable. + 25 + 1 + write-only + + + P26 + Multi Drive Enable. + 26 + 1 + write-only + + + P27 + Multi Drive Enable. + 27 + 1 + write-only + + + P28 + Multi Drive Enable. + 28 + 1 + write-only + + + P29 + Multi Drive Enable. + 29 + 1 + write-only + + + P30 + Multi Drive Enable. + 30 + 1 + write-only + + + P31 + Multi Drive Enable. + 31 + 1 + write-only + + + + + MDDR + Multi-driver Disable Register + 0x00000054 + 32 + write-only + + + P0 + Multi Drive Disable. + 0 + 1 + write-only + + + P1 + Multi Drive Disable. + 1 + 1 + write-only + + + P2 + Multi Drive Disable. + 2 + 1 + write-only + + + P3 + Multi Drive Disable. + 3 + 1 + write-only + + + P4 + Multi Drive Disable. + 4 + 1 + write-only + + + P5 + Multi Drive Disable. + 5 + 1 + write-only + + + P6 + Multi Drive Disable. + 6 + 1 + write-only + + + P7 + Multi Drive Disable. + 7 + 1 + write-only + + + P8 + Multi Drive Disable. + 8 + 1 + write-only + + + P9 + Multi Drive Disable. + 9 + 1 + write-only + + + P10 + Multi Drive Disable. + 10 + 1 + write-only + + + P11 + Multi Drive Disable. + 11 + 1 + write-only + + + P12 + Multi Drive Disable. + 12 + 1 + write-only + + + P13 + Multi Drive Disable. + 13 + 1 + write-only + + + P14 + Multi Drive Disable. + 14 + 1 + write-only + + + P15 + Multi Drive Disable. + 15 + 1 + write-only + + + P16 + Multi Drive Disable. + 16 + 1 + write-only + + + P17 + Multi Drive Disable. + 17 + 1 + write-only + + + P18 + Multi Drive Disable. + 18 + 1 + write-only + + + P19 + Multi Drive Disable. + 19 + 1 + write-only + + + P20 + Multi Drive Disable. + 20 + 1 + write-only + + + P21 + Multi Drive Disable. + 21 + 1 + write-only + + + P22 + Multi Drive Disable. + 22 + 1 + write-only + + + P23 + Multi Drive Disable. + 23 + 1 + write-only + + + P24 + Multi Drive Disable. + 24 + 1 + write-only + + + P25 + Multi Drive Disable. + 25 + 1 + write-only + + + P26 + Multi Drive Disable. + 26 + 1 + write-only + + + P27 + Multi Drive Disable. + 27 + 1 + write-only + + + P28 + Multi Drive Disable. + 28 + 1 + write-only + + + P29 + Multi Drive Disable. + 29 + 1 + write-only + + + P30 + Multi Drive Disable. + 30 + 1 + write-only + + + P31 + Multi Drive Disable. + 31 + 1 + write-only + + + + + MDSR + Multi-driver Status Register + 0x00000058 + 32 + read-only + 0x00000000 + + + P0 + Multi Drive Status. + 0 + 1 + read-only + + + P1 + Multi Drive Status. + 1 + 1 + read-only + + + P2 + Multi Drive Status. + 2 + 1 + read-only + + + P3 + Multi Drive Status. + 3 + 1 + read-only + + + P4 + Multi Drive Status. + 4 + 1 + read-only + + + P5 + Multi Drive Status. + 5 + 1 + read-only + + + P6 + Multi Drive Status. + 6 + 1 + read-only + + + P7 + Multi Drive Status. + 7 + 1 + read-only + + + P8 + Multi Drive Status. + 8 + 1 + read-only + + + P9 + Multi Drive Status. + 9 + 1 + read-only + + + P10 + Multi Drive Status. + 10 + 1 + read-only + + + P11 + Multi Drive Status. + 11 + 1 + read-only + + + P12 + Multi Drive Status. + 12 + 1 + read-only + + + P13 + Multi Drive Status. + 13 + 1 + read-only + + + P14 + Multi Drive Status. + 14 + 1 + read-only + + + P15 + Multi Drive Status. + 15 + 1 + read-only + + + P16 + Multi Drive Status. + 16 + 1 + read-only + + + P17 + Multi Drive Status. + 17 + 1 + read-only + + + P18 + Multi Drive Status. + 18 + 1 + read-only + + + P19 + Multi Drive Status. + 19 + 1 + read-only + + + P20 + Multi Drive Status. + 20 + 1 + read-only + + + P21 + Multi Drive Status. + 21 + 1 + read-only + + + P22 + Multi Drive Status. + 22 + 1 + read-only + + + P23 + Multi Drive Status. + 23 + 1 + read-only + + + P24 + Multi Drive Status. + 24 + 1 + read-only + + + P25 + Multi Drive Status. + 25 + 1 + read-only + + + P26 + Multi Drive Status. + 26 + 1 + read-only + + + P27 + Multi Drive Status. + 27 + 1 + read-only + + + P28 + Multi Drive Status. + 28 + 1 + read-only + + + P29 + Multi Drive Status. + 29 + 1 + read-only + + + P30 + Multi Drive Status. + 30 + 1 + read-only + + + P31 + Multi Drive Status. + 31 + 1 + read-only + + + + + PUDR + Pull-up Disable Register + 0x00000060 + 32 + write-only + + + P0 + Pull Up Disable. + 0 + 1 + write-only + + + P1 + Pull Up Disable. + 1 + 1 + write-only + + + P2 + Pull Up Disable. + 2 + 1 + write-only + + + P3 + Pull Up Disable. + 3 + 1 + write-only + + + P4 + Pull Up Disable. + 4 + 1 + write-only + + + P5 + Pull Up Disable. + 5 + 1 + write-only + + + P6 + Pull Up Disable. + 6 + 1 + write-only + + + P7 + Pull Up Disable. + 7 + 1 + write-only + + + P8 + Pull Up Disable. + 8 + 1 + write-only + + + P9 + Pull Up Disable. + 9 + 1 + write-only + + + P10 + Pull Up Disable. + 10 + 1 + write-only + + + P11 + Pull Up Disable. + 11 + 1 + write-only + + + P12 + Pull Up Disable. + 12 + 1 + write-only + + + P13 + Pull Up Disable. + 13 + 1 + write-only + + + P14 + Pull Up Disable. + 14 + 1 + write-only + + + P15 + Pull Up Disable. + 15 + 1 + write-only + + + P16 + Pull Up Disable. + 16 + 1 + write-only + + + P17 + Pull Up Disable. + 17 + 1 + write-only + + + P18 + Pull Up Disable. + 18 + 1 + write-only + + + P19 + Pull Up Disable. + 19 + 1 + write-only + + + P20 + Pull Up Disable. + 20 + 1 + write-only + + + P21 + Pull Up Disable. + 21 + 1 + write-only + + + P22 + Pull Up Disable. + 22 + 1 + write-only + + + P23 + Pull Up Disable. + 23 + 1 + write-only + + + P24 + Pull Up Disable. + 24 + 1 + write-only + + + P25 + Pull Up Disable. + 25 + 1 + write-only + + + P26 + Pull Up Disable. + 26 + 1 + write-only + + + P27 + Pull Up Disable. + 27 + 1 + write-only + + + P28 + Pull Up Disable. + 28 + 1 + write-only + + + P29 + Pull Up Disable. + 29 + 1 + write-only + + + P30 + Pull Up Disable. + 30 + 1 + write-only + + + P31 + Pull Up Disable. + 31 + 1 + write-only + + + + + PUER + Pull-up Enable Register + 0x00000064 + 32 + write-only + + + P0 + Pull Up Enable. + 0 + 1 + write-only + + + P1 + Pull Up Enable. + 1 + 1 + write-only + + + P2 + Pull Up Enable. + 2 + 1 + write-only + + + P3 + Pull Up Enable. + 3 + 1 + write-only + + + P4 + Pull Up Enable. + 4 + 1 + write-only + + + P5 + Pull Up Enable. + 5 + 1 + write-only + + + P6 + Pull Up Enable. + 6 + 1 + write-only + + + P7 + Pull Up Enable. + 7 + 1 + write-only + + + P8 + Pull Up Enable. + 8 + 1 + write-only + + + P9 + Pull Up Enable. + 9 + 1 + write-only + + + P10 + Pull Up Enable. + 10 + 1 + write-only + + + P11 + Pull Up Enable. + 11 + 1 + write-only + + + P12 + Pull Up Enable. + 12 + 1 + write-only + + + P13 + Pull Up Enable. + 13 + 1 + write-only + + + P14 + Pull Up Enable. + 14 + 1 + write-only + + + P15 + Pull Up Enable. + 15 + 1 + write-only + + + P16 + Pull Up Enable. + 16 + 1 + write-only + + + P17 + Pull Up Enable. + 17 + 1 + write-only + + + P18 + Pull Up Enable. + 18 + 1 + write-only + + + P19 + Pull Up Enable. + 19 + 1 + write-only + + + P20 + Pull Up Enable. + 20 + 1 + write-only + + + P21 + Pull Up Enable. + 21 + 1 + write-only + + + P22 + Pull Up Enable. + 22 + 1 + write-only + + + P23 + Pull Up Enable. + 23 + 1 + write-only + + + P24 + Pull Up Enable. + 24 + 1 + write-only + + + P25 + Pull Up Enable. + 25 + 1 + write-only + + + P26 + Pull Up Enable. + 26 + 1 + write-only + + + P27 + Pull Up Enable. + 27 + 1 + write-only + + + P28 + Pull Up Enable. + 28 + 1 + write-only + + + P29 + Pull Up Enable. + 29 + 1 + write-only + + + P30 + Pull Up Enable. + 30 + 1 + write-only + + + P31 + Pull Up Enable. + 31 + 1 + write-only + + + + + PUSR + Pad Pull-up Status Register + 0x00000068 + 32 + read-only + + + P0 + Pull Up Status. + 0 + 1 + read-only + + + P1 + Pull Up Status. + 1 + 1 + read-only + + + P2 + Pull Up Status. + 2 + 1 + read-only + + + P3 + Pull Up Status. + 3 + 1 + read-only + + + P4 + Pull Up Status. + 4 + 1 + read-only + + + P5 + Pull Up Status. + 5 + 1 + read-only + + + P6 + Pull Up Status. + 6 + 1 + read-only + + + P7 + Pull Up Status. + 7 + 1 + read-only + + + P8 + Pull Up Status. + 8 + 1 + read-only + + + P9 + Pull Up Status. + 9 + 1 + read-only + + + P10 + Pull Up Status. + 10 + 1 + read-only + + + P11 + Pull Up Status. + 11 + 1 + read-only + + + P12 + Pull Up Status. + 12 + 1 + read-only + + + P13 + Pull Up Status. + 13 + 1 + read-only + + + P14 + Pull Up Status. + 14 + 1 + read-only + + + P15 + Pull Up Status. + 15 + 1 + read-only + + + P16 + Pull Up Status. + 16 + 1 + read-only + + + P17 + Pull Up Status. + 17 + 1 + read-only + + + P18 + Pull Up Status. + 18 + 1 + read-only + + + P19 + Pull Up Status. + 19 + 1 + read-only + + + P20 + Pull Up Status. + 20 + 1 + read-only + + + P21 + Pull Up Status. + 21 + 1 + read-only + + + P22 + Pull Up Status. + 22 + 1 + read-only + + + P23 + Pull Up Status. + 23 + 1 + read-only + + + P24 + Pull Up Status. + 24 + 1 + read-only + + + P25 + Pull Up Status. + 25 + 1 + read-only + + + P26 + Pull Up Status. + 26 + 1 + read-only + + + P27 + Pull Up Status. + 27 + 1 + read-only + + + P28 + Pull Up Status. + 28 + 1 + read-only + + + P29 + Pull Up Status. + 29 + 1 + read-only + + + P30 + Pull Up Status. + 30 + 1 + read-only + + + P31 + Pull Up Status. + 31 + 1 + read-only + + + + + 2 + 4 + 0-1 + ABCDSR[%s] + Peripheral Select Register + 0x00000070 + 32 + read-write + + + P0 + Peripheral Select. + 0 + 1 + read-write + + + P1 + Peripheral Select. + 1 + 1 + read-write + + + P2 + Peripheral Select. + 2 + 1 + read-write + + + P3 + Peripheral Select. + 3 + 1 + read-write + + + P4 + Peripheral Select. + 4 + 1 + read-write + + + P5 + Peripheral Select. + 5 + 1 + read-write + + + P6 + Peripheral Select. + 6 + 1 + read-write + + + P7 + Peripheral Select. + 7 + 1 + read-write + + + P8 + Peripheral Select. + 8 + 1 + read-write + + + P9 + Peripheral Select. + 9 + 1 + read-write + + + P10 + Peripheral Select. + 10 + 1 + read-write + + + P11 + Peripheral Select. + 11 + 1 + read-write + + + P12 + Peripheral Select. + 12 + 1 + read-write + + + P13 + Peripheral Select. + 13 + 1 + read-write + + + P14 + Peripheral Select. + 14 + 1 + read-write + + + P15 + Peripheral Select. + 15 + 1 + read-write + + + P16 + Peripheral Select. + 16 + 1 + read-write + + + P17 + Peripheral Select. + 17 + 1 + read-write + + + P18 + Peripheral Select. + 18 + 1 + read-write + + + P19 + Peripheral Select. + 19 + 1 + read-write + + + P20 + Peripheral Select. + 20 + 1 + read-write + + + P21 + Peripheral Select. + 21 + 1 + read-write + + + P22 + Peripheral Select. + 22 + 1 + read-write + + + P23 + Peripheral Select. + 23 + 1 + read-write + + + P24 + Peripheral Select. + 24 + 1 + read-write + + + P25 + Peripheral Select. + 25 + 1 + read-write + + + P26 + Peripheral Select. + 26 + 1 + read-write + + + P27 + Peripheral Select. + 27 + 1 + read-write + + + P28 + Peripheral Select. + 28 + 1 + read-write + + + P29 + Peripheral Select. + 29 + 1 + read-write + + + P30 + Peripheral Select. + 30 + 1 + read-write + + + P31 + Peripheral Select. + 31 + 1 + read-write + + + + + IFSCDR + Input Filter Slow Clock Disable Register + 0x00000080 + 32 + write-only + + + P0 + PIO Clock Glitch Filtering Select. + 0 + 1 + write-only + + + P1 + PIO Clock Glitch Filtering Select. + 1 + 1 + write-only + + + P2 + PIO Clock Glitch Filtering Select. + 2 + 1 + write-only + + + P3 + PIO Clock Glitch Filtering Select. + 3 + 1 + write-only + + + P4 + PIO Clock Glitch Filtering Select. + 4 + 1 + write-only + + + P5 + PIO Clock Glitch Filtering Select. + 5 + 1 + write-only + + + P6 + PIO Clock Glitch Filtering Select. + 6 + 1 + write-only + + + P7 + PIO Clock Glitch Filtering Select. + 7 + 1 + write-only + + + P8 + PIO Clock Glitch Filtering Select. + 8 + 1 + write-only + + + P9 + PIO Clock Glitch Filtering Select. + 9 + 1 + write-only + + + P10 + PIO Clock Glitch Filtering Select. + 10 + 1 + write-only + + + P11 + PIO Clock Glitch Filtering Select. + 11 + 1 + write-only + + + P12 + PIO Clock Glitch Filtering Select. + 12 + 1 + write-only + + + P13 + PIO Clock Glitch Filtering Select. + 13 + 1 + write-only + + + P14 + PIO Clock Glitch Filtering Select. + 14 + 1 + write-only + + + P15 + PIO Clock Glitch Filtering Select. + 15 + 1 + write-only + + + P16 + PIO Clock Glitch Filtering Select. + 16 + 1 + write-only + + + P17 + PIO Clock Glitch Filtering Select. + 17 + 1 + write-only + + + P18 + PIO Clock Glitch Filtering Select. + 18 + 1 + write-only + + + P19 + PIO Clock Glitch Filtering Select. + 19 + 1 + write-only + + + P20 + PIO Clock Glitch Filtering Select. + 20 + 1 + write-only + + + P21 + PIO Clock Glitch Filtering Select. + 21 + 1 + write-only + + + P22 + PIO Clock Glitch Filtering Select. + 22 + 1 + write-only + + + P23 + PIO Clock Glitch Filtering Select. + 23 + 1 + write-only + + + P24 + PIO Clock Glitch Filtering Select. + 24 + 1 + write-only + + + P25 + PIO Clock Glitch Filtering Select. + 25 + 1 + write-only + + + P26 + PIO Clock Glitch Filtering Select. + 26 + 1 + write-only + + + P27 + PIO Clock Glitch Filtering Select. + 27 + 1 + write-only + + + P28 + PIO Clock Glitch Filtering Select. + 28 + 1 + write-only + + + P29 + PIO Clock Glitch Filtering Select. + 29 + 1 + write-only + + + P30 + PIO Clock Glitch Filtering Select. + 30 + 1 + write-only + + + P31 + PIO Clock Glitch Filtering Select. + 31 + 1 + write-only + + + + + IFSCER + Input Filter Slow Clock Enable Register + 0x00000084 + 32 + write-only + + + P0 + Debouncing Filtering Select. + 0 + 1 + write-only + + + P1 + Debouncing Filtering Select. + 1 + 1 + write-only + + + P2 + Debouncing Filtering Select. + 2 + 1 + write-only + + + P3 + Debouncing Filtering Select. + 3 + 1 + write-only + + + P4 + Debouncing Filtering Select. + 4 + 1 + write-only + + + P5 + Debouncing Filtering Select. + 5 + 1 + write-only + + + P6 + Debouncing Filtering Select. + 6 + 1 + write-only + + + P7 + Debouncing Filtering Select. + 7 + 1 + write-only + + + P8 + Debouncing Filtering Select. + 8 + 1 + write-only + + + P9 + Debouncing Filtering Select. + 9 + 1 + write-only + + + P10 + Debouncing Filtering Select. + 10 + 1 + write-only + + + P11 + Debouncing Filtering Select. + 11 + 1 + write-only + + + P12 + Debouncing Filtering Select. + 12 + 1 + write-only + + + P13 + Debouncing Filtering Select. + 13 + 1 + write-only + + + P14 + Debouncing Filtering Select. + 14 + 1 + write-only + + + P15 + Debouncing Filtering Select. + 15 + 1 + write-only + + + P16 + Debouncing Filtering Select. + 16 + 1 + write-only + + + P17 + Debouncing Filtering Select. + 17 + 1 + write-only + + + P18 + Debouncing Filtering Select. + 18 + 1 + write-only + + + P19 + Debouncing Filtering Select. + 19 + 1 + write-only + + + P20 + Debouncing Filtering Select. + 20 + 1 + write-only + + + P21 + Debouncing Filtering Select. + 21 + 1 + write-only + + + P22 + Debouncing Filtering Select. + 22 + 1 + write-only + + + P23 + Debouncing Filtering Select. + 23 + 1 + write-only + + + P24 + Debouncing Filtering Select. + 24 + 1 + write-only + + + P25 + Debouncing Filtering Select. + 25 + 1 + write-only + + + P26 + Debouncing Filtering Select. + 26 + 1 + write-only + + + P27 + Debouncing Filtering Select. + 27 + 1 + write-only + + + P28 + Debouncing Filtering Select. + 28 + 1 + write-only + + + P29 + Debouncing Filtering Select. + 29 + 1 + write-only + + + P30 + Debouncing Filtering Select. + 30 + 1 + write-only + + + P31 + Debouncing Filtering Select. + 31 + 1 + write-only + + + + + IFSCSR + Input Filter Slow Clock Status Register + 0x00000088 + 32 + read-only + 0x00000000 + + + P0 + Glitch or Debouncing Filter Selection Status + 0 + 1 + read-only + + + P1 + Glitch or Debouncing Filter Selection Status + 1 + 1 + read-only + + + P2 + Glitch or Debouncing Filter Selection Status + 2 + 1 + read-only + + + P3 + Glitch or Debouncing Filter Selection Status + 3 + 1 + read-only + + + P4 + Glitch or Debouncing Filter Selection Status + 4 + 1 + read-only + + + P5 + Glitch or Debouncing Filter Selection Status + 5 + 1 + read-only + + + P6 + Glitch or Debouncing Filter Selection Status + 6 + 1 + read-only + + + P7 + Glitch or Debouncing Filter Selection Status + 7 + 1 + read-only + + + P8 + Glitch or Debouncing Filter Selection Status + 8 + 1 + read-only + + + P9 + Glitch or Debouncing Filter Selection Status + 9 + 1 + read-only + + + P10 + Glitch or Debouncing Filter Selection Status + 10 + 1 + read-only + + + P11 + Glitch or Debouncing Filter Selection Status + 11 + 1 + read-only + + + P12 + Glitch or Debouncing Filter Selection Status + 12 + 1 + read-only + + + P13 + Glitch or Debouncing Filter Selection Status + 13 + 1 + read-only + + + P14 + Glitch or Debouncing Filter Selection Status + 14 + 1 + read-only + + + P15 + Glitch or Debouncing Filter Selection Status + 15 + 1 + read-only + + + P16 + Glitch or Debouncing Filter Selection Status + 16 + 1 + read-only + + + P17 + Glitch or Debouncing Filter Selection Status + 17 + 1 + read-only + + + P18 + Glitch or Debouncing Filter Selection Status + 18 + 1 + read-only + + + P19 + Glitch or Debouncing Filter Selection Status + 19 + 1 + read-only + + + P20 + Glitch or Debouncing Filter Selection Status + 20 + 1 + read-only + + + P21 + Glitch or Debouncing Filter Selection Status + 21 + 1 + read-only + + + P22 + Glitch or Debouncing Filter Selection Status + 22 + 1 + read-only + + + P23 + Glitch or Debouncing Filter Selection Status + 23 + 1 + read-only + + + P24 + Glitch or Debouncing Filter Selection Status + 24 + 1 + read-only + + + P25 + Glitch or Debouncing Filter Selection Status + 25 + 1 + read-only + + + P26 + Glitch or Debouncing Filter Selection Status + 26 + 1 + read-only + + + P27 + Glitch or Debouncing Filter Selection Status + 27 + 1 + read-only + + + P28 + Glitch or Debouncing Filter Selection Status + 28 + 1 + read-only + + + P29 + Glitch or Debouncing Filter Selection Status + 29 + 1 + read-only + + + P30 + Glitch or Debouncing Filter Selection Status + 30 + 1 + read-only + + + P31 + Glitch or Debouncing Filter Selection Status + 31 + 1 + read-only + + + + + SCDR + Slow Clock Divider Debouncing Register + 0x0000008C + 32 + read-write + 0x00000000 + + + DIV + 0 + 14 + read-write + + + + + PPDDR + Pad Pull-down Disable Register + 0x00000090 + 32 + write-only + + + P0 + Pull Down Disable. + 0 + 1 + write-only + + + P1 + Pull Down Disable. + 1 + 1 + write-only + + + P2 + Pull Down Disable. + 2 + 1 + write-only + + + P3 + Pull Down Disable. + 3 + 1 + write-only + + + P4 + Pull Down Disable. + 4 + 1 + write-only + + + P5 + Pull Down Disable. + 5 + 1 + write-only + + + P6 + Pull Down Disable. + 6 + 1 + write-only + + + P7 + Pull Down Disable. + 7 + 1 + write-only + + + P8 + Pull Down Disable. + 8 + 1 + write-only + + + P9 + Pull Down Disable. + 9 + 1 + write-only + + + P10 + Pull Down Disable. + 10 + 1 + write-only + + + P11 + Pull Down Disable. + 11 + 1 + write-only + + + P12 + Pull Down Disable. + 12 + 1 + write-only + + + P13 + Pull Down Disable. + 13 + 1 + write-only + + + P14 + Pull Down Disable. + 14 + 1 + write-only + + + P15 + Pull Down Disable. + 15 + 1 + write-only + + + P16 + Pull Down Disable. + 16 + 1 + write-only + + + P17 + Pull Down Disable. + 17 + 1 + write-only + + + P18 + Pull Down Disable. + 18 + 1 + write-only + + + P19 + Pull Down Disable. + 19 + 1 + write-only + + + P20 + Pull Down Disable. + 20 + 1 + write-only + + + P21 + Pull Down Disable. + 21 + 1 + write-only + + + P22 + Pull Down Disable. + 22 + 1 + write-only + + + P23 + Pull Down Disable. + 23 + 1 + write-only + + + P24 + Pull Down Disable. + 24 + 1 + write-only + + + P25 + Pull Down Disable. + 25 + 1 + write-only + + + P26 + Pull Down Disable. + 26 + 1 + write-only + + + P27 + Pull Down Disable. + 27 + 1 + write-only + + + P28 + Pull Down Disable. + 28 + 1 + write-only + + + P29 + Pull Down Disable. + 29 + 1 + write-only + + + P30 + Pull Down Disable. + 30 + 1 + write-only + + + P31 + Pull Down Disable. + 31 + 1 + write-only + + + + + PPDER + Pad Pull-down Enable Register + 0x00000094 + 32 + write-only + + + P0 + Pull Down Enable. + 0 + 1 + write-only + + + P1 + Pull Down Enable. + 1 + 1 + write-only + + + P2 + Pull Down Enable. + 2 + 1 + write-only + + + P3 + Pull Down Enable. + 3 + 1 + write-only + + + P4 + Pull Down Enable. + 4 + 1 + write-only + + + P5 + Pull Down Enable. + 5 + 1 + write-only + + + P6 + Pull Down Enable. + 6 + 1 + write-only + + + P7 + Pull Down Enable. + 7 + 1 + write-only + + + P8 + Pull Down Enable. + 8 + 1 + write-only + + + P9 + Pull Down Enable. + 9 + 1 + write-only + + + P10 + Pull Down Enable. + 10 + 1 + write-only + + + P11 + Pull Down Enable. + 11 + 1 + write-only + + + P12 + Pull Down Enable. + 12 + 1 + write-only + + + P13 + Pull Down Enable. + 13 + 1 + write-only + + + P14 + Pull Down Enable. + 14 + 1 + write-only + + + P15 + Pull Down Enable. + 15 + 1 + write-only + + + P16 + Pull Down Enable. + 16 + 1 + write-only + + + P17 + Pull Down Enable. + 17 + 1 + write-only + + + P18 + Pull Down Enable. + 18 + 1 + write-only + + + P19 + Pull Down Enable. + 19 + 1 + write-only + + + P20 + Pull Down Enable. + 20 + 1 + write-only + + + P21 + Pull Down Enable. + 21 + 1 + write-only + + + P22 + Pull Down Enable. + 22 + 1 + write-only + + + P23 + Pull Down Enable. + 23 + 1 + write-only + + + P24 + Pull Down Enable. + 24 + 1 + write-only + + + P25 + Pull Down Enable. + 25 + 1 + write-only + + + P26 + Pull Down Enable. + 26 + 1 + write-only + + + P27 + Pull Down Enable. + 27 + 1 + write-only + + + P28 + Pull Down Enable. + 28 + 1 + write-only + + + P29 + Pull Down Enable. + 29 + 1 + write-only + + + P30 + Pull Down Enable. + 30 + 1 + write-only + + + P31 + Pull Down Enable. + 31 + 1 + write-only + + + + + PPDSR + Pad Pull-down Status Register + 0x00000098 + 32 + read-only + + + P0 + Pull Down Status. + 0 + 1 + read-only + + + P1 + Pull Down Status. + 1 + 1 + read-only + + + P2 + Pull Down Status. + 2 + 1 + read-only + + + P3 + Pull Down Status. + 3 + 1 + read-only + + + P4 + Pull Down Status. + 4 + 1 + read-only + + + P5 + Pull Down Status. + 5 + 1 + read-only + + + P6 + Pull Down Status. + 6 + 1 + read-only + + + P7 + Pull Down Status. + 7 + 1 + read-only + + + P8 + Pull Down Status. + 8 + 1 + read-only + + + P9 + Pull Down Status. + 9 + 1 + read-only + + + P10 + Pull Down Status. + 10 + 1 + read-only + + + P11 + Pull Down Status. + 11 + 1 + read-only + + + P12 + Pull Down Status. + 12 + 1 + read-only + + + P13 + Pull Down Status. + 13 + 1 + read-only + + + P14 + Pull Down Status. + 14 + 1 + read-only + + + P15 + Pull Down Status. + 15 + 1 + read-only + + + P16 + Pull Down Status. + 16 + 1 + read-only + + + P17 + Pull Down Status. + 17 + 1 + read-only + + + P18 + Pull Down Status. + 18 + 1 + read-only + + + P19 + Pull Down Status. + 19 + 1 + read-only + + + P20 + Pull Down Status. + 20 + 1 + read-only + + + P21 + Pull Down Status. + 21 + 1 + read-only + + + P22 + Pull Down Status. + 22 + 1 + read-only + + + P23 + Pull Down Status. + 23 + 1 + read-only + + + P24 + Pull Down Status. + 24 + 1 + read-only + + + P25 + Pull Down Status. + 25 + 1 + read-only + + + P26 + Pull Down Status. + 26 + 1 + read-only + + + P27 + Pull Down Status. + 27 + 1 + read-only + + + P28 + Pull Down Status. + 28 + 1 + read-only + + + P29 + Pull Down Status. + 29 + 1 + read-only + + + P30 + Pull Down Status. + 30 + 1 + read-only + + + P31 + Pull Down Status. + 31 + 1 + read-only + + + + + OWER + Output Write Enable + 0x000000A0 + 32 + write-only + + + P0 + Output Write Enable. + 0 + 1 + write-only + + + P1 + Output Write Enable. + 1 + 1 + write-only + + + P2 + Output Write Enable. + 2 + 1 + write-only + + + P3 + Output Write Enable. + 3 + 1 + write-only + + + P4 + Output Write Enable. + 4 + 1 + write-only + + + P5 + Output Write Enable. + 5 + 1 + write-only + + + P6 + Output Write Enable. + 6 + 1 + write-only + + + P7 + Output Write Enable. + 7 + 1 + write-only + + + P8 + Output Write Enable. + 8 + 1 + write-only + + + P9 + Output Write Enable. + 9 + 1 + write-only + + + P10 + Output Write Enable. + 10 + 1 + write-only + + + P11 + Output Write Enable. + 11 + 1 + write-only + + + P12 + Output Write Enable. + 12 + 1 + write-only + + + P13 + Output Write Enable. + 13 + 1 + write-only + + + P14 + Output Write Enable. + 14 + 1 + write-only + + + P15 + Output Write Enable. + 15 + 1 + write-only + + + P16 + Output Write Enable. + 16 + 1 + write-only + + + P17 + Output Write Enable. + 17 + 1 + write-only + + + P18 + Output Write Enable. + 18 + 1 + write-only + + + P19 + Output Write Enable. + 19 + 1 + write-only + + + P20 + Output Write Enable. + 20 + 1 + write-only + + + P21 + Output Write Enable. + 21 + 1 + write-only + + + P22 + Output Write Enable. + 22 + 1 + write-only + + + P23 + Output Write Enable. + 23 + 1 + write-only + + + P24 + Output Write Enable. + 24 + 1 + write-only + + + P25 + Output Write Enable. + 25 + 1 + write-only + + + P26 + Output Write Enable. + 26 + 1 + write-only + + + P27 + Output Write Enable. + 27 + 1 + write-only + + + P28 + Output Write Enable. + 28 + 1 + write-only + + + P29 + Output Write Enable. + 29 + 1 + write-only + + + P30 + Output Write Enable. + 30 + 1 + write-only + + + P31 + Output Write Enable. + 31 + 1 + write-only + + + + + OWDR + Output Write Disable + 0x000000A4 + 32 + write-only + + + P0 + Output Write Disable. + 0 + 1 + write-only + + + P1 + Output Write Disable. + 1 + 1 + write-only + + + P2 + Output Write Disable. + 2 + 1 + write-only + + + P3 + Output Write Disable. + 3 + 1 + write-only + + + P4 + Output Write Disable. + 4 + 1 + write-only + + + P5 + Output Write Disable. + 5 + 1 + write-only + + + P6 + Output Write Disable. + 6 + 1 + write-only + + + P7 + Output Write Disable. + 7 + 1 + write-only + + + P8 + Output Write Disable. + 8 + 1 + write-only + + + P9 + Output Write Disable. + 9 + 1 + write-only + + + P10 + Output Write Disable. + 10 + 1 + write-only + + + P11 + Output Write Disable. + 11 + 1 + write-only + + + P12 + Output Write Disable. + 12 + 1 + write-only + + + P13 + Output Write Disable. + 13 + 1 + write-only + + + P14 + Output Write Disable. + 14 + 1 + write-only + + + P15 + Output Write Disable. + 15 + 1 + write-only + + + P16 + Output Write Disable. + 16 + 1 + write-only + + + P17 + Output Write Disable. + 17 + 1 + write-only + + + P18 + Output Write Disable. + 18 + 1 + write-only + + + P19 + Output Write Disable. + 19 + 1 + write-only + + + P20 + Output Write Disable. + 20 + 1 + write-only + + + P21 + Output Write Disable. + 21 + 1 + write-only + + + P22 + Output Write Disable. + 22 + 1 + write-only + + + P23 + Output Write Disable. + 23 + 1 + write-only + + + P24 + Output Write Disable. + 24 + 1 + write-only + + + P25 + Output Write Disable. + 25 + 1 + write-only + + + P26 + Output Write Disable. + 26 + 1 + write-only + + + P27 + Output Write Disable. + 27 + 1 + write-only + + + P28 + Output Write Disable. + 28 + 1 + write-only + + + P29 + Output Write Disable. + 29 + 1 + write-only + + + P30 + Output Write Disable. + 30 + 1 + write-only + + + P31 + Output Write Disable. + 31 + 1 + write-only + + + + + OWSR + Output Write Status Register + 0x000000A8 + 32 + read-only + 0x00000000 + + + P0 + Output Write Status. + 0 + 1 + read-only + + + P1 + Output Write Status. + 1 + 1 + read-only + + + P2 + Output Write Status. + 2 + 1 + read-only + + + P3 + Output Write Status. + 3 + 1 + read-only + + + P4 + Output Write Status. + 4 + 1 + read-only + + + P5 + Output Write Status. + 5 + 1 + read-only + + + P6 + Output Write Status. + 6 + 1 + read-only + + + P7 + Output Write Status. + 7 + 1 + read-only + + + P8 + Output Write Status. + 8 + 1 + read-only + + + P9 + Output Write Status. + 9 + 1 + read-only + + + P10 + Output Write Status. + 10 + 1 + read-only + + + P11 + Output Write Status. + 11 + 1 + read-only + + + P12 + Output Write Status. + 12 + 1 + read-only + + + P13 + Output Write Status. + 13 + 1 + read-only + + + P14 + Output Write Status. + 14 + 1 + read-only + + + P15 + Output Write Status. + 15 + 1 + read-only + + + P16 + Output Write Status. + 16 + 1 + read-only + + + P17 + Output Write Status. + 17 + 1 + read-only + + + P18 + Output Write Status. + 18 + 1 + read-only + + + P19 + Output Write Status. + 19 + 1 + read-only + + + P20 + Output Write Status. + 20 + 1 + read-only + + + P21 + Output Write Status. + 21 + 1 + read-only + + + P22 + Output Write Status. + 22 + 1 + read-only + + + P23 + Output Write Status. + 23 + 1 + read-only + + + P24 + Output Write Status. + 24 + 1 + read-only + + + P25 + Output Write Status. + 25 + 1 + read-only + + + P26 + Output Write Status. + 26 + 1 + read-only + + + P27 + Output Write Status. + 27 + 1 + read-only + + + P28 + Output Write Status. + 28 + 1 + read-only + + + P29 + Output Write Status. + 29 + 1 + read-only + + + P30 + Output Write Status. + 30 + 1 + read-only + + + P31 + Output Write Status. + 31 + 1 + read-only + + + + + AIMER + Additional Interrupt Modes Enable Register + 0x000000B0 + 32 + write-only + + + P0 + Additional Interrupt Modes Enable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Enable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Enable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Enable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Enable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Enable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Enable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Enable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Enable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Enable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Enable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Enable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Enable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Enable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Enable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Enable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Enable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Enable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Enable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Enable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Enable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Enable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Enable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Enable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Enable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Enable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Enable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Enable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Enable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Enable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Enable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Enable. + 31 + 1 + write-only + + + + + AIMDR + Additional Interrupt Modes Disables Register + 0x000000B4 + 32 + write-only + + + P0 + Additional Interrupt Modes Disable. + 0 + 1 + write-only + + + P1 + Additional Interrupt Modes Disable. + 1 + 1 + write-only + + + P2 + Additional Interrupt Modes Disable. + 2 + 1 + write-only + + + P3 + Additional Interrupt Modes Disable. + 3 + 1 + write-only + + + P4 + Additional Interrupt Modes Disable. + 4 + 1 + write-only + + + P5 + Additional Interrupt Modes Disable. + 5 + 1 + write-only + + + P6 + Additional Interrupt Modes Disable. + 6 + 1 + write-only + + + P7 + Additional Interrupt Modes Disable. + 7 + 1 + write-only + + + P8 + Additional Interrupt Modes Disable. + 8 + 1 + write-only + + + P9 + Additional Interrupt Modes Disable. + 9 + 1 + write-only + + + P10 + Additional Interrupt Modes Disable. + 10 + 1 + write-only + + + P11 + Additional Interrupt Modes Disable. + 11 + 1 + write-only + + + P12 + Additional Interrupt Modes Disable. + 12 + 1 + write-only + + + P13 + Additional Interrupt Modes Disable. + 13 + 1 + write-only + + + P14 + Additional Interrupt Modes Disable. + 14 + 1 + write-only + + + P15 + Additional Interrupt Modes Disable. + 15 + 1 + write-only + + + P16 + Additional Interrupt Modes Disable. + 16 + 1 + write-only + + + P17 + Additional Interrupt Modes Disable. + 17 + 1 + write-only + + + P18 + Additional Interrupt Modes Disable. + 18 + 1 + write-only + + + P19 + Additional Interrupt Modes Disable. + 19 + 1 + write-only + + + P20 + Additional Interrupt Modes Disable. + 20 + 1 + write-only + + + P21 + Additional Interrupt Modes Disable. + 21 + 1 + write-only + + + P22 + Additional Interrupt Modes Disable. + 22 + 1 + write-only + + + P23 + Additional Interrupt Modes Disable. + 23 + 1 + write-only + + + P24 + Additional Interrupt Modes Disable. + 24 + 1 + write-only + + + P25 + Additional Interrupt Modes Disable. + 25 + 1 + write-only + + + P26 + Additional Interrupt Modes Disable. + 26 + 1 + write-only + + + P27 + Additional Interrupt Modes Disable. + 27 + 1 + write-only + + + P28 + Additional Interrupt Modes Disable. + 28 + 1 + write-only + + + P29 + Additional Interrupt Modes Disable. + 29 + 1 + write-only + + + P30 + Additional Interrupt Modes Disable. + 30 + 1 + write-only + + + P31 + Additional Interrupt Modes Disable. + 31 + 1 + write-only + + + + + AIMMR + Additional Interrupt Modes Mask Register + 0x000000B8 + 32 + read-only + 0x00000000 + + + P0 + Peripheral CD Status. + 0 + 1 + read-only + + + P1 + Peripheral CD Status. + 1 + 1 + read-only + + + P2 + Peripheral CD Status. + 2 + 1 + read-only + + + P3 + Peripheral CD Status. + 3 + 1 + read-only + + + P4 + Peripheral CD Status. + 4 + 1 + read-only + + + P5 + Peripheral CD Status. + 5 + 1 + read-only + + + P6 + Peripheral CD Status. + 6 + 1 + read-only + + + P7 + Peripheral CD Status. + 7 + 1 + read-only + + + P8 + Peripheral CD Status. + 8 + 1 + read-only + + + P9 + Peripheral CD Status. + 9 + 1 + read-only + + + P10 + Peripheral CD Status. + 10 + 1 + read-only + + + P11 + Peripheral CD Status. + 11 + 1 + read-only + + + P12 + Peripheral CD Status. + 12 + 1 + read-only + + + P13 + Peripheral CD Status. + 13 + 1 + read-only + + + P14 + Peripheral CD Status. + 14 + 1 + read-only + + + P15 + Peripheral CD Status. + 15 + 1 + read-only + + + P16 + Peripheral CD Status. + 16 + 1 + read-only + + + P17 + Peripheral CD Status. + 17 + 1 + read-only + + + P18 + Peripheral CD Status. + 18 + 1 + read-only + + + P19 + Peripheral CD Status. + 19 + 1 + read-only + + + P20 + Peripheral CD Status. + 20 + 1 + read-only + + + P21 + Peripheral CD Status. + 21 + 1 + read-only + + + P22 + Peripheral CD Status. + 22 + 1 + read-only + + + P23 + Peripheral CD Status. + 23 + 1 + read-only + + + P24 + Peripheral CD Status. + 24 + 1 + read-only + + + P25 + Peripheral CD Status. + 25 + 1 + read-only + + + P26 + Peripheral CD Status. + 26 + 1 + read-only + + + P27 + Peripheral CD Status. + 27 + 1 + read-only + + + P28 + Peripheral CD Status. + 28 + 1 + read-only + + + P29 + Peripheral CD Status. + 29 + 1 + read-only + + + P30 + Peripheral CD Status. + 30 + 1 + read-only + + + P31 + Peripheral CD Status. + 31 + 1 + read-only + + + + + ESR + Edge Select Register + 0x000000C0 + 32 + write-only + + + P0 + Edge Interrupt Selection. + 0 + 1 + write-only + + + P1 + Edge Interrupt Selection. + 1 + 1 + write-only + + + P2 + Edge Interrupt Selection. + 2 + 1 + write-only + + + P3 + Edge Interrupt Selection. + 3 + 1 + write-only + + + P4 + Edge Interrupt Selection. + 4 + 1 + write-only + + + P5 + Edge Interrupt Selection. + 5 + 1 + write-only + + + P6 + Edge Interrupt Selection. + 6 + 1 + write-only + + + P7 + Edge Interrupt Selection. + 7 + 1 + write-only + + + P8 + Edge Interrupt Selection. + 8 + 1 + write-only + + + P9 + Edge Interrupt Selection. + 9 + 1 + write-only + + + P10 + Edge Interrupt Selection. + 10 + 1 + write-only + + + P11 + Edge Interrupt Selection. + 11 + 1 + write-only + + + P12 + Edge Interrupt Selection. + 12 + 1 + write-only + + + P13 + Edge Interrupt Selection. + 13 + 1 + write-only + + + P14 + Edge Interrupt Selection. + 14 + 1 + write-only + + + P15 + Edge Interrupt Selection. + 15 + 1 + write-only + + + P16 + Edge Interrupt Selection. + 16 + 1 + write-only + + + P17 + Edge Interrupt Selection. + 17 + 1 + write-only + + + P18 + Edge Interrupt Selection. + 18 + 1 + write-only + + + P19 + Edge Interrupt Selection. + 19 + 1 + write-only + + + P20 + Edge Interrupt Selection. + 20 + 1 + write-only + + + P21 + Edge Interrupt Selection. + 21 + 1 + write-only + + + P22 + Edge Interrupt Selection. + 22 + 1 + write-only + + + P23 + Edge Interrupt Selection. + 23 + 1 + write-only + + + P24 + Edge Interrupt Selection. + 24 + 1 + write-only + + + P25 + Edge Interrupt Selection. + 25 + 1 + write-only + + + P26 + Edge Interrupt Selection. + 26 + 1 + write-only + + + P27 + Edge Interrupt Selection. + 27 + 1 + write-only + + + P28 + Edge Interrupt Selection. + 28 + 1 + write-only + + + P29 + Edge Interrupt Selection. + 29 + 1 + write-only + + + P30 + Edge Interrupt Selection. + 30 + 1 + write-only + + + P31 + Edge Interrupt Selection. + 31 + 1 + write-only + + + + + LSR + Level Select Register + 0x000000C4 + 32 + write-only + + + P0 + Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Level Interrupt Selection. + 31 + 1 + write-only + + + + + ELSR + Edge/Level Status Register + 0x000000C8 + 32 + read-only + 0x00000000 + + + P0 + Edge/Level Interrupt source selection. + 0 + 1 + read-only + + + P1 + Edge/Level Interrupt source selection. + 1 + 1 + read-only + + + P2 + Edge/Level Interrupt source selection. + 2 + 1 + read-only + + + P3 + Edge/Level Interrupt source selection. + 3 + 1 + read-only + + + P4 + Edge/Level Interrupt source selection. + 4 + 1 + read-only + + + P5 + Edge/Level Interrupt source selection. + 5 + 1 + read-only + + + P6 + Edge/Level Interrupt source selection. + 6 + 1 + read-only + + + P7 + Edge/Level Interrupt source selection. + 7 + 1 + read-only + + + P8 + Edge/Level Interrupt source selection. + 8 + 1 + read-only + + + P9 + Edge/Level Interrupt source selection. + 9 + 1 + read-only + + + P10 + Edge/Level Interrupt source selection. + 10 + 1 + read-only + + + P11 + Edge/Level Interrupt source selection. + 11 + 1 + read-only + + + P12 + Edge/Level Interrupt source selection. + 12 + 1 + read-only + + + P13 + Edge/Level Interrupt source selection. + 13 + 1 + read-only + + + P14 + Edge/Level Interrupt source selection. + 14 + 1 + read-only + + + P15 + Edge/Level Interrupt source selection. + 15 + 1 + read-only + + + P16 + Edge/Level Interrupt source selection. + 16 + 1 + read-only + + + P17 + Edge/Level Interrupt source selection. + 17 + 1 + read-only + + + P18 + Edge/Level Interrupt source selection. + 18 + 1 + read-only + + + P19 + Edge/Level Interrupt source selection. + 19 + 1 + read-only + + + P20 + Edge/Level Interrupt source selection. + 20 + 1 + read-only + + + P21 + Edge/Level Interrupt source selection. + 21 + 1 + read-only + + + P22 + Edge/Level Interrupt source selection. + 22 + 1 + read-only + + + P23 + Edge/Level Interrupt source selection. + 23 + 1 + read-only + + + P24 + Edge/Level Interrupt source selection. + 24 + 1 + read-only + + + P25 + Edge/Level Interrupt source selection. + 25 + 1 + read-only + + + P26 + Edge/Level Interrupt source selection. + 26 + 1 + read-only + + + P27 + Edge/Level Interrupt source selection. + 27 + 1 + read-only + + + P28 + Edge/Level Interrupt source selection. + 28 + 1 + read-only + + + P29 + Edge/Level Interrupt source selection. + 29 + 1 + read-only + + + P30 + Edge/Level Interrupt source selection. + 30 + 1 + read-only + + + P31 + Edge/Level Interrupt source selection. + 31 + 1 + read-only + + + + + FELLSR + Falling Edge/Low Level Select Register + 0x000000D0 + 32 + write-only + + + P0 + Falling Edge/Low Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Falling Edge/Low Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Falling Edge/Low Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Falling Edge/Low Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Falling Edge/Low Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Falling Edge/Low Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Falling Edge/Low Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Falling Edge/Low Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Falling Edge/Low Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Falling Edge/Low Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Falling Edge/Low Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Falling Edge/Low Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Falling Edge/Low Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Falling Edge/Low Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Falling Edge/Low Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Falling Edge/Low Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Falling Edge/Low Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Falling Edge/Low Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Falling Edge/Low Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Falling Edge/Low Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Falling Edge/Low Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Falling Edge/Low Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Falling Edge/Low Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Falling Edge/Low Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Falling Edge/Low Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Falling Edge/Low Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Falling Edge/Low Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Falling Edge/Low Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Falling Edge/Low Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Falling Edge/Low Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Falling Edge/Low Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Falling Edge/Low Level Interrupt Selection. + 31 + 1 + write-only + + + + + REHLSR + Rising Edge/ High Level Select Register + 0x000000D4 + 32 + write-only + + + P0 + Rising Edge /High Level Interrupt Selection. + 0 + 1 + write-only + + + P1 + Rising Edge /High Level Interrupt Selection. + 1 + 1 + write-only + + + P2 + Rising Edge /High Level Interrupt Selection. + 2 + 1 + write-only + + + P3 + Rising Edge /High Level Interrupt Selection. + 3 + 1 + write-only + + + P4 + Rising Edge /High Level Interrupt Selection. + 4 + 1 + write-only + + + P5 + Rising Edge /High Level Interrupt Selection. + 5 + 1 + write-only + + + P6 + Rising Edge /High Level Interrupt Selection. + 6 + 1 + write-only + + + P7 + Rising Edge /High Level Interrupt Selection. + 7 + 1 + write-only + + + P8 + Rising Edge /High Level Interrupt Selection. + 8 + 1 + write-only + + + P9 + Rising Edge /High Level Interrupt Selection. + 9 + 1 + write-only + + + P10 + Rising Edge /High Level Interrupt Selection. + 10 + 1 + write-only + + + P11 + Rising Edge /High Level Interrupt Selection. + 11 + 1 + write-only + + + P12 + Rising Edge /High Level Interrupt Selection. + 12 + 1 + write-only + + + P13 + Rising Edge /High Level Interrupt Selection. + 13 + 1 + write-only + + + P14 + Rising Edge /High Level Interrupt Selection. + 14 + 1 + write-only + + + P15 + Rising Edge /High Level Interrupt Selection. + 15 + 1 + write-only + + + P16 + Rising Edge /High Level Interrupt Selection. + 16 + 1 + write-only + + + P17 + Rising Edge /High Level Interrupt Selection. + 17 + 1 + write-only + + + P18 + Rising Edge /High Level Interrupt Selection. + 18 + 1 + write-only + + + P19 + Rising Edge /High Level Interrupt Selection. + 19 + 1 + write-only + + + P20 + Rising Edge /High Level Interrupt Selection. + 20 + 1 + write-only + + + P21 + Rising Edge /High Level Interrupt Selection. + 21 + 1 + write-only + + + P22 + Rising Edge /High Level Interrupt Selection. + 22 + 1 + write-only + + + P23 + Rising Edge /High Level Interrupt Selection. + 23 + 1 + write-only + + + P24 + Rising Edge /High Level Interrupt Selection. + 24 + 1 + write-only + + + P25 + Rising Edge /High Level Interrupt Selection. + 25 + 1 + write-only + + + P26 + Rising Edge /High Level Interrupt Selection. + 26 + 1 + write-only + + + P27 + Rising Edge /High Level Interrupt Selection. + 27 + 1 + write-only + + + P28 + Rising Edge /High Level Interrupt Selection. + 28 + 1 + write-only + + + P29 + Rising Edge /High Level Interrupt Selection. + 29 + 1 + write-only + + + P30 + Rising Edge /High Level Interrupt Selection. + 30 + 1 + write-only + + + P31 + Rising Edge /High Level Interrupt Selection. + 31 + 1 + write-only + + + + + FRLHSR + Fall/Rise - Low/High Status Register + 0x000000D8 + 32 + read-only + 0x00000000 + + + P0 + Edge /Level Interrupt Source Selection. + 0 + 1 + read-only + + + P1 + Edge /Level Interrupt Source Selection. + 1 + 1 + read-only + + + P2 + Edge /Level Interrupt Source Selection. + 2 + 1 + read-only + + + P3 + Edge /Level Interrupt Source Selection. + 3 + 1 + read-only + + + P4 + Edge /Level Interrupt Source Selection. + 4 + 1 + read-only + + + P5 + Edge /Level Interrupt Source Selection. + 5 + 1 + read-only + + + P6 + Edge /Level Interrupt Source Selection. + 6 + 1 + read-only + + + P7 + Edge /Level Interrupt Source Selection. + 7 + 1 + read-only + + + P8 + Edge /Level Interrupt Source Selection. + 8 + 1 + read-only + + + P9 + Edge /Level Interrupt Source Selection. + 9 + 1 + read-only + + + P10 + Edge /Level Interrupt Source Selection. + 10 + 1 + read-only + + + P11 + Edge /Level Interrupt Source Selection. + 11 + 1 + read-only + + + P12 + Edge /Level Interrupt Source Selection. + 12 + 1 + read-only + + + P13 + Edge /Level Interrupt Source Selection. + 13 + 1 + read-only + + + P14 + Edge /Level Interrupt Source Selection. + 14 + 1 + read-only + + + P15 + Edge /Level Interrupt Source Selection. + 15 + 1 + read-only + + + P16 + Edge /Level Interrupt Source Selection. + 16 + 1 + read-only + + + P17 + Edge /Level Interrupt Source Selection. + 17 + 1 + read-only + + + P18 + Edge /Level Interrupt Source Selection. + 18 + 1 + read-only + + + P19 + Edge /Level Interrupt Source Selection. + 19 + 1 + read-only + + + P20 + Edge /Level Interrupt Source Selection. + 20 + 1 + read-only + + + P21 + Edge /Level Interrupt Source Selection. + 21 + 1 + read-only + + + P22 + Edge /Level Interrupt Source Selection. + 22 + 1 + read-only + + + P23 + Edge /Level Interrupt Source Selection. + 23 + 1 + read-only + + + P24 + Edge /Level Interrupt Source Selection. + 24 + 1 + read-only + + + P25 + Edge /Level Interrupt Source Selection. + 25 + 1 + read-only + + + P26 + Edge /Level Interrupt Source Selection. + 26 + 1 + read-only + + + P27 + Edge /Level Interrupt Source Selection. + 27 + 1 + read-only + + + P28 + Edge /Level Interrupt Source Selection. + 28 + 1 + read-only + + + P29 + Edge /Level Interrupt Source Selection. + 29 + 1 + read-only + + + P30 + Edge /Level Interrupt Source Selection. + 30 + 1 + read-only + + + P31 + Edge /Level Interrupt Source Selection. + 31 + 1 + read-only + + + + + LOCKSR + Lock Status + 0x000000E0 + 32 + read-only + 0x00000000 + + + P0 + Lock Status. + 0 + 1 + read-only + + + P1 + Lock Status. + 1 + 1 + read-only + + + P2 + Lock Status. + 2 + 1 + read-only + + + P3 + Lock Status. + 3 + 1 + read-only + + + P4 + Lock Status. + 4 + 1 + read-only + + + P5 + Lock Status. + 5 + 1 + read-only + + + P6 + Lock Status. + 6 + 1 + read-only + + + P7 + Lock Status. + 7 + 1 + read-only + + + P8 + Lock Status. + 8 + 1 + read-only + + + P9 + Lock Status. + 9 + 1 + read-only + + + P10 + Lock Status. + 10 + 1 + read-only + + + P11 + Lock Status. + 11 + 1 + read-only + + + P12 + Lock Status. + 12 + 1 + read-only + + + P13 + Lock Status. + 13 + 1 + read-only + + + P14 + Lock Status. + 14 + 1 + read-only + + + P15 + Lock Status. + 15 + 1 + read-only + + + P16 + Lock Status. + 16 + 1 + read-only + + + P17 + Lock Status. + 17 + 1 + read-only + + + P18 + Lock Status. + 18 + 1 + read-only + + + P19 + Lock Status. + 19 + 1 + read-only + + + P20 + Lock Status. + 20 + 1 + read-only + + + P21 + Lock Status. + 21 + 1 + read-only + + + P22 + Lock Status. + 22 + 1 + read-only + + + P23 + Lock Status. + 23 + 1 + read-only + + + P24 + Lock Status. + 24 + 1 + read-only + + + P25 + Lock Status. + 25 + 1 + read-only + + + P26 + Lock Status. + 26 + 1 + read-only + + + P27 + Lock Status. + 27 + 1 + read-only + + + P28 + Lock Status. + 28 + 1 + read-only + + + P29 + Lock Status. + 29 + 1 + read-only + + + P30 + Lock Status. + 30 + 1 + read-only + + + P31 + Lock Status. + 31 + 1 + read-only + + + + + WPMR + Write Protect Mode Register + 0x000000E4 + 32 + read-write + 0x00000000 + + + WPEN + Write Protect Enable + 0 + 1 + read-write + + + WPKEY + Write Protect KEY + 8 + 24 + read-write + + + + + WPSR + Write Protect Status Register + 0x000000E8 + 32 + read-only + 0x00000000 + + + WPVS + Write Protect Violation Status + 0 + 1 + read-only + + + WPVSRC + Write Protect Violation Source + 8 + 16 + read-only + + + + + SCHMITT + Schmitt Trigger Register + 0x00000100 + 32 + read-write + 0x00000000 + + + SCHMITT0 + 0 + 1 + read-write + + + SCHMITT1 + 1 + 1 + read-write + + + SCHMITT2 + 2 + 1 + read-write + + + SCHMITT3 + 3 + 1 + read-write + + + SCHMITT4 + 4 + 1 + read-write + + + SCHMITT5 + 5 + 1 + read-write + + + SCHMITT6 + 6 + 1 + read-write + + + SCHMITT7 + 7 + 1 + read-write + + + SCHMITT8 + 8 + 1 + read-write + + + SCHMITT9 + 9 + 1 + read-write + + + SCHMITT10 + 10 + 1 + read-write + + + SCHMITT11 + 11 + 1 + read-write + + + SCHMITT12 + 12 + 1 + read-write + + + SCHMITT13 + 13 + 1 + read-write + + + SCHMITT14 + 14 + 1 + read-write + + + SCHMITT15 + 15 + 1 + read-write + + + SCHMITT16 + 16 + 1 + read-write + + + SCHMITT17 + 17 + 1 + read-write + + + SCHMITT18 + 18 + 1 + read-write + + + SCHMITT19 + 19 + 1 + read-write + + + SCHMITT20 + 20 + 1 + read-write + + + SCHMITT21 + 21 + 1 + read-write + + + SCHMITT22 + 22 + 1 + read-write + + + SCHMITT23 + 23 + 1 + read-write + + + SCHMITT24 + 24 + 1 + read-write + + + SCHMITT25 + 25 + 1 + read-write + + + SCHMITT26 + 26 + 1 + read-write + + + SCHMITT27 + 27 + 1 + read-write + + + SCHMITT28 + 28 + 1 + read-write + + + SCHMITT29 + 29 + 1 + read-write + + + SCHMITT30 + 30 + 1 + read-write + + + SCHMITT31 + 31 + 1 + read-write + + + + + PCMR + Parallel Capture Mode Register + 0x00000150 + 32 + read-write + 0x00000000 + + + PCEN + Parallel Capture Mode Enable + 0 + 1 + read-write + + + DSIZE + Parallel Capture Mode Data Size + 4 + 2 + read-write + + + BYTE + The reception data in the PIO_PCRHR register is a BYTE (8-bit) + 0x0 + + + HALFWORD + The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit) + 0x1 + + + WORD + The reception data in the PIO_PCRHR register is a WORD (32-bit) + 0x2 + + + + + ALWYS + Parallel Capture Mode Always Sampling + 9 + 1 + read-write + + + HALFS + Parallel Capture Mode Half Sampling + 10 + 1 + read-write + + + FRSTS + Parallel Capture Mode First Sample + 11 + 1 + read-write + + + + + PCIER + Parallel Capture Interrupt Enable Register + 0x00000154 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Enable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Enable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Enable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Enable + 3 + 1 + write-only + + + + + PCIDR + Parallel Capture Interrupt Disable Register + 0x00000158 + 32 + write-only + + + DRDY + Parallel Capture Mode Data Ready Interrupt Disable + 0 + 1 + write-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Disable + 1 + 1 + write-only + + + ENDRX + End of Reception Transfer Interrupt Disable + 2 + 1 + write-only + + + RXBUFF + Reception Buffer Full Interrupt Disable + 3 + 1 + write-only + + + + + PCIMR + Parallel Capture Interrupt Mask Register + 0x0000015C + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready Interrupt Mask + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error Interrupt Mask + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer Interrupt Mask + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full Interrupt Mask + 3 + 1 + read-only + + + + + PCISR + Parallel Capture Interrupt Status Register + 0x00000160 + 32 + read-only + 0x00000000 + + + DRDY + Parallel Capture Mode Data Ready + 0 + 1 + read-only + + + OVRE + Parallel Capture Mode Overrun Error. + 1 + 1 + read-only + + + ENDRX + End of Reception Transfer. + 2 + 1 + read-only + + + RXBUFF + Reception Buffer Full + 3 + 1 + read-only + + + + + PCRHR + Parallel Capture Reception Holding Register + 0x00000164 + 32 + read-only + 0x00000000 + + + RDATA + Parallel Capture Mode Reception Data. + 0 + 32 + read-only + + + + + + + RSTC + 11009C + Reset Controller + SYSC + RSTC_ + 0x400E1400 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + PROCRST + Processor Reset + 0 + 1 + write-only + + + PERRST + Peripheral Reset + 2 + 1 + write-only + + + EXTRST + External Reset + 3 + 1 + write-only + + + KEY + System Reset Key + 24 + 8 + write-only + + + + + SR + Status Register + 0x00000004 + 32 + read-only + 0x00000000 + + + URSTS + User Reset Status + 0 + 1 + read-only + + + RSTTYP + Reset Type + 8 + 3 + read-only + + + NRSTL + NRST Pin Level + 16 + 1 + read-only + + + SRCMP + Software Reset Command in Progress + 17 + 1 + read-only + + + + + MR + Mode Register + 0x00000008 + 32 + read-write + 0x00000001 + + + URSTEN + User Reset Enable + 0 + 1 + read-write + + + URSTIEN + User Reset Interrupt Enable + 4 + 1 + read-write + + + ERSTL + External Reset Length + 8 + 4 + read-write + + + KEY + Password + 24 + 8 + read-write + + + + + + + SUPC + 6452M + Supply Controller + SYSC + SUPC_ + 0x400E1410 + + 0 + 0x200 + registers + + + + CR + Supply Controller Control Register + 0x00000000 + 32 + write-only + + + VROFF + Voltage Regulator Off + 2 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + STOP_VREG + if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. + 1 + + + + + XTALSEL + Crystal Oscillator Select + 3 + 1 + write-only + + + NO_EFFECT + no effect. + 0 + + + CRYSTAL_SEL + if KEY is correct, switches the slow clock on the crystal oscillator output. + 1 + + + + + KEY + Password + 24 + 8 + write-only + + + + + SMMR + Supply Controller Supply Monitor Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + SMTH + Supply Monitor Threshold + 0 + 4 + read-write + + + 1_9V + 1.9 V + 0x0 + + + 2_0V + 2.0 V + 0x1 + + + 2_1V + 2.1 V + 0x2 + + + 2_2V + 2.2 V + 0x3 + + + 2_3V + 2.3 V + 0x4 + + + 2_4V + 2.4 V + 0x5 + + + 2_5V + 2.5 V + 0x6 + + + 2_6V + 2.6 V + 0x7 + + + 2_7V + 2.7 V + 0x8 + + + 2_8V + 2.8 V + 0x9 + + + 2_9V + 2.9 V + 0xA + + + 3_0V + 3.0 V + 0xB + + + 3_1V + 3.1 V + 0xC + + + 3_2V + 3.2 V + 0xD + + + 3_3V + 3.3 V + 0xE + + + 3_4V + 3.4 V + 0xF + + + + + SMSMPL + Supply Monitor Sampling Period + 8 + 3 + read-write + + + SMD + Supply Monitor disabled + 0x0 + + + CSM + Continuous Supply Monitor + 0x1 + + + 32SLCK + Supply Monitor enabled one SLCK period every 32 SLCK periods + 0x2 + + + 256SLCK + Supply Monitor enabled one SLCK period every 256 SLCK periods + 0x3 + + + 2048SLCK + Supply Monitor enabled one SLCK period every 2,048 SLCK periods + 0x4 + + + + + SMRSTEN + Supply Monitor Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. + 1 + + + + + SMIEN + Supply Monitor Interrupt Enable + 13 + 1 + read-write + + + NOT_ENABLE + the SUPC interrupt signal is not affected when a supply monitor detection occurs. + 0 + + + ENABLE + the SUPC interrupt signal is asserted when a supply monitor detection occurs. + 1 + + + + + + + MR + Supply Controller Mode Register + 0x00000008 + 32 + read-write + 0x00005A00 + + + BODRSTEN + Brownout Detector Reset Enable + 12 + 1 + read-write + + + NOT_ENABLE + the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. + 0 + + + ENABLE + the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. + 1 + + + + + BODDIS + Brownout Detector Disable + 13 + 1 + read-write + + + ENABLE + the core brownout detector is enabled. + 0 + + + DISABLE + the core brownout detector is disabled. + 1 + + + + + ONREG + Voltage Regulator enable + 14 + 1 + read-write + + + ONREG_UNUSED + Voltage Regulator is not used + 0 + + + ONREG_USED + Voltage Regulator is used + 1 + + + + + OSCBYPASS + Oscillator Bypass + 20 + 1 + read-write + + + NO_EFFECT + no effect. Clock selection depends on XTALSEL value. + 0 + + + BYPASS + the 32-KHz XTAL oscillator is selected and is put in bypass mode. + 1 + + + + + KEY + Password Key + 24 + 8 + read-write + + + + + WUMR + Supply Controller Wake Up Mode Register + 0x0000000C + 32 + read-write + 0x00000000 + + + SMEN + Supply Monitor Wake Up Enable + 1 + 1 + read-write + + + NOT_ENABLE + the supply monitor detection has no wake up effect. + 0 + + + ENABLE + the supply monitor detection forces the wake up of the core power supply. + 1 + + + + + RTTEN + Real Time Timer Wake Up Enable + 2 + 1 + read-write + + + NOT_ENABLE + the RTT alarm signal has no wake up effect. + 0 + + + ENABLE + the RTT alarm signal forces the wake up of the core power supply. + 1 + + + + + RTCEN + Real Time Clock Wake Up Enable + 3 + 1 + read-write + + + NOT_ENABLE + the RTC alarm signal has no wake up effect. + 0 + + + ENABLE + the RTC alarm signal forces the wake up of the core power supply. + 1 + + + + + LPDBCEN0 + Low power Debouncer ENable WKUP0 + 5 + 1 + read-write + + + NOT_ENABLE + the WKUP0 input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP0 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCEN1 + Low power Debouncer ENable WKUP1 + 6 + 1 + read-write + + + NOT_ENABLE + the WKUP1input pin is not connected with low power debouncer. + 0 + + + ENABLE + the WKUP1 input pin is connected with low power debouncer and can force a core wake up. + 1 + + + + + LPDBCCLR + Low power Debouncer Clear + 7 + 1 + read-write + + + NOT_ENABLE + a low power debounce event does not create an immediate clear on first half GPBR registers. + 0 + + + ENABLE + a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers. + 1 + + + + + WKUPDBC + Wake Up Inputs Debouncer Period + 12 + 3 + read-write + + + IMMEDIATE + Immediate, no debouncing, detected active at least on one Slow Clock edge. + 0x0 + + + 3_SCLK + WKUPx shall be in its active state for at least 3 SLCK periods + 0x1 + + + 32_SCLK + WKUPx shall be in its active state for at least 32 SLCK periods + 0x2 + + + 512_SCLK + WKUPx shall be in its active state for at least 512 SLCK periods + 0x3 + + + 4096_SCLK + WKUPx shall be in its active state for at least 4,096 SLCK periods + 0x4 + + + 32768_SCLK + WKUPx shall be in its active state for at least 32,768 SLCK periods + 0x5 + + + + + LPDBC + Low Power DeBounCer Period + 16 + 3 + read-write + + + DISABLE + Disable the low power debouncer. + 0x0 + + + 2_RTCOUT0 + WKUP0/1 in its active state for at least 2 RTCOUT0 periods + 0x1 + + + 3_RTCOUT0 + WKUP0/1 in its active state for at least 3 RTCOUT0 periods + 0x2 + + + 4_RTCOUT0 + WKUP0/1 in its active state for at least 4 RTCOUT0 periods + 0x3 + + + 5_RTCOUT0 + WKUP0/1 in its active state for at least 5 RTCOUT0 periods + 0x4 + + + 6_RTCOUT0 + WKUP0/1 in its active state for at least 6 RTCOUT0 periods + 0x5 + + + 7_RTCOUT0 + WKUP0/1 in its active state for at least 7 RTCOUT0 periods + 0x6 + + + 8_RTCOUT0 + WKUP0/1 in its active state for at least 8 RTCOUT0 periods + 0x7 + + + + + + + WUIR + Supply Controller Wake Up Inputs Register + 0x00000010 + 32 + read-write + 0x00000000 + + + WKUPEN0 + Wake Up Input Enable 0 + 0 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN1 + Wake Up Input Enable 1 + 1 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN2 + Wake Up Input Enable 2 + 2 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN3 + Wake Up Input Enable 3 + 3 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN4 + Wake Up Input Enable 4 + 4 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN5 + Wake Up Input Enable 5 + 5 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN6 + Wake Up Input Enable 6 + 6 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN7 + Wake Up Input Enable 7 + 7 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN8 + Wake Up Input Enable 8 + 8 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN9 + Wake Up Input Enable 9 + 9 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN10 + Wake Up Input Enable 10 + 10 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN11 + Wake Up Input Enable 11 + 11 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN12 + Wake Up Input Enable 12 + 12 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN13 + Wake Up Input Enable 13 + 13 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN14 + Wake Up Input Enable 14 + 14 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPEN15 + Wake Up Input Enable 15 + 15 + 1 + read-write + + + DISABLE + the corresponding wake-up input has no wake up effect. + 0 + + + ENABLE + the corresponding wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT0 + Wake Up Input Type 0 + 16 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT1 + Wake Up Input Type 1 + 17 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT2 + Wake Up Input Type 2 + 18 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT3 + Wake Up Input Type 3 + 19 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT4 + Wake Up Input Type 4 + 20 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT5 + Wake Up Input Type 5 + 21 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT6 + Wake Up Input Type 6 + 22 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT7 + Wake Up Input Type 7 + 23 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT8 + Wake Up Input Type 8 + 24 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT9 + Wake Up Input Type 9 + 25 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT10 + Wake Up Input Type 10 + 26 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT11 + Wake Up Input Type 11 + 27 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT12 + Wake Up Input Type 12 + 28 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT13 + Wake Up Input Type 13 + 29 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT14 + Wake Up Input Type 14 + 30 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + WKUPT15 + Wake Up Input Type 15 + 31 + 1 + read-write + + + LOW + a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply. + 0 + + + HIGH + a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply. + 1 + + + + + + + SR + Supply Controller Status Register + 0x00000014 + 32 + read-only + 0x00000800 + + + WKUPS + WKUP Wake Up Status + 1 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. + 1 + + + + + SMWS + Supply Monitor Detection Wake Up Status + 2 + 1 + read-only + + + NO + no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. + 1 + + + + + BODRSTS + Brownout Detector Reset Status + 3 + 1 + read-only + + + NO + no core brownout rising edge event has been detected since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one brownout output rising edge event has been detected since the last read of the SUPC_SR. + 1 + + + + + SMRSTS + Supply Monitor Reset Status + 4 + 1 + read-only + + + NO + no supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. + 1 + + + + + SMS + Supply Monitor Status + 5 + 1 + read-only + + + NO + no supply monitor detection since the last read of SUPC_SR. + 0 + + + PRESENT + at least one supply monitor detection since the last read of SUPC_SR. + 1 + + + + + SMOS + Supply Monitor Output Status + 6 + 1 + read-only + + + HIGH + the supply monitor detected VDDIO higher than its threshold at its last measurement. + 0 + + + LOW + the supply monitor detected VDDIO lower than its threshold at its last measurement. + 1 + + + + + OSCSEL + 32-kHz Oscillator Selection Status + 7 + 1 + read-only + + + RC + the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. + 0 + + + CRYST + the slow clock, SLCK is generated by the 32-kHz crystal oscillator. + 1 + + + + + LPDBCS0 + Low Power Debouncer Wake Up Status on WKUP0 + 13 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. + 1 + + + + + LPDBCS1 + Low Power Debouncer Wake Up Status on WKUP1 + 14 + 1 + read-only + + + NO + no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 0 + + + PRESENT + at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. + 1 + + + + + WKUPIS0 + WKUP Input Status 0 + 16 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS1 + WKUP Input Status 1 + 17 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS2 + WKUP Input Status 2 + 18 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS3 + WKUP Input Status 3 + 19 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS4 + WKUP Input Status 4 + 20 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS5 + WKUP Input Status 5 + 21 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS6 + WKUP Input Status 6 + 22 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS7 + WKUP Input Status 7 + 23 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS8 + WKUP Input Status 8 + 24 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS9 + WKUP Input Status 9 + 25 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS10 + WKUP Input Status 10 + 26 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS11 + WKUP Input Status 11 + 27 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS12 + WKUP Input Status 12 + 28 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS13 + WKUP Input Status 13 + 29 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS14 + WKUP Input Status 14 + 30 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + WKUPIS15 + WKUP Input Status 15 + 31 + 1 + read-only + + + DIS + the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. + 0 + + + EN + the corresponding wake-up input was active at the time the debouncer triggered a wake up event. + 1 + + + + + + + + + RTT + 6081F + Real-time Timer + SYSC + RTT_ + 0x400E1430 + + 0 + 0x200 + registers + + + + MR + Mode Register + 0x00000000 + 32 + read-write + 0x00008000 + + + RTPRES + Real-time Timer Prescaler Value + 0 + 16 + read-write + + + ALMIEN + Alarm Interrupt Enable + 16 + 1 + read-write + + + RTTINCIEN + Real-time Timer Increment Interrupt Enable + 17 + 1 + read-write + + + RTTRST + Real-time Timer Restart + 18 + 1 + read-write + + + RTTDIS + Real-time Timer Disable + 20 + 1 + read-write + + + RTC1HZ + Real-Time Clock 1Hz Clock Selection + 24 + 1 + read-write + + + + + AR + Alarm Register + 0x00000004 + 32 + read-write + 0xFFFFFFFF + + + ALMV + Alarm Value + 0 + 32 + read-write + + + + + VR + Value Register + 0x00000008 + 32 + read-only + 0x00000000 + + + CRTV + Current Real-time Value + 0 + 32 + read-only + + + + + SR + Status Register + 0x0000000C + 32 + read-only + 0x00000000 + + + ALMS + Real-time Alarm Status + 0 + 1 + read-only + + + RTTINC + Real-time Timer Increment + 1 + 1 + read-only + + + + + + + WDT + 6080B + Watchdog Timer + SYSC + WDT_ + 0x400E1450 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + write-only + + + WDRSTT + Watchdog Restart + 0 + 1 + write-only + + + KEY + Password + 24 + 8 + write-only + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x3FFF2FFF + + + WDV + Watchdog Counter Value + 0 + 12 + read-write + + + WDFIEN + Watchdog Fault Interrupt Enable + 12 + 1 + read-write + + + WDRSTEN + Watchdog Reset Enable + 13 + 1 + read-write + + + WDRPROC + Watchdog Reset Processor + 14 + 1 + read-write + + + WDDIS + Watchdog Disable + 15 + 1 + read-write + + + WDD + Watchdog Delta Value + 16 + 12 + read-write + + + WDDBGHLT + Watchdog Debug Halt + 28 + 1 + read-write + + + WDIDLEHLT + Watchdog Idle Halt + 29 + 1 + read-write + + + + + SR + Status Register + 0x00000008 + 32 + read-only + 0x00000000 + + + WDUNF + Watchdog Underflow + 0 + 1 + read-only + + + WDERR + Watchdog Error + 1 + 1 + read-only + + + + + + + RTC + 6056K + Real-time Clock + SYSC + RTC_ + 0x400E1460 + + 0 + 0x200 + registers + + + + CR + Control Register + 0x00000000 + 32 + read-write + 0x00000000 + + + UPDTIM + Update Request Time Register + 0 + 1 + read-write + + + UPDCAL + Update Request Calendar Register + 1 + 1 + read-write + + + TIMEVSEL + Time Event Selection + 8 + 2 + read-write + + + MINUTE + Minute change + 0x0 + + + HOUR + Hour change + 0x1 + + + MIDNIGHT + Every day at midnight + 0x2 + + + NOON + Every day at noon + 0x3 + + + + + CALEVSEL + Calendar Event Selection + 16 + 2 + read-write + + + WEEK + Week change (every Monday at time 00:00:00) + 0x0 + + + MONTH + Month change (every 01 of each month at time 00:00:00) + 0x1 + + + YEAR + Year change (every January 1 at time 00:00:00) + 0x2 + + + + + + + MR + Mode Register + 0x00000004 + 32 + read-write + 0x00000000 + + + HRMOD + 12-/24-hour Mode + 0 + 1 + read-write + + + PERSIAN + PERSIAN Calendar + 1 + 1 + read-write + + + NEGPPM + NEGative PPM Correction + 4 + 1 + read-write + + + CORRECTION + Slow Clock Correction + 8 + 7 + read-write + + + HIGHPPM + HIGH PPM Correction + 15 + 1 + read-write + + + OUT0 + RTCOUT0 Output Source Selection + 16 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + OUT1 + RTCOUT1 Output Source Selection + 20 + 3 + read-write + + + NO_WAVE + no waveform, stuck at '0' + 0x0 + + + FREQ1HZ + 1 Hz square wave + 0x1 + + + FREQ32HZ + 32 Hz square wave + 0x2 + + + FREQ64HZ + 64 Hz square wave + 0x3 + + + FREQ512HZ + 512 Hz square wave + 0x4 + + + ALARM_TOGGLE + output toggles when alarm flag rises + 0x5 + + + ALARM_FLAG + output is a copy of the alarm flag + 0x6 + + + PROG_PULSE + duty cycle programmable pulse + 0x7 + + + + + THIGH + High Duration of the Output Pulse + 24 + 3 + read-write + + + H_31MS + 31.2 ms + 0x0 + + + H_16MS + 15.6 ms + 0x1 + + + H_4MS + 3.91 ms + 0x2 + + + H_976US + 976 us + 0x3 + + + H_488US + 488 us + 0x4 + + + H_122US + 122 us + 0x5 + + + H_30US + 30.5 us + 0x6 + + + H_15US + 15.2 us + 0x7 + + + + + TPERIOD + Period of the Output Pulse + 28 + 2 + read-write + + + P_1S + 1 second + 0x0 + + + P_500MS + 500 ms + 0x1 + + + P_250MS + 250 ms + 0x2 + + + P_125MS + 125 ms + 0x3 + + + + + + + TIMR + Time Register + 0x00000008 + 32 + read-write + 0x00000000 + + + SEC + Current Second + 0 + 7 + read-write + + + MIN + Current Minute + 8 + 7 + read-write + + + HOUR + Current Hour + 16 + 6 + read-write + + + AMPM + Ante Meridiem Post Meridiem Indicator + 22 + 1 + read-write + + + + + CALR + Calendar Register + 0x0000000C + 32 + read-write + 0x01810720 + + + CENT + Current Century + 0 + 7 + read-write + + + YEAR + Current Year + 8 + 8 + read-write + + + MONTH + Current Month + 16 + 5 + read-write + + + DAY + Current Day in Current Week + 21 + 3 + read-write + + + DATE + Current Day in Current Month + 24 + 6 + read-write + + + + + TIMALR + Time Alarm Register + 0x00000010 + 32 + read-write + 0x00000000 + + + SEC + Second Alarm + 0 + 7 + read-write + + + SECEN + Second Alarm Enable + 7 + 1 + read-write + + + MIN + Minute Alarm + 8 + 7 + read-write + + + MINEN + Minute Alarm Enable + 15 + 1 + read-write + + + HOUR + Hour Alarm + 16 + 6 + read-write + + + AMPM + AM/PM Indicator + 22 + 1 + read-write + + + HOUREN + Hour Alarm Enable + 23 + 1 + read-write + + + + + CALALR + Calendar Alarm Register + 0x00000014 + 32 + read-write + 0x01010000 + + + MONTH + Month Alarm + 16 + 5 + read-write + + + MTHEN + Month Alarm Enable + 23 + 1 + read-write + + + DATE + Date Alarm + 24 + 6 + read-write + + + DATEEN + Date Alarm Enable + 31 + 1 + read-write + + + + + SR + Status Register + 0x00000018 + 32 + read-only + 0x00000000 + + + ACKUPD + Acknowledge for Update + 0 + 1 + read-only + + + FREERUN + Time and calendar registers cannot be updated. + 0 + + + UPDATE + Time and calendar registers can be updated. + 1 + + + + + ALARM + Alarm Flag + 1 + 1 + read-only + + + NO_ALARMEVENT + No alarm matching condition occurred. + 0 + + + ALARMEVENT + An alarm matching condition has occurred. + 1 + + + + + SEC + Second Event + 2 + 1 + read-only + + + NO_SECEVENT + No second event has occurred since the last clear. + 0 + + + SECEVENT + At least one second event has occurred since the last clear. + 1 + + + + + TIMEV + Time Event + 3 + 1 + read-only + + + NO_TIMEVENT + No time event has occurred since the last clear. + 0 + + + TIMEVENT + At least one time event has occurred since the last clear. + 1 + + + + + CALEV + Calendar Event + 4 + 1 + read-only + + + NO_CALEVENT + No calendar event has occurred since the last clear. + 0 + + + CALEVENT + At least one calendar event has occurred since the last clear. + 1 + + + + + TDERR + Time and/or Date Free Running Error + 5 + 1 + read-only + + + CORRECT + The internal free running counters are carrying valid values since the last read of RTC_SR. + 0 + + + ERR_TIMEDATE + The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. + 1 + + + + + + + SCCR + Status Clear Command Register + 0x0000001C + 32 + write-only + + + ACKCLR + Acknowledge Clear + 0 + 1 + write-only + + + ALRCLR + Alarm Clear + 1 + 1 + write-only + + + SECCLR + Second Clear + 2 + 1 + write-only + + + TIMCLR + Time Clear + 3 + 1 + write-only + + + CALCLR + Calendar Clear + 4 + 1 + write-only + + + TDERRCLR + Time and/or Date Free Running Error Clear + 5 + 1 + write-only + + + + + IER + Interrupt Enable Register + 0x00000020 + 32 + write-only + + + ACKEN + Acknowledge Update Interrupt Enable + 0 + 1 + write-only + + + ALREN + Alarm Interrupt Enable + 1 + 1 + write-only + + + SECEN + Second Event Interrupt Enable + 2 + 1 + write-only + + + TIMEN + Time Event Interrupt Enable + 3 + 1 + write-only + + + CALEN + Calendar Event Interrupt Enable + 4 + 1 + write-only + + + TDERREN + Time and/or Date Error Interrupt Enable + 5 + 1 + write-only + + + + + IDR + Interrupt Disable Register + 0x00000024 + 32 + write-only + + + ACKDIS + Acknowledge Update Interrupt Disable + 0 + 1 + write-only + + + ALRDIS + Alarm Interrupt Disable + 1 + 1 + write-only + + + SECDIS + Second Event Interrupt Disable + 2 + 1 + write-only + + + TIMDIS + Time Event Interrupt Disable + 3 + 1 + write-only + + + CALDIS + Calendar Event Interrupt Disable + 4 + 1 + write-only + + + TDERRDIS + Time and/or Date Error Interrupt Disable + 5 + 1 + write-only + + + + + IMR + Interrupt Mask Register + 0x00000028 + 32 + read-only + 0x00000000 + + + ACK + Acknowledge Update Interrupt Mask + 0 + 1 + read-only + + + ALR + Alarm Interrupt Mask + 1 + 1 + read-only + + + SEC + Second Event Interrupt Mask + 2 + 1 + read-only + + + TIM + Time Event Interrupt Mask + 3 + 1 + read-only + + + CAL + Calendar Event Interrupt Mask + 4 + 1 + read-only + + + + + VER + Valid Entry Register + 0x0000002C + 32 + read-only + 0x00000000 + + + NVTIM + Non-valid Time + 0 + 1 + read-only + + + NVCAL + Non-valid Calendar + 1 + 1 + read-only + + + NVTIMALR + Non-valid Time Alarm + 2 + 1 + read-only + + + NVCALALR + Non-valid Calendar Alarm + 3 + 1 + read-only + + + + + + + GPBR + 6378C + General Purpose Backup Register + SYSC + GPBR_ + 0x400E1490 + + 0 + 0x200 + registers + + + + 8 + 4 + 0-7 + GPBR[%s] + General Purpose Backup Register + 0x00000000 + 32 + read-write + + + GPBR_VALUE + Value of GPBR x + 0 + 32 + read-write + + + + + + + diff --git a/zephyr/ports/asf/sam3sd8/templates/library.c b/zephyr/ports/asf/sam3sd8/templates/library.c new file mode 100644 index 0000000..369a571 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/templates/library.c @@ -0,0 +1,15 @@ +/* + * $projectname$.c + * + * Created: $date$ + * Author : $user$ + */ + +#include "sam.h" + + +/* Replace with your library code */ +int myfunc(void) +{ + return 0; +} diff --git a/zephyr/ports/asf/sam3sd8/templates/library.cpp b/zephyr/ports/asf/sam3sd8/templates/library.cpp new file mode 100644 index 0000000..e4a6991 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/templates/library.cpp @@ -0,0 +1,15 @@ +/* + * $projectname$.cpp + * + * Created: $date$ + * Author : $user$ + */ + +#include "sam.h" + + +/* Replace with your library code */ +int myfunc(void) +{ + return 0; +} diff --git a/zephyr/ports/asf/sam3sd8/templates/main.c b/zephyr/ports/asf/sam3sd8/templates/main.c new file mode 100644 index 0000000..95f1b43 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/templates/main.c @@ -0,0 +1,21 @@ +/* + * $projectname$.c + * + * Created: $date$ + * Author : $user$ + */ + + +#include "sam.h" + + +int main(void) +{ + /* Initialize the SAM system */ + SystemInit(); + + /* Replace with your application code */ + while (1) + { + } +} diff --git a/zephyr/ports/asf/sam3sd8/templates/main.cpp b/zephyr/ports/asf/sam3sd8/templates/main.cpp new file mode 100644 index 0000000..fd8a7b8 --- /dev/null +++ b/zephyr/ports/asf/sam3sd8/templates/main.cpp @@ -0,0 +1,21 @@ +/* + * $projectname$.cpp + * + * Created: $date$ + * Author : $user$ + */ + + +#include "sam.h" + + +int main(void) +{ + /* Initialize the SAM system */ + SystemInit(); + + /* Replace with your application code */ + while (1) + { + } +} diff --git a/zephyr/ports/ports.cmake b/zephyr/ports/ports.cmake new file mode 100644 index 0000000..6fb33bf --- /dev/null +++ b/zephyr/ports/ports.cmake @@ -0,0 +1,3 @@ +list(APPEND DTS_ROOT ${CMAKE_CURRENT_LIST_DIR}) +list(APPEND SOC_ROOT ${CMAKE_CURRENT_LIST_DIR}) +list(APPEND BOARD_ROOT ${CMAKE_CURRENT_LIST_DIR}) diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/CMakeLists.txt b/zephyr/ports/soc/arm/atmel_sam/sam3s/CMakeLists.txt new file mode 100644 index 0000000..332416b --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.defconfig.series b/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.defconfig.series new file mode 100644 index 0000000..8011e2d --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.defconfig.series @@ -0,0 +1,32 @@ +# Atmel SAM3S MCU series configuration options + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM3S + +config SOC_SERIES + default "sam3s" + +config SOC_PART_NUMBER + default "sam3s16c" if SOC_PART_NUMBER_SAM3S16C + default "sam3sa16c" if SOC_PART_NUMBER_SAM3SA16C + default "sam3s16b" if SOC_PART_NUMBER_SAM3S16B + default "sam3s8c" if SOC_PART_NUMBER_SAM3S8C + default "sam3s8b" if SOC_PART_NUMBER_SAM3S8B + default "sam3s4c" if SOC_PART_NUMBER_SAM3S4C + default "sam3s4b" if SOC_PART_NUMBER_SAM3S4B + default "sam3s4a" if SOC_PART_NUMBER_SAM3S4A + default "sam3s2c" if SOC_PART_NUMBER_SAM3S2C + default "sam3s2b" if SOC_PART_NUMBER_SAM3S2B + default "sam3s2a" if SOC_PART_NUMBER_SAM3S2A + +# +# SAM3S family has total 35 peripherals capable of +# generating interrupts. +# +config NUM_IRQS + default 35 + +endif # SOC_SERIES_SAM3S diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.series b/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.series new file mode 100644 index 0000000..b019437 --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.series @@ -0,0 +1,20 @@ +# Atmel SAM3S MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2020-2023 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM3S + bool "Atmel SAM3S MCU" + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select SOC_FAMILY_SAM + select PLATFORM_SPECIFIC_INIT + select ASF + help + Enable support for Atmel SAM3S Cortex-M4 microcontrollers. + Part No.: SAM3S16C, SAM3S16B, SAM3S8C, SAM3S8B, + SAM3S4C, SAM3S4B, SAM3S4A, SAM3S2C, SAM3S2B, SAM3S2A diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.soc b/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.soc new file mode 100644 index 0000000..8ce342a --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/Kconfig.soc @@ -0,0 +1,111 @@ +# Atmel SAM3S MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Atmel SAM3S MCU Selection" + depends on SOC_SERIES_SAM3S + + config SOC_PART_NUMBER_SAM3S16C + bool "SAM3S16C" + + config SOC_PART_NUMBER_SAM3SA16C + bool "SAM3SA16C" + + config SOC_PART_NUMBER_SAM3S16B + bool "SAM3S16B" + + config SOC_PART_NUMBER_SAM3S8C + bool "SAM3S8C" + + config SOC_PART_NUMBER_SAM3S8B + bool "SAM3S8B" + + config SOC_PART_NUMBER_SAM3S4C + bool "SAM3S4C" + + config SOC_PART_NUMBER_SAM3S4B + bool "SAM3S4B" + + config SOC_PART_NUMBER_SAM3S4A + bool "SAM3S4A" + + config SOC_PART_NUMBER_SAM3S2C + bool "SAM3S2C" + + config SOC_PART_NUMBER_SAM3S2B + bool "SAM3S2B" + + config SOC_PART_NUMBER_SAM3S2A + bool "SAM3S2A" + +endchoice + +if SOC_SERIES_SAM3S + +config SOC_ATMEL_SAM3S_EXT_SLCK + bool "Atmel SAM3S to use external crystal oscillator for slow clock" + help + Says y if you want to use external 32 kHz crystal + oscillator to drive the slow clock. Note that this + adds a few seconds to boot time, as the crystal + needs to stabilize after power-up. + + Says n if you do not need accurate and precise timers. + The slow clock will be driven by the internal fast + RC oscillator running at 32 kHz. + +config SOC_ATMEL_SAM3S_EXT_MAINCK + bool "Atmel SAM3S to use external crystal oscillator for main clock" + help + The main clock is being used to drive the PLL, and + thus driving the processor clock. + + Says y if you want to use external crystal oscillator + to drive the main clock. Note that this adds about + a second to boot time, as the crystal needs to + stabilize after power-up. + + The crystal used here can be from 3 to 20 MHz. + + Says n here will use the internal fast RC oscillator + running at 12 MHz. + +config SOC_ATMEL_SAM3S_PLLA_MULA + hex "PLL MULA" + default 0x09 + help + This is the multiplier (MULA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + With default of MULA == 9, and DIVA == 1, + PLL is running at 10 times of main clock. + +config SOC_ATMEL_SAM3S_PLLA_DIVA + hex "PLL DIVA" + default 0x01 + help + This is the divider (DIVA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + With default of MULA == 9, and DIVA == 1, + PLL is running at 10 times of main clock. + +config SOC_ATMEL_SAM3S_WAIT_MODE + bool "Atmel SAM3S goes to Wait mode instead of Sleep mode" + depends on SOC_ATMEL_SAM3S_EXT_MAINCK + default y if DEBUG + help + For JTAG debugging CPU clock (HCLK) should not stop. In order + to achieve this, make CPU go to Wait mode instead of Sleep + mode while using external crystal oscillator for main clock. + +endif # SOC_SERIES_SAM3S diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/linker.ld b/zephyr/ports/soc/arm/atmel_sam/sam3s/linker.ld new file mode 100644 index 0000000..757d858 --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/linker.ld @@ -0,0 +1,9 @@ +/* linker.ld - Linker command/script file */ + +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/soc.c b/zephyr/ports/soc/arm/atmel_sam/sam3s/soc.c new file mode 100644 index 0000000..dbcc3a0 --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/soc.c @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2023 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM3S MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM3S series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clock on SoC at boot time. + * + * Setup the SoC clocks according to section 28.12 in datasheet. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + uint32_t reg_val; + +#ifdef CONFIG_SOC_ATMEL_SAM3S_EXT_SLCK + /* Switch slow clock to the external 32 KHz crystal oscillator. */ + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL; + + /* Wait for oscillator to be stabilized. */ + while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) { + ; + } + +#endif /* CONFIG_SOC_ATMEL_SAM3S_EXT_SLCK */ + +#ifdef CONFIG_SOC_ATMEL_SAM3S_EXT_MAINCK + /* + * Setup main external crystal oscillator. + */ + + /* Start the external crystal oscillator. */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + /* Fast RC oscillator frequency is at 4 MHz. */ + | CKGR_MOR_MOSCRCF_4_MHz + /* + * We select maximum setup time. While start up time + * could be shortened this optimization is not deemed + * critical right now. + */ + | CKGR_MOR_MOSCXTST(0xFFu) + /* RC oscillator must stay on. */ + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTEN; + + /* Wait for oscillator to be stabilized. */ + while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) { + ; + } + + /* Select the external crystal oscillator as the main clock source. */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCRCF_4_MHz + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTEN + | CKGR_MOR_MOSCXTST(0xFFu) + | CKGR_MOR_MOSCSEL; + + /* Wait for external oscillator to be selected. */ + while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) { + ; + } + + /* Turn off RC oscillator, not used any longer, to save power */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCSEL + | CKGR_MOR_MOSCXTST(0xFFu) + | CKGR_MOR_MOSCXTEN; + + /* Wait for the RC oscillator to be turned off. */ + while (PMC->PMC_SR & PMC_SR_MOSCRCS) { + ; + } + +#ifdef CONFIG_SOC_ATMEL_SAM3S_WAIT_MODE + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + PMC->PMC_FSMR |= PMC_FSMR_LPM; +#endif +#else + /* Setup main fast RC oscillator. */ + + /* + * NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR + * register, should normally be the case. + */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { + ; + } + + /* Set main fast RC oscillator to 12 MHz. */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCRCF_12_MHz + | CKGR_MOR_MOSCRCEN; + + /* Wait for RC oscillator to stabilize. */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) { + ; + } +#endif /* CONFIG_SOC_ATMEL_SAM3S_EXT_MAINCK */ + + /* + * Setup PLLA + */ + + /* Switch MCK (Master Clock) to the main clock first. */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK; + + /* Wait for clock selection to complete. */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Setup PLLA. */ + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE + | CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAM3S_PLLA_MULA) + | CKGR_PLLAR_PLLACOUNT(0x3Fu) + | CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAM3S_PLLA_DIVA); + + /* + * NOTE: Both MULA and DIVA must be set to a value greater than 0 or + * otherwise PLL will be disabled. In this case we would get stuck in + * the following loop. + */ + + /* Wait for PLL lock. */ + while (!(PMC->PMC_SR & PMC_SR_LOCKA)) { + ; + } + + /* + * Final setup of the Master Clock + */ + + /* + * NOTE: PMC_MCKR must not be programmed in a single write operation. + * If CSS or PRES are modified we must wait for MCKRDY bit to be + * set again. + */ + + /* Setup prescaler - PLLA Clock / Processor Clock (HCLK). */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1; + + /* Wait for Master Clock setup to complete */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } + + /* Finally select PLL as Master Clock source. */ + reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk; + PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK; + + /* Wait for Master Clock setup to complete. */ + while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) { + ; + } +} + +void z_arm_platform_init(void) +{ + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. Look at table 44.73 in the SAM3S datasheet. + * This is set to the highest number of read cycles because it won't + * hurt lower clock frequencies. However, a high frequency with too + * few read cycles could cause flash read problems. FWS 5 (6 cycles) + * is the safe setting for all of this SoCs usable frequencies. + * TODO: Add code to handle SAM3SD devices that have 2 EFCs. + */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(5); + + /* Setup system clocks. */ + clock_init(); +} diff --git a/zephyr/ports/soc/arm/atmel_sam/sam3s/soc.h b/zephyr/ports/soc/arm/atmel_sam/sam3s/soc.h new file mode 100644 index 0000000..6e4da72 --- /dev/null +++ b/zephyr/ports/soc/arm/atmel_sam/sam3s/soc.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2020 Gerson Fernando Budke + * Copyright (c) 2018 Vincent van der Locht + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM3S family processors. + */ + +#ifndef _ATMEL_SAM3S_SOC_H_ +#define _ATMEL_SAM3S_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_PART_NUMBER_SAM3S1A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S1B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S1C) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S2A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S2B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S2C) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S4A) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S4B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S4C) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S8B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3S8C) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3SD8B) +#include +#elif defined(CONFIG_SOC_PART_NUMBER_SAM3SD8C) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* !_ASMLANGUAGE */ + +#endif /* _ATMEL_SAM3S_SOC_H_ */