95 lines
8.6 KiB
C
95 lines
8.6 KiB
C
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3SD8_USART2_INSTANCE_
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#define _SAM3SD8_USART2_INSTANCE_
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/* ========== Register definition for USART2 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */
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#define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */
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#define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
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#define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
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#define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
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#define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */
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#define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
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#define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
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#define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
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#define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
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#define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
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#define REG_USART2_FIDI (0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
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#define REG_USART2_NER (0x4002C044U) /**< \brief (USART2) Number of Errors Register */
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#define REG_USART2_IF (0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
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#define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
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#define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
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#define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
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#define REG_USART2_VERSION (0x4002C0FCU) /**< \brief (USART2) Version Register */
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#define REG_USART2_RPR (0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
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#define REG_USART2_RCR (0x4002C104U) /**< \brief (USART2) Receive Counter Register */
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#define REG_USART2_TPR (0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
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#define REG_USART2_TCR (0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
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#define REG_USART2_RNPR (0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
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#define REG_USART2_RNCR (0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
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#define REG_USART2_TNPR (0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
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#define REG_USART2_TNCR (0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
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#define REG_USART2_PTCR (0x4002C120U) /**< \brief (USART2) Transfer Control Register */
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#define REG_USART2_PTSR (0x4002C124U) /**< \brief (USART2) Transfer Status Register */
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#else
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#define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */
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#define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */
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#define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */
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#define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */
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#define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */
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#define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */
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#define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receiver Holding Register */
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#define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmitter Holding Register */
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#define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */
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#define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */
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#define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */
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#define REG_USART2_FIDI (*(__IO uint32_t*)0x4002C040U) /**< \brief (USART2) FI DI Ratio Register */
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#define REG_USART2_NER (*(__I uint32_t*)0x4002C044U) /**< \brief (USART2) Number of Errors Register */
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#define REG_USART2_IF (*(__IO uint32_t*)0x4002C04CU) /**< \brief (USART2) IrDA Filter Register */
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#define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
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#define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protect Mode Register */
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#define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protect Status Register */
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#define REG_USART2_VERSION (*(__I uint32_t*)0x4002C0FCU) /**< \brief (USART2) Version Register */
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#define REG_USART2_RPR (*(__IO uint32_t*)0x4002C100U) /**< \brief (USART2) Receive Pointer Register */
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#define REG_USART2_RCR (*(__IO uint32_t*)0x4002C104U) /**< \brief (USART2) Receive Counter Register */
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#define REG_USART2_TPR (*(__IO uint32_t*)0x4002C108U) /**< \brief (USART2) Transmit Pointer Register */
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#define REG_USART2_TCR (*(__IO uint32_t*)0x4002C10CU) /**< \brief (USART2) Transmit Counter Register */
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#define REG_USART2_RNPR (*(__IO uint32_t*)0x4002C110U) /**< \brief (USART2) Receive Next Pointer Register */
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#define REG_USART2_RNCR (*(__IO uint32_t*)0x4002C114U) /**< \brief (USART2) Receive Next Counter Register */
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#define REG_USART2_TNPR (*(__IO uint32_t*)0x4002C118U) /**< \brief (USART2) Transmit Next Pointer Register */
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#define REG_USART2_TNCR (*(__IO uint32_t*)0x4002C11CU) /**< \brief (USART2) Transmit Next Counter Register */
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#define REG_USART2_PTCR (*(__O uint32_t*)0x4002C120U) /**< \brief (USART2) Transfer Control Register */
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#define REG_USART2_PTSR (*(__I uint32_t*)0x4002C124U) /**< \brief (USART2) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3SD8_USART2_INSTANCE_ */
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