7868 lines
618 KiB
Plaintext
7868 lines
618 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- ============================================================================ -->
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<!-- Atmel Microcontroller Software Support -->
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<!-- SAM Software Package License -->
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<!-- ============================================================================ -->
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<!-- Copyright (c) %copyright_year%, Atmel Corporation -->
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<!-- -->
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<!-- All rights reserved. -->
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<!-- -->
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<!-- Redistribution and use in source and binary forms, with or without -->
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<!-- modification, are permitted provided that the following condition is met: -->
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<!-- -->
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<!-- - Redistributions of source code must retain the above copyright notice, -->
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<!-- this list of conditions and the disclaimer below. -->
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<!-- -->
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<!-- Atmel's name may not be used to endorse or promote products derived from -->
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<!-- this software without specific prior written permission. -->
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<!-- -->
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<!-- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -->
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<!-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -->
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<!-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -->
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<!-- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -->
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<!-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -->
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<!-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -->
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<!-- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -->
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<!-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -->
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<!-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -->
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<!-- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -->
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<!-- ============================================================================ -->
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<avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.6" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
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<variants>
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<variant ordercode="ATSAM3S8B-AU" package="LQFP64" speedmax="64000000" tempmax="+85" tempmin="-40" vccmax="3.6" vccmin="1.8"/>
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<variant ordercode="ATSAM3S8B-MU" package="QFN64" speedmax="64000000" tempmax="+85" tempmin="-40" vccmax="3.6" vccmin="1.8"/>
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</variants>
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<devices>
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<device architecture="CORTEX-M3" family="SAM3" name="ATSAM3S8B" series="SAM3SD8">
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<address-spaces>
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<address-space id="base" name="base" endianness="little" size="0x100000000" start="0">
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<memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io"/>
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<memory-segment name="SYSTEM" start="0xE0000000" size="0x10000000" type="io"/>
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<memory-segment name="IROM" start="0x00800000" size="0x00400000" type="rom"/>
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<memory-segment name="IRAM" start="0x20000000" size="0x00010000" type="ram"/>
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<memory-segment name="EBI_CS0" start="0x60000000" size="0x01000000" type="other"/>
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<memory-segment name="EBI_CS1" start="0x61000000" size="0x01000000" type="other"/>
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<memory-segment name="EBI_CS2" start="0x62000000" size="0x01000000" type="other"/>
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<memory-segment name="EBI_CS3" start="0x63000000" size="0x01000000" type="other"/>
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<memory-segment name="IFLASH" start="0x00400000" size="0x00080000" type="flash" pagesize="256"/></address-space>
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<address-space id="fuses" name="fuses" endianness="little" size="1" start="0"/>
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<address-space id="lockbits" name="lockbits" endianness="little" size="0x2" start="0"/>
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</address-spaces>
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<peripherals>
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<module name="ACC" version="6490C">
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<instance name="ACC">
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<register-group address-space="base" name="ACC" name-in-module="ACC" offset="0x40040000"/>
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</instance>
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</module>
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<module name="ADC" version="6489I">
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<instance name="ADC">
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<register-group address-space="base" name="ADC" name-in-module="ADC" offset="0x40038000"/>
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<signals>
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<signal pad="PA8" function="B" group="ADTRG"/>
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<signal pad="PA17" function="X1" group="AD" index="0"/>
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<signal pad="PA18" function="X1" group="AD" index="1"/>
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<signal pad="PA19" function="X1" group="AD" index="2"/>
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<signal pad="PA19" function="X1" group="WKUP" index="9"/>
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<signal pad="PA20" function="X1" group="AD" index="3"/>
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<signal pad="PA20" function="X1" group="WKUP" index="10"/>
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<signal pad="PB0" function="X1" group="AD" index="4"/>
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<signal pad="PB0" function="X1" group="RTCOUT" index="0"/>
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<signal pad="PB1" function="X1" group="AD" index="5"/>
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<signal pad="PB1" function="X1" group="RTCOUT" index="1"/>
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<signal pad="PB2" function="X1" group="AD" index="6"/>
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<signal pad="PB2" function="X1" group="WKUP" index="12"/>
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<signal pad="PB3" function="X1" group="AD" index="7"/>
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<signal pad="PA21" function="X1" group="AD" index="8"/>
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<signal pad="PA22" function="X1" group="AD" index="9"/>
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<signal pad="PC13" function="X1" group="AD" index="10"/>
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<signal pad="PC15" function="X1" group="AD" index="11"/>
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<signal pad="PC12" function="X1" group="AD" index="12"/>
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<signal pad="PC29" function="X1" group="AD" index="13"/>
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<signal pad="PC30" function="X1" group="AD" index="14"/>
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</signals>
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</instance>
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</module>
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<module name="CHIPID" version="6417K">
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<instance name="CHIPID">
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<register-group address-space="base" name="CHIPID" name-in-module="CHIPID" offset="0x400E0740"/>
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</instance>
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</module>
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<module name="CRCCU" version="11001D">
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<instance name="CRCCU">
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<register-group address-space="base" name="CRCCU" name-in-module="CRCCU" offset="0x40044000"/>
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</instance>
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</module>
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<module name="DACC" version="6461F">
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<instance name="DACC">
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<register-group address-space="base" name="DACC" name-in-module="DACC" offset="0x4003C000"/>
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<signals>
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<signal pad="PB13" function="X1" group="DAC" index="0"/>
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<signal pad="PB14" function="X1" group="DAC" index="1"/>
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<signal pad="PA2" function="C" group="DATRG"/>
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</signals>
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</instance>
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</module>
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<module name="EFC" version="6450G">
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<instance name="EFC">
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<register-group address-space="base" name="EFC" name-in-module="EFC" offset="0x400E0A00"/>
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<parameters>
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<param name="FLASH_SIZE" value="524288"/>
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<param name="PAGE_SIZE" value="256"/>
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<param name="PAGES_PR_REGION" value="128"/>
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</parameters>
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</instance>
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</module>
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<module name="GPBR" version="6378C">
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<instance name="GPBR">
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<register-group address-space="base" name="GPBR" name-in-module="GPBR" offset="0x400E1490"/>
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</instance>
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</module>
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<module name="HSMCI" version="6449H">
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<instance name="HSMCI">
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<register-group address-space="base" name="HSMCI" name-in-module="HSMCI" offset="0x40000000"/>
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<signals>
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<signal pad="PA28" function="C" group="MCCDA"/>
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<signal pad="PA29" function="C" group="MCCK"/>
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<signal pad="PA30" function="C" group="MCDA" index="0"/>
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<signal pad="PA31" function="C" group="MCDA" index="1"/>
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<signal pad="PA26" function="C" group="MCDA" index="2"/>
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<signal pad="PA27" function="C" group="MCDA" index="3"/>
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</signals>
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</instance>
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</module>
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<module name="MATRIX" version="6499A">
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<instance name="MATRIX">
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<register-group address-space="base" name="MATRIX" name-in-module="MATRIX" offset="0x400E0200"/>
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</instance>
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</module>
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<module name="PIO" version="11004F">
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<instance name="PIOA">
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<register-group address-space="base" name="PIOA" name-in-module="PIO" offset="0x400E0E00"/>
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<signals>
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<signal pad="PA23" function="D" group="PIODCCLK"/>
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<signal pad="PA15" function="D" group="PIODCEN" index="1"/>
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<signal pad="PA16" function="D" group="PIODCEN" index="2"/>
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<signal pad="PA24" function="D" group="PIODC" index="0"/>
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<signal pad="PA25" function="D" group="PIODC" index="1"/>
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<signal pad="PA26" function="D" group="PIODC" index="2"/>
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<signal pad="PA27" function="D" group="PIODC" index="3"/>
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<signal pad="PA28" function="D" group="PIODC" index="4"/>
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<signal pad="PA29" function="D" group="PIODC" index="5"/>
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<signal pad="PA30" function="D" group="PIODC" index="6"/>
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<signal pad="PA31" function="D" group="PIODC" index="7"/>
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</signals>
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</instance>
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<instance name="PIOB">
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<register-group address-space="base" name="PIOB" name-in-module="PIO" offset="0x400E1000"/>
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</instance>
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</module>
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<module name="PMC" version="11116D">
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<instance name="PMC">
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<register-group address-space="base" name="PMC" name-in-module="PMC" offset="0x400E0400"/>
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<signals>
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<signal pad="PA6" function="B" group="PCK" index="0"/>
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<signal pad="PB13" function="B" group="PCK" index="0"/>
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<signal pad="PA17" function="B" group="PCK" index="1"/>
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<signal pad="PA21" function="B" group="PCK" index="1"/>
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<signal pad="PA18" function="B" group="PCK" index="2"/>
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<signal pad="PA31" function="B" group="PCK" index="2"/>
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<signal pad="PB3" function="B" group="PCK" index="2"/>
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</signals>
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</instance>
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</module>
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<module name="PWM" version="6343H">
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<instance name="PWM">
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<register-group address-space="base" name="PWM" name-in-module="PWM" offset="0x40020000"/>
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<signals>
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<signal pad="PA9" function="C" group="PWMFI" index="0"/>
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<signal pad="PA0" function="A" group="PWMH" index="0"/>
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<signal pad="PA11" function="B" group="PWMH" index="0"/>
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<signal pad="PA23" function="B" group="PWMH" index="0"/>
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<signal pad="PB0" function="A" group="PWMH" index="0"/>
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<signal pad="PC18" function="B" group="PWMH" index="0"/>
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<signal pad="PA1" function="A" group="PWMH" index="1"/>
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<signal pad="PA12" function="B" group="PWMH" index="1"/>
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<signal pad="PA24" function="B" group="PWMH" index="1"/>
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<signal pad="PB1" function="A" group="PWMH" index="1"/>
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<signal pad="PC19" function="B" group="PWMH" index="1"/>
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<signal pad="PA2" function="A" group="PWMH" index="2"/>
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<signal pad="PA13" function="B" group="PWMH" index="2"/>
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<signal pad="PA25" function="B" group="PWMH" index="2"/>
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<signal pad="PB4" function="B" group="PWMH" index="2"/>
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<signal pad="PC20" function="B" group="PWMH" index="2"/>
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<signal pad="PA7" function="B" group="PWMH" index="3"/>
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<signal pad="PA14" function="B" group="PWMH" index="3"/>
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<signal pad="PA17" function="C" group="PWMH" index="3"/>
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<signal pad="PB14" function="B" group="PWMH" index="3"/>
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<signal pad="PC21" function="B" group="PWMH" index="3"/>
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<signal pad="PA19" function="B" group="PWML" index="0"/>
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<signal pad="PB5" function="B" group="PWML" index="0"/>
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<signal pad="PC0" function="B" group="PWML" index="0"/>
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<signal pad="PC13" function="B" group="PWML" index="0"/>
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<signal pad="PA20" function="B" group="PWML" index="1"/>
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<signal pad="PB12" function="A" group="PWML" index="1"/>
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<signal pad="PC1" function="B" group="PWML" index="1"/>
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<signal pad="PC15" function="B" group="PWML" index="1"/>
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<signal pad="PA16" function="C" group="PWML" index="2"/>
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<signal pad="PA30" function="A" group="PWML" index="2"/>
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<signal pad="PB13" function="A" group="PWML" index="2"/>
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<signal pad="PC2" function="B" group="PWML" index="2"/>
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<signal pad="PA15" function="C" group="PWML" index="3"/>
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<signal pad="PC3" function="B" group="PWML" index="3"/>
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<signal pad="PC22" function="B" group="PWML" index="3"/>
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</signals>
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</instance>
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</module>
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<module name="RSTC" version="11009C">
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<instance name="RSTC">
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<register-group address-space="base" name="RSTC" name-in-module="RSTC" offset="0x400E1400"/>
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</instance>
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</module>
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<module name="RTC" version="6056K">
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<instance name="RTC">
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<register-group address-space="base" name="RTC" name-in-module="RTC" offset="0x400E1460"/>
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</instance>
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</module>
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<module name="RTT" version="6081F">
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<instance name="RTT">
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<register-group address-space="base" name="RTT" name-in-module="RTT" offset="0x400E1430"/>
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</instance>
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</module>
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<module name="SPI" version="6088R">
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<instance name="SPI">
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<register-group address-space="base" name="SPI" name-in-module="SPI" offset="0x40008000"/>
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<signals>
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<signal pad="PA12" function="A" group="MISO"/>
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<signal pad="PA13" function="A" group="MOSI"/>
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<signal pad="PA11" function="A" group="NPCS" index="0"/>
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<signal pad="PA9" function="B" group="NPCS" index="1"/>
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<signal pad="PA31" function="A" group="NPCS" index="1"/>
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<signal pad="PB14" function="A" group="NPCS" index="1"/>
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<signal pad="PC4" function="B" group="NPCS" index="1"/>
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<signal pad="PA10" function="B" group="NPCS" index="2"/>
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<signal pad="PA30" function="B" group="NPCS" index="2"/>
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<signal pad="PB2" function="B" group="NPCS" index="2"/>
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<signal pad="PA3" function="B" group="NPCS" index="3"/>
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<signal pad="PA5" function="B" group="NPCS" index="3"/>
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<signal pad="PA22" function="B" group="NPCS" index="3"/>
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<signal pad="PA14" function="A" group="SPCK"/>
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</signals>
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</instance>
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</module>
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<module name="SSC" version="6078J">
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<instance name="SSC">
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<register-group address-space="base" name="SSC" name-in-module="SSC" offset="0x40004000"/>
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<signals>
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<signal pad="PA18" function="A" group="RD"/>
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<signal pad="PA20" function="A" group="RF"/>
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<signal pad="PA19" function="A" group="RK"/>
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<signal pad="PA17" function="A" group="TD"/>
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<signal pad="PA15" function="A" group="TF"/>
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<signal pad="PA16" function="A" group="TK"/>
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</signals>
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</instance>
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</module>
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<module name="SUPC" version="6452M">
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<instance name="SUPC">
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<register-group address-space="base" name="SUPC" name-in-module="SUPC" offset="0x400E1410"/>
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</instance>
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</module>
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<module name="TC" version="6082Q">
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<instance name="TC0">
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<register-group address-space="base" name="TC0" name-in-module="TC" offset="0x40010000"/>
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<signals>
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<signal pad="PA4" function="B" group="TCLK" index="0"/>
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|
<signal pad="PA28" function="B" group="TCLK" index="1"/>
|
||
|
|
<signal pad="PA29" function="B" group="TCLK" index="2"/>
|
||
|
|
<signal pad="PA0" function="B" group="TIOA" index="0"/>
|
||
|
|
<signal pad="PA15" function="B" group="TIOA" index="1"/>
|
||
|
|
<signal pad="PA26" function="B" group="TIOA" index="2"/>
|
||
|
|
<signal pad="PA1" function="B" group="TIOB" index="0"/>
|
||
|
|
<signal pad="PA16" function="B" group="TIOB" index="1"/>
|
||
|
|
<signal pad="PA27" function="B" group="TIOB" index="2"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="TWI" version="6212L">
|
||
|
|
<instance name="TWI0">
|
||
|
|
<register-group address-space="base" name="TWI0" name-in-module="TWI" offset="0x40018000"/>
|
||
|
|
<signals>
|
||
|
|
<signal pad="PA4" function="A" group="TWCK" index="0"/>
|
||
|
|
<signal pad="PA3" function="A" group="TWD" index="0"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
<instance name="TWI1">
|
||
|
|
<register-group address-space="base" name="TWI1" name-in-module="TWI" offset="0x4001C000"/>
|
||
|
|
<signals>
|
||
|
|
<signal pad="PB5" function="A" group="TWCK" index="1"/>
|
||
|
|
<signal pad="PB4" function="A" group="TWD" index="1"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="UART" version="6418E">
|
||
|
|
<instance name="UART0">
|
||
|
|
<register-group address-space="base" name="UART0" name-in-module="UART" offset="0x400E0600"/>
|
||
|
|
<signals>
|
||
|
|
<signal pad="PA9" function="A" group="URXD" index="0"/>
|
||
|
|
<signal pad="PA10" function="A" group="UTXD" index="0"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
<instance name="UART1">
|
||
|
|
<register-group address-space="base" name="UART1" name-in-module="UART" offset="0x400E0800"/>
|
||
|
|
<signals>
|
||
|
|
<signal pad="PB2" function="A" group="URXD" index="1"/>
|
||
|
|
<signal pad="PB3" function="A" group="UTXD" index="1"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="UDP" version="6083V">
|
||
|
|
<instance name="UDP">
|
||
|
|
<register-group address-space="base" name="UDP" name-in-module="UDP" offset="0x40034000"/>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="USART" version="6089Y">
|
||
|
|
<instance name="USART0">
|
||
|
|
<register-group address-space="base" name="USART0" name-in-module="USART" offset="0x40024000"/>
|
||
|
|
<signals>
|
||
|
|
<signal pad="PA8" function="A" group="CTS" index="0"/>
|
||
|
|
<signal pad="PA7" function="A" group="RTS" index="0"/>
|
||
|
|
<signal pad="PA5" function="A" group="RXD" index="0"/>
|
||
|
|
<signal pad="PA2" function="B" group="SCK" index="0"/>
|
||
|
|
<signal pad="PA6" function="A" group="TXD" index="0"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
<instance name="USART1">
|
||
|
|
<register-group address-space="base" name="USART1" name-in-module="USART" offset="0x40028000"/>
|
||
|
|
<signals>
|
||
|
|
<signal pad="PA25" function="A" group="CTS" index="1"/>
|
||
|
|
<signal pad="PA26" function="A" group="DCD" index="1"/>
|
||
|
|
<signal pad="PA28" function="A" group="DSR" index="1"/>
|
||
|
|
<signal pad="PA27" function="A" group="DTR" index="1"/>
|
||
|
|
<signal pad="PA29" function="A" group="RI" index="1"/>
|
||
|
|
<signal pad="PA24" function="A" group="RTS" index="1"/>
|
||
|
|
<signal pad="PA21" function="A" group="RXD" index="1"/>
|
||
|
|
<signal pad="PA23" function="A" group="SCK" index="1"/>
|
||
|
|
<signal pad="PA22" function="A" group="TXD" index="1"/>
|
||
|
|
</signals>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="WDT" version="6080B">
|
||
|
|
<instance name="WDT">
|
||
|
|
<register-group address-space="base" name="WDT" name-in-module="WDT" offset="0x400E1450"/>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="FUSES" version="1">
|
||
|
|
<instance name="FUSES">
|
||
|
|
<register-group address-space="fuses" name="GPNVMBITS" name-in-module="GPNVMBITS" offset="0"/>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="LOCKBIT" version="1">
|
||
|
|
<instance name="LOCKBIT">
|
||
|
|
<register-group address-space="lockbits" name="LOCKBIT" name-in-module="LOCKBIT" offset="0"/>
|
||
|
|
</instance>
|
||
|
|
</module>
|
||
|
|
<module name="SystemControl">
|
||
|
|
<instance name="SystemControl">
|
||
|
|
<register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
|
||
|
|
</instance>
|
||
|
|
</module><module name="SysTick">
|
||
|
|
<instance name="SysTick">
|
||
|
|
<register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
|
||
|
|
</instance>
|
||
|
|
</module><module name="NVIC">
|
||
|
|
<instance name="NVIC">
|
||
|
|
<register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
|
||
|
|
</instance>
|
||
|
|
</module></peripherals>
|
||
|
|
<interrupts>
|
||
|
|
<interrupt index="-14" name="NonMaskableInt_IRQn" caption="Non Maskable Interrupt"/>
|
||
|
|
<interrupt index="-12" name="MemoryManagement_IRQn" caption="Cortex-M3 Memory Management Interrupt"/>
|
||
|
|
<interrupt index="-11" name="BusFault_IRQn" caption="Cortex-M3 Bus Fault Interrupt"/>
|
||
|
|
<interrupt index="-10" name="UsageFault_IRQn" caption="Cortex-M3 Usage Fault Interrupt"/>
|
||
|
|
<interrupt index="-5" name="SVCall_IRQn" caption="Cortex-M3 SV Call Interrupt"/>
|
||
|
|
<interrupt index="-4" name="DebugMonitor_IRQn" caption="Cortex-M3 Debug Monitor Interrupt"/>
|
||
|
|
<interrupt index="-2" name="PendSV_IRQn" caption="Cortex-M3 Pend SV Interrupt"/>
|
||
|
|
<interrupt index="-1" name="SysTick_IRQn" caption="Cortex-M3 System Tick Interrupt"/>
|
||
|
|
<interrupt index="0" module-instance="SYSC" name="SUPC" caption="Supply Controller"/>
|
||
|
|
<interrupt index="1" module-instance="SYSC" name="RSTC" caption="Reset Controller"/>
|
||
|
|
<interrupt index="2" module-instance="SYSC" name="RTC" caption="Real Time Clock"/>
|
||
|
|
<interrupt index="3" module-instance="SYSC" name="RTT" caption="Real Time Timer"/>
|
||
|
|
<interrupt index="4" module-instance="SYSC" name="WDT" caption="Watchdog Timer"/>
|
||
|
|
<interrupt index="5" module-instance="PMC" name="PMC" caption="Power Management Controller"/>
|
||
|
|
<interrupt index="6" module-instance="EFC" name="EFC" caption="Enhanced Embedded Flash Controller"/>
|
||
|
|
<interrupt index="8" module-instance="UART0" name="UART0" caption="UART 0"/>
|
||
|
|
<interrupt index="9" module-instance="UART1" name="UART1" caption="UART 1"/>
|
||
|
|
<interrupt index="11" module-instance="PIOA" name="PIOA" caption="Parallel I/O Controller A"/>
|
||
|
|
<interrupt index="12" module-instance="PIOB" name="PIOB" caption="Parallel I/O Controller B"/>
|
||
|
|
<interrupt index="14" module-instance="USART0" name="USART0" caption="USART 0"/>
|
||
|
|
<interrupt index="15" module-instance="USART1" name="USART1" caption="USART 1"/>
|
||
|
|
<interrupt index="18" module-instance="HSMCI" name="HSMCI" caption="Multimedia Card Interface"/>
|
||
|
|
<interrupt index="19" module-instance="TWI0" name="TWI0" caption="Two Wire Interface 0"/>
|
||
|
|
<interrupt index="20" module-instance="TWI1" name="TWI1" caption="Two Wire Interface 1"/>
|
||
|
|
<interrupt index="21" module-instance="SPI" name="SPI" caption="Serial Peripheral Interface"/>
|
||
|
|
<interrupt index="22" module-instance="SSC" name="SSC" caption="Synchronous Serial Controler"/>
|
||
|
|
<interrupt index="23" module-instance="TC0" name="TC0" caption="Timer/Counter 0"/>
|
||
|
|
<interrupt index="24" module-instance="TC0" name="TC1" caption="Timer/Counter 1"/>
|
||
|
|
<interrupt index="25" module-instance="TC0" name="TC2" caption="Timer/Counter 2"/>
|
||
|
|
<interrupt index="29" module-instance="ADC" name="ADC" caption="Analog To Digital Converter"/>
|
||
|
|
<interrupt index="30" module-instance="DACC" name="DACC" caption="Digital To Analog Converter"/>
|
||
|
|
<interrupt index="31" module-instance="PWM" name="PWM" caption="Pulse Width Modulation"/>
|
||
|
|
<interrupt index="32" module-instance="CRCCU" name="CRCCU" caption="CRC Calculation Unit"/>
|
||
|
|
<interrupt index="33" module-instance="ACC" name="ACC" caption="Analog Comparator"/>
|
||
|
|
<interrupt index="34" module-instance="UDP" name="UDP" caption="USB Device Port"/>
|
||
|
|
</interrupts>
|
||
|
|
<interfaces>
|
||
|
|
<interface type="samjtag" name="JTAG"/>
|
||
|
|
<interface type="swd" name="SWD"/>
|
||
|
|
</interfaces>
|
||
|
|
<property-groups>
|
||
|
|
<property-group name="SIGNATURES">
|
||
|
|
<property name="JTAGID" value="0x05B2D03F"/>
|
||
|
|
<property name="CHIPID_CIDR" value="0x289B0A60"/>
|
||
|
|
<property name="CHIPID_EXID" value="0x0"/>
|
||
|
|
</property-group>
|
||
|
|
</property-groups>
|
||
|
|
<parameters>
|
||
|
|
<param name="__CM3_REV" value="0x0200"/>
|
||
|
|
<param name="__MPU_PRESENT" value="1"/>
|
||
|
|
<param name="__FPU_PRESENT" value="0"/>
|
||
|
|
<param name="__NVIC_PRIO_BITS" value="4"/>
|
||
|
|
<param name="__Vendor_SysTickConfig" value="0"/>
|
||
|
|
</parameters>
|
||
|
|
</device>
|
||
|
|
</devices>
|
||
|
|
<modules>
|
||
|
|
<module caption="Analog Comparator Controller" name="ACC" version="6490C">
|
||
|
|
<register-group name="ACC">
|
||
|
|
<register caption="Control Register" name="ACC_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="SoftWare ReSeT" mask="0x00000001" name="SWRST"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="ACC_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="SELection for MINUS comparator input" mask="0x00000007" name="SELMINUS" values="ACC_MR__SELMINUS"/>
|
||
|
|
<bitfield caption="SELection for PLUS comparator input" mask="0x00000070" name="SELPLUS" values="ACC_MR__SELPLUS"/>
|
||
|
|
<bitfield caption="Analog Comparator ENable" mask="0x00000100" name="ACEN" values="ACC_MR__ACEN"/>
|
||
|
|
<bitfield caption="EDGE TYPe" mask="0x00000600" name="EDGETYP" values="ACC_MR__EDGETYP"/>
|
||
|
|
<bitfield caption="INVert comparator output" mask="0x00001000" name="INV" values="ACC_MR__INV"/>
|
||
|
|
<bitfield caption="SELection of Fault Source" mask="0x00002000" name="SELFS" values="ACC_MR__SELFS"/>
|
||
|
|
<bitfield caption="Fault Enable" mask="0x00004000" name="FE" values="ACC_MR__FE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="ACC_IER" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison Edge" mask="0x00000001" name="CE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="ACC_IDR" offset="0x28" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison Edge" mask="0x00000001" name="CE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="ACC_IMR" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="Comparison Edge" mask="0x00000001" name="CE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Status Register" name="ACC_ISR" offset="0x30" rw="R" size="4">
|
||
|
|
<bitfield caption="Comparison Edge" mask="0x00000001" name="CE"/>
|
||
|
|
<bitfield caption="Synchronized Comparator Output" mask="0x00000002" name="SCO"/>
|
||
|
|
<bitfield caption="" mask="0x80000000" name="MASK"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Analog Control Register" name="ACC_ACR" offset="0x94" rw="RW" size="4">
|
||
|
|
<bitfield caption="Current SELection" mask="0x00000001" name="ISEL" values="ACC_ACR__ISEL"/>
|
||
|
|
<bitfield caption="HYSTeresis selection" mask="0x00000006" name="HYST"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="ACC_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="ACC_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write PROTection ERRor" mask="0x00000001" name="WPROTERR"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="ACC_MR__SELMINUS">
|
||
|
|
<value caption="SelectTS" name="TS" value="0x0"/>
|
||
|
|
<value caption="Select ADVREF" name="ADVREF" value="0x1"/>
|
||
|
|
<value caption="Select DAC0" name="DAC0" value="0x2"/>
|
||
|
|
<value caption="Select DAC1" name="DAC1" value="0x3"/>
|
||
|
|
<value caption="Select AD0" name="AD0" value="0x4"/>
|
||
|
|
<value caption="Select AD1" name="AD1" value="0x5"/>
|
||
|
|
<value caption="Select AD2" name="AD2" value="0x6"/>
|
||
|
|
<value caption="Select AD3" name="AD3" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_MR__SELPLUS">
|
||
|
|
<value caption="Select AD0" name="AD0" value="0x0"/>
|
||
|
|
<value caption="Select AD1" name="AD1" value="0x1"/>
|
||
|
|
<value caption="Select AD2" name="AD2" value="0x2"/>
|
||
|
|
<value caption="Select AD3" name="AD3" value="0x3"/>
|
||
|
|
<value caption="Select AD4" name="AD4" value="0x4"/>
|
||
|
|
<value caption="Select AD5" name="AD5" value="0x5"/>
|
||
|
|
<value caption="Select AD6" name="AD6" value="0x6"/>
|
||
|
|
<value caption="Select AD7" name="AD7" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_MR__ACEN">
|
||
|
|
<value caption="Analog Comparator Disabled." name="DIS" value="0"/>
|
||
|
|
<value caption="Analog Comparator Enabled." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_MR__EDGETYP">
|
||
|
|
<value caption="only rising edge of comparator output" name="RISING" value="0x0"/>
|
||
|
|
<value caption="falling edge of comparator output" name="FALLING" value="0x1"/>
|
||
|
|
<value caption="any edge of comparator output" name="ANY" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_MR__INV">
|
||
|
|
<value caption="Analog Comparator output is directly processed." name="DIS" value="0"/>
|
||
|
|
<value caption="Analog Comparator output is inverted prior to being processed." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_MR__SELFS">
|
||
|
|
<value caption="the CF flag is used to drive the FAULT output." name="CF" value="0"/>
|
||
|
|
<value caption="the output of the Analog Comparator flag is used to drive the FAULT output." name="OUTPUT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_MR__FE">
|
||
|
|
<value caption="the FAULT output is tied to 0." name="DIS" value="0"/>
|
||
|
|
<value caption="the FAULT output is driven by the signal defined by SELFS." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ACC_ACR__ISEL">
|
||
|
|
<value caption="low power option." name="LOPW" value="0"/>
|
||
|
|
<value caption="high speed option." name="HISP" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Analog-to-Digital Converter" name="ADC" version="6489I">
|
||
|
|
<register-group name="ADC">
|
||
|
|
<register caption="Control Register" name="ADC_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Software Reset" mask="0x00000001" name="SWRST"/>
|
||
|
|
<bitfield caption="Start Conversion" mask="0x00000002" name="START"/>
|
||
|
|
<bitfield caption="Automatic Calibration of ADC" mask="0x00000008" name="AUTOCAL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="ADC_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Trigger Enable" mask="0x00000001" name="TRGEN" values="ADC_MR__TRGEN"/>
|
||
|
|
<bitfield caption="Trigger Selection" mask="0x0000000E" name="TRGSEL" values="ADC_MR__TRGSEL"/>
|
||
|
|
<bitfield caption="Resolution" mask="0x00000010" name="LOWRES" values="ADC_MR__LOWRES"/>
|
||
|
|
<bitfield caption="Sleep Mode" mask="0x00000020" name="SLEEP" values="ADC_MR__SLEEP"/>
|
||
|
|
<bitfield caption="Fast Wake Up" mask="0x00000040" name="FWUP" values="ADC_MR__FWUP"/>
|
||
|
|
<bitfield caption="Free Run Mode" mask="0x00000080" name="FREERUN" values="ADC_MR__FREERUN"/>
|
||
|
|
<bitfield caption="Prescaler Rate Selection" mask="0x0000FF00" name="PRESCAL"/>
|
||
|
|
<bitfield caption="Start Up Time" mask="0x000F0000" name="STARTUP" values="ADC_MR__STARTUP"/>
|
||
|
|
<bitfield caption="Analog Settling Time" mask="0x00300000" name="SETTLING" values="ADC_MR__SETTLING"/>
|
||
|
|
<bitfield caption="Analog Change" mask="0x00800000" name="ANACH" values="ADC_MR__ANACH"/>
|
||
|
|
<bitfield caption="Tracking Time" mask="0x0F000000" name="TRACKTIM"/>
|
||
|
|
<bitfield caption="Transfer Period" mask="0x30000000" name="TRANSFER"/>
|
||
|
|
<bitfield caption="Use Sequence Enable" mask="0x80000000" name="USEQ" values="ADC_MR__USEQ"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Sequence Register 1" name="ADC_SEQR1" offset="0x08" rw="RW" size="4">
|
||
|
|
<bitfield caption="User Sequence Number 1" mask="0x00000007" name="USCH1"/>
|
||
|
|
<bitfield caption="User Sequence Number 2" mask="0x00000070" name="USCH2"/>
|
||
|
|
<bitfield caption="User Sequence Number 3" mask="0x00000700" name="USCH3"/>
|
||
|
|
<bitfield caption="User Sequence Number 4" mask="0x00007000" name="USCH4"/>
|
||
|
|
<bitfield caption="User Sequence Number 5" mask="0x00070000" name="USCH5"/>
|
||
|
|
<bitfield caption="User Sequence Number 6" mask="0x00700000" name="USCH6"/>
|
||
|
|
<bitfield caption="User Sequence Number 7" mask="0x07000000" name="USCH7"/>
|
||
|
|
<bitfield caption="User Sequence Number 8" mask="0x70000000" name="USCH8"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Sequence Register 2" name="ADC_SEQR2" offset="0x0C" rw="RW" size="4">
|
||
|
|
<bitfield caption="User Sequence Number 9" mask="0x00000007" name="USCH9"/>
|
||
|
|
<bitfield caption="User Sequence Number 10" mask="0x00000070" name="USCH10"/>
|
||
|
|
<bitfield caption="User Sequence Number 11" mask="0x00000700" name="USCH11"/>
|
||
|
|
<bitfield caption="User Sequence Number 12" mask="0x00007000" name="USCH12"/>
|
||
|
|
<bitfield caption="User Sequence Number 13" mask="0x00070000" name="USCH13"/>
|
||
|
|
<bitfield caption="User Sequence Number 14" mask="0x00700000" name="USCH14"/>
|
||
|
|
<bitfield caption="User Sequence Number 15" mask="0x07000000" name="USCH15"/>
|
||
|
|
<bitfield caption="User Sequence Number 16" mask="0x70000000" name="USCH16"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Enable Register" name="ADC_CHER" offset="0x10" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel 0 Enable" mask="0x00000001" name="CH0"/>
|
||
|
|
<bitfield caption="Channel 1 Enable" mask="0x00000002" name="CH1"/>
|
||
|
|
<bitfield caption="Channel 2 Enable" mask="0x00000004" name="CH2"/>
|
||
|
|
<bitfield caption="Channel 3 Enable" mask="0x00000008" name="CH3"/>
|
||
|
|
<bitfield caption="Channel 4 Enable" mask="0x00000010" name="CH4"/>
|
||
|
|
<bitfield caption="Channel 5 Enable" mask="0x00000020" name="CH5"/>
|
||
|
|
<bitfield caption="Channel 6 Enable" mask="0x00000040" name="CH6"/>
|
||
|
|
<bitfield caption="Channel 7 Enable" mask="0x00000080" name="CH7"/>
|
||
|
|
<bitfield caption="Channel 8 Enable" mask="0x00000100" name="CH8"/>
|
||
|
|
<bitfield caption="Channel 9 Enable" mask="0x00000200" name="CH9"/>
|
||
|
|
<bitfield caption="Channel 10 Enable" mask="0x00000400" name="CH10"/>
|
||
|
|
<bitfield caption="Channel 11 Enable" mask="0x00000800" name="CH11"/>
|
||
|
|
<bitfield caption="Channel 12 Enable" mask="0x00001000" name="CH12"/>
|
||
|
|
<bitfield caption="Channel 13 Enable" mask="0x00002000" name="CH13"/>
|
||
|
|
<bitfield caption="Channel 14 Enable" mask="0x00004000" name="CH14"/>
|
||
|
|
<bitfield caption="Channel 15 Enable" mask="0x00008000" name="CH15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Disable Register" name="ADC_CHDR" offset="0x14" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel 0 Disable" mask="0x00000001" name="CH0"/>
|
||
|
|
<bitfield caption="Channel 1 Disable" mask="0x00000002" name="CH1"/>
|
||
|
|
<bitfield caption="Channel 2 Disable" mask="0x00000004" name="CH2"/>
|
||
|
|
<bitfield caption="Channel 3 Disable" mask="0x00000008" name="CH3"/>
|
||
|
|
<bitfield caption="Channel 4 Disable" mask="0x00000010" name="CH4"/>
|
||
|
|
<bitfield caption="Channel 5 Disable" mask="0x00000020" name="CH5"/>
|
||
|
|
<bitfield caption="Channel 6 Disable" mask="0x00000040" name="CH6"/>
|
||
|
|
<bitfield caption="Channel 7 Disable" mask="0x00000080" name="CH7"/>
|
||
|
|
<bitfield caption="Channel 8 Disable" mask="0x00000100" name="CH8"/>
|
||
|
|
<bitfield caption="Channel 9 Disable" mask="0x00000200" name="CH9"/>
|
||
|
|
<bitfield caption="Channel 10 Disable" mask="0x00000400" name="CH10"/>
|
||
|
|
<bitfield caption="Channel 11 Disable" mask="0x00000800" name="CH11"/>
|
||
|
|
<bitfield caption="Channel 12 Disable" mask="0x00001000" name="CH12"/>
|
||
|
|
<bitfield caption="Channel 13 Disable" mask="0x00002000" name="CH13"/>
|
||
|
|
<bitfield caption="Channel 14 Disable" mask="0x00004000" name="CH14"/>
|
||
|
|
<bitfield caption="Channel 15 Disable" mask="0x00008000" name="CH15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Status Register" name="ADC_CHSR" offset="0x18" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel 0 Status" mask="0x00000001" name="CH0"/>
|
||
|
|
<bitfield caption="Channel 1 Status" mask="0x00000002" name="CH1"/>
|
||
|
|
<bitfield caption="Channel 2 Status" mask="0x00000004" name="CH2"/>
|
||
|
|
<bitfield caption="Channel 3 Status" mask="0x00000008" name="CH3"/>
|
||
|
|
<bitfield caption="Channel 4 Status" mask="0x00000010" name="CH4"/>
|
||
|
|
<bitfield caption="Channel 5 Status" mask="0x00000020" name="CH5"/>
|
||
|
|
<bitfield caption="Channel 6 Status" mask="0x00000040" name="CH6"/>
|
||
|
|
<bitfield caption="Channel 7 Status" mask="0x00000080" name="CH7"/>
|
||
|
|
<bitfield caption="Channel 8 Status" mask="0x00000100" name="CH8"/>
|
||
|
|
<bitfield caption="Channel 9 Status" mask="0x00000200" name="CH9"/>
|
||
|
|
<bitfield caption="Channel 10 Status" mask="0x00000400" name="CH10"/>
|
||
|
|
<bitfield caption="Channel 11 Status" mask="0x00000800" name="CH11"/>
|
||
|
|
<bitfield caption="Channel 12 Status" mask="0x00001000" name="CH12"/>
|
||
|
|
<bitfield caption="Channel 13 Status" mask="0x00002000" name="CH13"/>
|
||
|
|
<bitfield caption="Channel 14 Status" mask="0x00004000" name="CH14"/>
|
||
|
|
<bitfield caption="Channel 15 Status" mask="0x00008000" name="CH15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Last Converted Data Register" name="ADC_LCDR" offset="0x20" rw="R" size="4">
|
||
|
|
<bitfield caption="Last Data Converted" mask="0x00000FFF" name="LDATA"/>
|
||
|
|
<bitfield caption="Channel Number" mask="0x0000F000" name="CHNB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="ADC_IER" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 0" mask="0x00000001" name="EOC0"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 1" mask="0x00000002" name="EOC1"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 2" mask="0x00000004" name="EOC2"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 3" mask="0x00000008" name="EOC3"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 4" mask="0x00000010" name="EOC4"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 5" mask="0x00000020" name="EOC5"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 6" mask="0x00000040" name="EOC6"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 7" mask="0x00000080" name="EOC7"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 8" mask="0x00000100" name="EOC8"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 9" mask="0x00000200" name="EOC9"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 10" mask="0x00000400" name="EOC10"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 11" mask="0x00000800" name="EOC11"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 12" mask="0x00001000" name="EOC12"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 13" mask="0x00002000" name="EOC13"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 14" mask="0x00004000" name="EOC14"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable 15" mask="0x00008000" name="EOC15"/>
|
||
|
|
<bitfield caption="End of Calibration Sequence" mask="0x00800000" name="EOCAL"/>
|
||
|
|
<bitfield caption="Data Ready Interrupt Enable" mask="0x01000000" name="DRDY"/>
|
||
|
|
<bitfield caption="General Overrun Error Interrupt Enable" mask="0x02000000" name="GOVRE"/>
|
||
|
|
<bitfield caption="Comparison Event Interrupt Enable" mask="0x04000000" name="COMPE"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Enable" mask="0x08000000" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Enable" mask="0x10000000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="ADC_IDR" offset="0x28" rw="W" size="4">
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 0" mask="0x00000001" name="EOC0"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 1" mask="0x00000002" name="EOC1"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 2" mask="0x00000004" name="EOC2"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 3" mask="0x00000008" name="EOC3"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 4" mask="0x00000010" name="EOC4"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 5" mask="0x00000020" name="EOC5"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 6" mask="0x00000040" name="EOC6"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 7" mask="0x00000080" name="EOC7"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 8" mask="0x00000100" name="EOC8"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 9" mask="0x00000200" name="EOC9"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 10" mask="0x00000400" name="EOC10"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 11" mask="0x00000800" name="EOC11"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 12" mask="0x00001000" name="EOC12"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 13" mask="0x00002000" name="EOC13"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 14" mask="0x00004000" name="EOC14"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable 15" mask="0x00008000" name="EOC15"/>
|
||
|
|
<bitfield caption="End of Calibration Sequence" mask="0x00800000" name="EOCAL"/>
|
||
|
|
<bitfield caption="Data Ready Interrupt Disable" mask="0x01000000" name="DRDY"/>
|
||
|
|
<bitfield caption="General Overrun Error Interrupt Disable" mask="0x02000000" name="GOVRE"/>
|
||
|
|
<bitfield caption="Comparison Event Interrupt Disable" mask="0x04000000" name="COMPE"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Disable" mask="0x08000000" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Disable" mask="0x10000000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="ADC_IMR" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 0" mask="0x00000001" name="EOC0"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 1" mask="0x00000002" name="EOC1"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 2" mask="0x00000004" name="EOC2"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 3" mask="0x00000008" name="EOC3"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 4" mask="0x00000010" name="EOC4"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 5" mask="0x00000020" name="EOC5"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 6" mask="0x00000040" name="EOC6"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 7" mask="0x00000080" name="EOC7"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 8" mask="0x00000100" name="EOC8"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 9" mask="0x00000200" name="EOC9"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 10" mask="0x00000400" name="EOC10"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 11" mask="0x00000800" name="EOC11"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 12" mask="0x00001000" name="EOC12"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 13" mask="0x00002000" name="EOC13"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 14" mask="0x00004000" name="EOC14"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask 15" mask="0x00008000" name="EOC15"/>
|
||
|
|
<bitfield caption="End of Calibration Sequence" mask="0x00800000" name="EOCAL"/>
|
||
|
|
<bitfield caption="Data Ready Interrupt Mask" mask="0x01000000" name="DRDY"/>
|
||
|
|
<bitfield caption="General Overrun Error Interrupt Mask" mask="0x02000000" name="GOVRE"/>
|
||
|
|
<bitfield caption="Comparison Event Interrupt Mask" mask="0x04000000" name="COMPE"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Mask" mask="0x08000000" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Mask" mask="0x10000000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Status Register" name="ADC_ISR" offset="0x30" rw="R" size="4">
|
||
|
|
<bitfield caption="End of Conversion 0" mask="0x00000001" name="EOC0"/>
|
||
|
|
<bitfield caption="End of Conversion 1" mask="0x00000002" name="EOC1"/>
|
||
|
|
<bitfield caption="End of Conversion 2" mask="0x00000004" name="EOC2"/>
|
||
|
|
<bitfield caption="End of Conversion 3" mask="0x00000008" name="EOC3"/>
|
||
|
|
<bitfield caption="End of Conversion 4" mask="0x00000010" name="EOC4"/>
|
||
|
|
<bitfield caption="End of Conversion 5" mask="0x00000020" name="EOC5"/>
|
||
|
|
<bitfield caption="End of Conversion 6" mask="0x00000040" name="EOC6"/>
|
||
|
|
<bitfield caption="End of Conversion 7" mask="0x00000080" name="EOC7"/>
|
||
|
|
<bitfield caption="End of Conversion 8" mask="0x00000100" name="EOC8"/>
|
||
|
|
<bitfield caption="End of Conversion 9" mask="0x00000200" name="EOC9"/>
|
||
|
|
<bitfield caption="End of Conversion 10" mask="0x00000400" name="EOC10"/>
|
||
|
|
<bitfield caption="End of Conversion 11" mask="0x00000800" name="EOC11"/>
|
||
|
|
<bitfield caption="End of Conversion 12" mask="0x00001000" name="EOC12"/>
|
||
|
|
<bitfield caption="End of Conversion 13" mask="0x00002000" name="EOC13"/>
|
||
|
|
<bitfield caption="End of Conversion 14" mask="0x00004000" name="EOC14"/>
|
||
|
|
<bitfield caption="End of Conversion 15" mask="0x00008000" name="EOC15"/>
|
||
|
|
<bitfield caption="End of Calibration Sequence" mask="0x00800000" name="EOCAL"/>
|
||
|
|
<bitfield caption="Data Ready" mask="0x01000000" name="DRDY"/>
|
||
|
|
<bitfield caption="General Overrun Error" mask="0x02000000" name="GOVRE"/>
|
||
|
|
<bitfield caption="Comparison Error" mask="0x04000000" name="COMPE"/>
|
||
|
|
<bitfield caption="End of RX Buffer" mask="0x08000000" name="ENDRX"/>
|
||
|
|
<bitfield caption="RX Buffer Full" mask="0x10000000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Overrun Status Register" name="ADC_OVER" offset="0x3C" rw="R" size="4">
|
||
|
|
<bitfield caption="Overrun Error 0" mask="0x00000001" name="OVRE0"/>
|
||
|
|
<bitfield caption="Overrun Error 1" mask="0x00000002" name="OVRE1"/>
|
||
|
|
<bitfield caption="Overrun Error 2" mask="0x00000004" name="OVRE2"/>
|
||
|
|
<bitfield caption="Overrun Error 3" mask="0x00000008" name="OVRE3"/>
|
||
|
|
<bitfield caption="Overrun Error 4" mask="0x00000010" name="OVRE4"/>
|
||
|
|
<bitfield caption="Overrun Error 5" mask="0x00000020" name="OVRE5"/>
|
||
|
|
<bitfield caption="Overrun Error 6" mask="0x00000040" name="OVRE6"/>
|
||
|
|
<bitfield caption="Overrun Error 7" mask="0x00000080" name="OVRE7"/>
|
||
|
|
<bitfield caption="Overrun Error 8" mask="0x00000100" name="OVRE8"/>
|
||
|
|
<bitfield caption="Overrun Error 9" mask="0x00000200" name="OVRE9"/>
|
||
|
|
<bitfield caption="Overrun Error 10" mask="0x00000400" name="OVRE10"/>
|
||
|
|
<bitfield caption="Overrun Error 11" mask="0x00000800" name="OVRE11"/>
|
||
|
|
<bitfield caption="Overrun Error 12" mask="0x00001000" name="OVRE12"/>
|
||
|
|
<bitfield caption="Overrun Error 13" mask="0x00002000" name="OVRE13"/>
|
||
|
|
<bitfield caption="Overrun Error 14" mask="0x00004000" name="OVRE14"/>
|
||
|
|
<bitfield caption="Overrun Error 15" mask="0x00008000" name="OVRE15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Extended Mode Register" name="ADC_EMR" offset="0x40" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison Mode" mask="0x00000003" name="CMPMODE" values="ADC_EMR__CMPMODE"/>
|
||
|
|
<bitfield caption="Comparison Selected Channel" mask="0x000000F0" name="CMPSEL"/>
|
||
|
|
<bitfield caption="Compare All Channels" mask="0x00000200" name="CMPALL"/>
|
||
|
|
<bitfield caption="Compare Event Filtering" mask="0x00003000" name="CMPFILTER"/>
|
||
|
|
<bitfield caption="TAG of ADC_LDCR register" mask="0x01000000" name="TAG"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Compare Window Register" name="ADC_CWR" offset="0x44" rw="RW" size="4">
|
||
|
|
<bitfield caption="Low Threshold" mask="0x00000FFF" name="LOWTHRES"/>
|
||
|
|
<bitfield caption="High Threshold" mask="0x0FFF0000" name="HIGHTHRES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Gain Register" name="ADC_CGR" offset="0x48" rw="RW" size="4">
|
||
|
|
<bitfield caption="Gain for channel 0" mask="0x00000003" name="GAIN0"/>
|
||
|
|
<bitfield caption="Gain for channel 1" mask="0x0000000C" name="GAIN1"/>
|
||
|
|
<bitfield caption="Gain for channel 2" mask="0x00000030" name="GAIN2"/>
|
||
|
|
<bitfield caption="Gain for channel 3" mask="0x000000C0" name="GAIN3"/>
|
||
|
|
<bitfield caption="Gain for channel 4" mask="0x00000300" name="GAIN4"/>
|
||
|
|
<bitfield caption="Gain for channel 5" mask="0x00000C00" name="GAIN5"/>
|
||
|
|
<bitfield caption="Gain for channel 6" mask="0x00003000" name="GAIN6"/>
|
||
|
|
<bitfield caption="Gain for channel 7" mask="0x0000C000" name="GAIN7"/>
|
||
|
|
<bitfield caption="Gain for channel 8" mask="0x00030000" name="GAIN8"/>
|
||
|
|
<bitfield caption="Gain for channel 9" mask="0x000C0000" name="GAIN9"/>
|
||
|
|
<bitfield caption="Gain for channel 10" mask="0x00300000" name="GAIN10"/>
|
||
|
|
<bitfield caption="Gain for channel 11" mask="0x00C00000" name="GAIN11"/>
|
||
|
|
<bitfield caption="Gain for channel 12" mask="0x03000000" name="GAIN12"/>
|
||
|
|
<bitfield caption="Gain for channel 13" mask="0x0C000000" name="GAIN13"/>
|
||
|
|
<bitfield caption="Gain for channel 14" mask="0x30000000" name="GAIN14"/>
|
||
|
|
<bitfield caption="Gain for channel 15" mask="0xC0000000" name="GAIN15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Offset Register" name="ADC_COR" offset="0x4C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Offset for channel 0" mask="0x00000001" name="OFF0"/>
|
||
|
|
<bitfield caption="Offset for channel 1" mask="0x00000002" name="OFF1"/>
|
||
|
|
<bitfield caption="Offset for channel 2" mask="0x00000004" name="OFF2"/>
|
||
|
|
<bitfield caption="Offset for channel 3" mask="0x00000008" name="OFF3"/>
|
||
|
|
<bitfield caption="Offset for channel 4" mask="0x00000010" name="OFF4"/>
|
||
|
|
<bitfield caption="Offset for channel 5" mask="0x00000020" name="OFF5"/>
|
||
|
|
<bitfield caption="Offset for channel 6" mask="0x00000040" name="OFF6"/>
|
||
|
|
<bitfield caption="Offset for channel 7" mask="0x00000080" name="OFF7"/>
|
||
|
|
<bitfield caption="Offset for channel 8" mask="0x00000100" name="OFF8"/>
|
||
|
|
<bitfield caption="Offset for channel 9" mask="0x00000200" name="OFF9"/>
|
||
|
|
<bitfield caption="Offset for channel 10" mask="0x00000400" name="OFF10"/>
|
||
|
|
<bitfield caption="Offset for channel 11" mask="0x00000800" name="OFF11"/>
|
||
|
|
<bitfield caption="Offset for channel 12" mask="0x00001000" name="OFF12"/>
|
||
|
|
<bitfield caption="Offset for channel 13" mask="0x00002000" name="OFF13"/>
|
||
|
|
<bitfield caption="Offset for channel 14" mask="0x00004000" name="OFF14"/>
|
||
|
|
<bitfield caption="Offset for channel 15" mask="0x00008000" name="OFF15"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 0" mask="0x00010000" name="DIFF0"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 1" mask="0x00020000" name="DIFF1"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 2" mask="0x00040000" name="DIFF2"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 3" mask="0x00080000" name="DIFF3"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 4" mask="0x00100000" name="DIFF4"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 5" mask="0x00200000" name="DIFF5"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 6" mask="0x00400000" name="DIFF6"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 7" mask="0x00800000" name="DIFF7"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 8" mask="0x01000000" name="DIFF8"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 9" mask="0x02000000" name="DIFF9"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 10" mask="0x04000000" name="DIFF10"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 11" mask="0x08000000" name="DIFF11"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 12" mask="0x10000000" name="DIFF12"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 13" mask="0x20000000" name="DIFF13"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 14" mask="0x40000000" name="DIFF14"/>
|
||
|
|
<bitfield caption="Differential inputs for channel 15" mask="0x80000000" name="DIFF15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 0" name="ADC_CDR0" offset="0x50" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 1" name="ADC_CDR1" offset="0x54" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 2" name="ADC_CDR2" offset="0x58" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 3" name="ADC_CDR3" offset="0x5C" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 4" name="ADC_CDR4" offset="0x60" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 5" name="ADC_CDR5" offset="0x64" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 6" name="ADC_CDR6" offset="0x68" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 7" name="ADC_CDR7" offset="0x6C" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 8" name="ADC_CDR8" offset="0x70" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 9" name="ADC_CDR9" offset="0x74" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 10" name="ADC_CDR10" offset="0x78" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 11" name="ADC_CDR11" offset="0x7C" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 12" name="ADC_CDR12" offset="0x80" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 13" name="ADC_CDR13" offset="0x84" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Data Register 14" name="ADC_CDR14" offset="0x88" rw="R" size="4">
|
||
|
|
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Analog Control Register" name="ADC_ACR" offset="0x94" rw="RW" size="4">
|
||
|
|
<bitfield caption="Temperature Sensor On" mask="0x00000010" name="TSON"/>
|
||
|
|
<bitfield caption="ADC Bias Current Control" mask="0x00000300" name="IBCTL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="ADC_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="ADC_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="ADC_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="ADC_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="ADC_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="ADC_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="ADC_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="ADC_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="ADC_MR__TRGEN">
|
||
|
|
<value caption="Hardware triggers are disabled. Starting a conversion is only possible by software." name="DIS" value="0"/>
|
||
|
|
<value caption="Hardware trigger selected by TRGSEL field is enabled." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__TRGSEL">
|
||
|
|
<value caption="External trigger" name="ADC_TRIG0" value="0x0"/>
|
||
|
|
<value caption="TIO Output of the Timer Counter Channel 0" name="ADC_TRIG1" value="0x1"/>
|
||
|
|
<value caption="TIO Output of the Timer Counter Channel 1" name="ADC_TRIG2" value="0x2"/>
|
||
|
|
<value caption="TIO Output of the Timer Counter Channel 2" name="ADC_TRIG3" value="0x3"/>
|
||
|
|
<value caption="PWM Event Line 0" name="ADC_TRIG4" value="0x4"/>
|
||
|
|
<value caption="PWM Event Line 1" name="ADC_TRIG5" value="0x5"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__LOWRES">
|
||
|
|
<value caption="12-bit resolution" name="BITS_12" value="0"/>
|
||
|
|
<value caption="10-bit resolution" name="BITS_10" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__SLEEP">
|
||
|
|
<value caption="Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions" name="NORMAL" value="0"/>
|
||
|
|
<value caption="Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions" name="SLEEP" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__FWUP">
|
||
|
|
<value caption="Normal Sleep Mode: The sleep mode is defined by the SLEEP bit" name="OFF" value="0"/>
|
||
|
|
<value caption="Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF" name="ON" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__FREERUN">
|
||
|
|
<value caption="Normal Mode" name="OFF" value="0"/>
|
||
|
|
<value caption="Free Run Mode: Never wait for any trigger." name="ON" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__STARTUP">
|
||
|
|
<value caption="0 periods of ADCClock" name="SUT0" value="0x0"/>
|
||
|
|
<value caption="8 periods of ADCClock" name="SUT8" value="0x1"/>
|
||
|
|
<value caption="16 periods of ADCClock" name="SUT16" value="0x2"/>
|
||
|
|
<value caption="24 periods of ADCClock" name="SUT24" value="0x3"/>
|
||
|
|
<value caption="64 periods of ADCClock" name="SUT64" value="0x4"/>
|
||
|
|
<value caption="80 periods of ADCClock" name="SUT80" value="0x5"/>
|
||
|
|
<value caption="96 periods of ADCClock" name="SUT96" value="0x6"/>
|
||
|
|
<value caption="112 periods of ADCClock" name="SUT112" value="0x7"/>
|
||
|
|
<value caption="512 periods of ADCClock" name="SUT512" value="0x8"/>
|
||
|
|
<value caption="576 periods of ADCClock" name="SUT576" value="0x9"/>
|
||
|
|
<value caption="640 periods of ADCClock" name="SUT640" value="0xA"/>
|
||
|
|
<value caption="704 periods of ADCClock" name="SUT704" value="0xB"/>
|
||
|
|
<value caption="768 periods of ADCClock" name="SUT768" value="0xC"/>
|
||
|
|
<value caption="832 periods of ADCClock" name="SUT832" value="0xD"/>
|
||
|
|
<value caption="896 periods of ADCClock" name="SUT896" value="0xE"/>
|
||
|
|
<value caption="960 periods of ADCClock" name="SUT960" value="0xF"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__SETTLING">
|
||
|
|
<value caption="3 periods of ADCClock" name="AST3" value="0x0"/>
|
||
|
|
<value caption="5 periods of ADCClock" name="AST5" value="0x1"/>
|
||
|
|
<value caption="9 periods of ADCClock" name="AST9" value="0x2"/>
|
||
|
|
<value caption="17 periods of ADCClock" name="AST17" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__ANACH">
|
||
|
|
<value caption="No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels" name="NONE" value="0"/>
|
||
|
|
<value caption="Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers" name="ALLOWED" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_MR__USEQ">
|
||
|
|
<value caption="Normal Mode: The controller converts channels in a simple numeric order." name="NUM_ORDER" value="0"/>
|
||
|
|
<value caption="User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers." name="REG_ORDER" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="ADC_EMR__CMPMODE">
|
||
|
|
<value caption="Generates an event when the converted data is lower than the low threshold of the window." name="LOW" value="0x0"/>
|
||
|
|
<value caption="Generates an event when the converted data is higher than the high threshold of the window." name="HIGH" value="0x1"/>
|
||
|
|
<value caption="Generates an event when the converted data is in the comparison window." name="IN" value="0x2"/>
|
||
|
|
<value caption="Generates an event when the converted data is out of the comparison window." name="OUT" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Chip Identifier" name="CHIPID" version="6417K">
|
||
|
|
<register-group name="CHIPID">
|
||
|
|
<register caption="Chip ID Register" name="CHIPID_CIDR" offset="0x0" rw="R" size="4">
|
||
|
|
<bitfield caption="Version of the Device" mask="0x0000001F" name="VERSION"/>
|
||
|
|
<bitfield caption="Embedded Processor" mask="0x000000E0" name="EPROC" values="CHIPID_CIDR__EPROC"/>
|
||
|
|
<bitfield caption="Nonvolatile Program Memory Size" mask="0x00000F00" name="NVPSIZ" values="CHIPID_CIDR__NVPSIZ"/>
|
||
|
|
<bitfield caption="Second Nonvolatile Program Memory Size" mask="0x0000F000" name="NVPSIZ2" values="CHIPID_CIDR__NVPSIZ2"/>
|
||
|
|
<bitfield caption="Internal SRAM Size" mask="0x000F0000" name="SRAMSIZ" values="CHIPID_CIDR__SRAMSIZ"/>
|
||
|
|
<bitfield caption="Architecture Identifier" mask="0x0FF00000" name="ARCH" values="CHIPID_CIDR__ARCH"/>
|
||
|
|
<bitfield caption="Nonvolatile Program Memory Type" mask="0x70000000" name="NVPTYP" values="CHIPID_CIDR__NVPTYP"/>
|
||
|
|
<bitfield caption="Extension Flag" mask="0x80000000" name="EXT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Chip ID Extension Register" name="CHIPID_EXID" offset="0x4" rw="R" size="4">
|
||
|
|
<bitfield caption="Chip ID Extension" mask="0xFFFFFFFF" name="EXID"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="CHIPID_CIDR__EPROC">
|
||
|
|
<value caption="ARM946ES" name="ARM946ES" value="0x1"/>
|
||
|
|
<value caption="ARM7TDMI" name="ARM7TDMI" value="0x2"/>
|
||
|
|
<value caption="Cortex-M3" name="CM3" value="0x3"/>
|
||
|
|
<value caption="ARM920T" name="ARM920T" value="0x4"/>
|
||
|
|
<value caption="ARM926EJS" name="ARM926EJS" value="0x5"/>
|
||
|
|
<value caption="Cortex-A5" name="CA5" value="0x6"/>
|
||
|
|
<value caption="Cortex-M4" name="CM4" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="CHIPID_CIDR__NVPSIZ">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="8K bytes" name="_8K" value="0x1"/>
|
||
|
|
<value caption="16K bytes" name="_16K" value="0x2"/>
|
||
|
|
<value caption="32K bytes" name="_32K" value="0x3"/>
|
||
|
|
<value caption="64K bytes" name="_64K" value="0x5"/>
|
||
|
|
<value caption="128K bytes" name="_128K" value="0x7"/>
|
||
|
|
<value caption="256K bytes" name="_256K" value="0x9"/>
|
||
|
|
<value caption="512K bytes" name="_512K" value="0xA"/>
|
||
|
|
<value caption="1024K bytes" name="_1024K" value="0xC"/>
|
||
|
|
<value caption="2048K bytes" name="_2048K" value="0xE"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="CHIPID_CIDR__NVPSIZ2">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="8K bytes" name="_8K" value="0x1"/>
|
||
|
|
<value caption="16K bytes" name="_16K" value="0x2"/>
|
||
|
|
<value caption="32K bytes" name="_32K" value="0x3"/>
|
||
|
|
<value caption="64K bytes" name="_64K" value="0x5"/>
|
||
|
|
<value caption="128K bytes" name="_128K" value="0x7"/>
|
||
|
|
<value caption="256K bytes" name="_256K" value="0x9"/>
|
||
|
|
<value caption="512K bytes" name="_512K" value="0xA"/>
|
||
|
|
<value caption="1024K bytes" name="_1024K" value="0xC"/>
|
||
|
|
<value caption="2048K bytes" name="_2048K" value="0xE"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="CHIPID_CIDR__SRAMSIZ">
|
||
|
|
<value caption="48K bytes" name="_48K" value="0x0"/>
|
||
|
|
<value caption="1K bytes" name="_1K" value="0x1"/>
|
||
|
|
<value caption="2K bytes" name="_2K" value="0x2"/>
|
||
|
|
<value caption="6K bytes" name="_6K" value="0x3"/>
|
||
|
|
<value caption="24K bytes" name="_24K" value="0x4"/>
|
||
|
|
<value caption="4K bytes" name="_4K" value="0x5"/>
|
||
|
|
<value caption="80K bytes" name="_80K" value="0x6"/>
|
||
|
|
<value caption="160K bytes" name="_160K" value="0x7"/>
|
||
|
|
<value caption="8K bytes" name="_8K" value="0x8"/>
|
||
|
|
<value caption="16K bytes" name="_16K" value="0x9"/>
|
||
|
|
<value caption="32K bytes" name="_32K" value="0xA"/>
|
||
|
|
<value caption="64K bytes" name="_64K" value="0xB"/>
|
||
|
|
<value caption="128K bytes" name="_128K" value="0xC"/>
|
||
|
|
<value caption="256K bytes" name="_256K" value="0xD"/>
|
||
|
|
<value caption="96K bytes" name="_96K" value="0xE"/>
|
||
|
|
<value caption="512K bytes" name="_512K" value="0xF"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="CHIPID_CIDR__ARCH">
|
||
|
|
<value caption="AT91SAM9xx Series" name="AT91SAM9xx" value="0x19"/>
|
||
|
|
<value caption="AT91SAM9XExx Series" name="AT91SAM9XExx" value="0x29"/>
|
||
|
|
<value caption="AT91x34 Series" name="AT91x34" value="0x34"/>
|
||
|
|
<value caption="CAP7 Series" name="CAP7" value="0x37"/>
|
||
|
|
<value caption="CAP9 Series" name="CAP9" value="0x39"/>
|
||
|
|
<value caption="CAP11 Series" name="CAP11" value="0x3B"/>
|
||
|
|
<value caption="AT91x40 Series" name="AT91x40" value="0x40"/>
|
||
|
|
<value caption="AT91x42 Series" name="AT91x42" value="0x42"/>
|
||
|
|
<value caption="AT91x55 Series" name="AT91x55" value="0x55"/>
|
||
|
|
<value caption="AT91SAM7Axx Series" name="AT91SAM7Axx" value="0x60"/>
|
||
|
|
<value caption="AT91SAM7AQxx Series" name="AT91SAM7AQxx" value="0x61"/>
|
||
|
|
<value caption="AT91x63 Series" name="AT91x63" value="0x63"/>
|
||
|
|
<value caption="AT91SAM7Sxx Series" name="AT91SAM7Sxx" value="0x70"/>
|
||
|
|
<value caption="AT91SAM7XCxx Series" name="AT91SAM7XCxx" value="0x71"/>
|
||
|
|
<value caption="AT91SAM7SExx Series" name="AT91SAM7SExx" value="0x72"/>
|
||
|
|
<value caption="AT91SAM7Lxx Series" name="AT91SAM7Lxx" value="0x73"/>
|
||
|
|
<value caption="AT91SAM7Xxx Series" name="AT91SAM7Xxx" value="0x75"/>
|
||
|
|
<value caption="AT91SAM7SLxx Series" name="AT91SAM7SLxx" value="0x76"/>
|
||
|
|
<value caption="SAM3UxC Series (100-pin version)" name="SAM3UxC" value="0x80"/>
|
||
|
|
<value caption="SAM3UxE Series (144-pin version)" name="SAM3UxE" value="0x81"/>
|
||
|
|
<value caption="SAM3AxC Series (100-pin version)" name="SAM3AxC" value="0x83"/>
|
||
|
|
<value caption="SAM4AxC Series (100-pin version)" name="SAM4AxC" value="0x83"/>
|
||
|
|
<value caption="SAM3XxC Series (100-pin version)" name="SAM3XxC" value="0x84"/>
|
||
|
|
<value caption="SAM4XxC Series (100-pin version)" name="SAM4XxC" value="0x84"/>
|
||
|
|
<value caption="SAM3XxE Series (144-pin version)" name="SAM3XxE" value="0x85"/>
|
||
|
|
<value caption="SAM4XxE Series (144-pin version)" name="SAM4XxE" value="0x85"/>
|
||
|
|
<value caption="SAM3XxG Series (208/217-pin version)" name="SAM3XxG" value="0x86"/>
|
||
|
|
<value caption="SAM4XxG Series (208/217-pin version)" name="SAM4XxG" value="0x86"/>
|
||
|
|
<value caption="SAM3SxASeries (48-pin version)" name="SAM3SxA" value="0x88"/>
|
||
|
|
<value caption="SAM4SxA Series (48-pin version)" name="SAM4SxA" value="0x88"/>
|
||
|
|
<value caption="SAM3SxB Series (64-pin version)" name="SAM3SxB" value="0x89"/>
|
||
|
|
<value caption="SAM4SxB Series (64-pin version)" name="SAM4SxB" value="0x89"/>
|
||
|
|
<value caption="SAM3SxC Series (100-pin version)" name="SAM3SxC" value="0x8A"/>
|
||
|
|
<value caption="SAM4SxC Series (100-pin version)" name="SAM4SxC" value="0x8A"/>
|
||
|
|
<value caption="AT91x92 Series" name="AT91x92" value="0x92"/>
|
||
|
|
<value caption="SAM3NxA Series (48-pin version)" name="SAM3NxA" value="0x93"/>
|
||
|
|
<value caption="SAM3NxB Series (64-pin version)" name="SAM3NxB" value="0x94"/>
|
||
|
|
<value caption="SAM3NxC Series (100-pin version)" name="SAM3NxC" value="0x95"/>
|
||
|
|
<value caption="SAM3SDxB Series (64-pin version)" name="SAM3SDxB" value="0x99"/>
|
||
|
|
<value caption="SAM3SDxC Series (100-pin version)" name="SAM3SDxC" value="0x9A"/>
|
||
|
|
<value caption="SAM5A" name="SAM5A" value="0xA5"/>
|
||
|
|
<value caption="AT75Cxx Series" name="AT75Cxx" value="0xF0"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="CHIPID_CIDR__NVPTYP">
|
||
|
|
<value caption="ROM" name="ROM" value="0x0"/>
|
||
|
|
<value caption="ROMless or on-chip Flash" name="ROMLESS" value="0x1"/>
|
||
|
|
<value caption="Embedded Flash Memory" name="FLASH" value="0x2"/>
|
||
|
|
<value caption="ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size" name="ROM_FLASH" value="0x3"/>
|
||
|
|
<value caption="SRAM emulating ROM" name="SRAM" value="0x4"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Cyclic Redundancy Check Calculation Unit" name="CRCCU" version="11001D">
|
||
|
|
<register-group name="CRCCU">
|
||
|
|
<register caption="CRCCU Descriptor Base Register" name="CRCCU_DSCR" offset="0x00000000" rw="RW" size="4">
|
||
|
|
<bitfield caption="Descriptor Base Address" mask="0xFFFFFE00" name="DSCR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Enable Register" name="CRCCU_DMA_EN" offset="0x00000008" rw="W" size="4">
|
||
|
|
<bitfield caption="DMA Enable Register" mask="0x00000001" name="DMAEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Disable Register" name="CRCCU_DMA_DIS" offset="0x0000000C" rw="W" size="4">
|
||
|
|
<bitfield caption="DMA Disable Register" mask="0x00000001" name="DMADIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Status Register" name="CRCCU_DMA_SR" offset="0x00000010" rw="R" size="4">
|
||
|
|
<bitfield caption="DMA Status Register" mask="0x00000001" name="DMASR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Interrupt Enable Register" name="CRCCU_DMA_IER" offset="0x00000014" rw="W" size="4">
|
||
|
|
<bitfield caption="Interrupt Enable register" mask="0x00000001" name="DMAIER"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Interrupt Disable Register" name="CRCCU_DMA_IDR" offset="0x00000018" rw="W" size="4">
|
||
|
|
<bitfield caption="Interrupt Disable register" mask="0x00000001" name="DMAIDR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Interrupt Mask Register" name="CRCCU_DMA_IMR" offset="0x0000001C" rw="R" size="4">
|
||
|
|
<bitfield caption="Interrupt Mask Register" mask="0x00000001" name="DMAIMR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU DMA Interrupt Status Register" name="CRCCU_DMA_ISR" offset="0x00000020" rw="R" size="4">
|
||
|
|
<bitfield caption="Interrupt Status register" mask="0x00000001" name="DMAISR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Control Register" name="CRCCU_CR" offset="0x00000034" rw="W" size="4">
|
||
|
|
<bitfield caption="CRC Computation Reset" mask="0x00000001" name="RESET"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Mode Register" name="CRCCU_MR" offset="0x00000038" rw="RW" size="4">
|
||
|
|
<bitfield caption="CRC Enable" mask="0x00000001" name="ENABLE"/>
|
||
|
|
<bitfield caption="CRC Compare" mask="0x00000002" name="COMPARE"/>
|
||
|
|
<bitfield caption="Primitive Polynomial" mask="0x0000000C" name="PTYPE" values="CRCCU_MR__PTYPE"/>
|
||
|
|
<bitfield caption="Request Divider" mask="0x000000F0" name="DIVIDER"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Status Register" name="CRCCU_SR" offset="0x0000003C" rw="R" size="4">
|
||
|
|
<bitfield caption="Cyclic Redundancy Check Value" mask="0xFFFFFFFF" name="CRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Interrupt Enable Register" name="CRCCU_IER" offset="0x00000040" rw="W" size="4">
|
||
|
|
<bitfield caption="CRC Error Interrupt Enable" mask="0x00000001" name="ERRIER"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Interrupt Disable Register" name="CRCCU_IDR" offset="0x00000044" rw="W" size="4">
|
||
|
|
<bitfield caption="CRC Error Interrupt Disable" mask="0x00000001" name="ERRIDR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Interrupt Mask Register" name="CRCCU_IMR" offset="0x00000048" rw="R" size="4">
|
||
|
|
<bitfield caption="CRC Error Interrupt Mask" mask="0x00000001" name="ERRIMR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="CRCCU Interrupt Status Register" name="CRCCU_ISR" offset="0x0000004C" rw="R" size="4">
|
||
|
|
<bitfield caption="CRC Error Interrupt Status" mask="0x00000001" name="ERRISR"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="CRCCU_MR__PTYPE">
|
||
|
|
<value caption="Polynom 0x04C11DB7" name="CCITT8023" value="0x0"/>
|
||
|
|
<value caption="Polynom 0x1EDC6F41" name="CASTAGNOLI" value="0x1"/>
|
||
|
|
<value caption="Polynom 0x1021" name="CCITT16" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Digital-to-Analog Converter Controller" name="DACC" version="6461F">
|
||
|
|
<register-group name="DACC">
|
||
|
|
<register caption="Control Register" name="DACC_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Software Reset" mask="0x00000001" name="SWRST"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="DACC_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Trigger Enable" mask="0x00000001" name="TRGEN" values="DACC_MR__TRGEN"/>
|
||
|
|
<bitfield caption="Trigger Selection" mask="0x0000000E" name="TRGSEL"/>
|
||
|
|
<bitfield caption="Word Transfer" mask="0x00000010" name="WORD" values="DACC_MR__WORD"/>
|
||
|
|
<bitfield caption="Sleep Mode" mask="0x00000020" name="SLEEP"/>
|
||
|
|
<bitfield caption="Fast Wake up Mode" mask="0x00000040" name="FASTWKUP"/>
|
||
|
|
<bitfield caption="Refresh Period" mask="0x0000FF00" name="REFRESH"/>
|
||
|
|
<bitfield caption="User Channel Selection" mask="0x00030000" name="USER_SEL" values="DACC_MR__USER_SEL"/>
|
||
|
|
<bitfield caption="Tag Selection Mode" mask="0x00100000" name="TAG" values="DACC_MR__TAG"/>
|
||
|
|
<bitfield caption="Max Speed Mode" mask="0x00200000" name="MAXS" values="DACC_MR__MAXS"/>
|
||
|
|
<bitfield caption="Startup Time Selection" mask="0x3F000000" name="STARTUP" values="DACC_MR__STARTUP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Enable Register" name="DACC_CHER" offset="0x10" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel 0 Enable" mask="0x00000001" name="CH0"/>
|
||
|
|
<bitfield caption="Channel 1 Enable" mask="0x00000002" name="CH1"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Disable Register" name="DACC_CHDR" offset="0x14" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel 0 Disable" mask="0x00000001" name="CH0"/>
|
||
|
|
<bitfield caption="Channel 1 Disable" mask="0x00000002" name="CH1"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Status Register" name="DACC_CHSR" offset="0x18" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel 0 Status" mask="0x00000001" name="CH0"/>
|
||
|
|
<bitfield caption="Channel 1 Status" mask="0x00000002" name="CH1"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Conversion Data Register" name="DACC_CDR" offset="0x20" rw="W" size="4">
|
||
|
|
<bitfield caption="Data to Convert" mask="0xFFFFFFFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="DACC_IER" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Enable" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Enable" mask="0x00000002" name="EOC"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Enable" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Enable" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="DACC_IDR" offset="0x28" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Disable." mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Disable" mask="0x00000002" name="EOC"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Disable" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Disable" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="DACC_IMR" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Mask" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Mask" mask="0x00000002" name="EOC"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Mask" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Mask" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Status Register" name="DACC_ISR" offset="0x30" rw="R" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Flag" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="End of Conversion Interrupt Flag" mask="0x00000002" name="EOC"/>
|
||
|
|
<bitfield caption="End of DMA Interrupt Flag" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Analog Current Register" name="DACC_ACR" offset="0x94" rw="RW" size="4">
|
||
|
|
<bitfield caption="Analog Output Current Control" mask="0x00000003" name="IBCTLCH0"/>
|
||
|
|
<bitfield caption="Analog Output Current Control" mask="0x0000000C" name="IBCTLCH1"/>
|
||
|
|
<bitfield caption="Bias Current Control for DAC Core" mask="0x00000300" name="IBCTLDACCORE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode register" name="DACC_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status register" name="DACC_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write protection error" mask="0x00000001" name="WPROTERR"/>
|
||
|
|
<bitfield caption="Write protection error address" mask="0x0000FF00" name="WPROTADDR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="DACC_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="DACC_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="DACC_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="DACC_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="DACC_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="DACC_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="DACC_MR__TRGEN">
|
||
|
|
<value caption="External trigger mode disabled. DACC in free running mode." name="DIS" value="0"/>
|
||
|
|
<value caption="External trigger mode enabled." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="DACC_MR__WORD">
|
||
|
|
<value caption="Half-Word transfer" name="HALF" value="0"/>
|
||
|
|
<value caption="Word Transfer" name="WORD" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="DACC_MR__USER_SEL">
|
||
|
|
<value caption="Channel 0" name="CHANNEL0" value="0"/>
|
||
|
|
<value caption="Channel 1" name="CHANNEL1" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="DACC_MR__TAG">
|
||
|
|
<value caption="Tag selection mode disabled. Using USER_SEL to select the channel for the conversion." name="DIS" value="0"/>
|
||
|
|
<value caption="Tag selection mode enabled" name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="DACC_MR__MAXS">
|
||
|
|
<value caption="Normal Mode" name="NORMAL" value="0"/>
|
||
|
|
<value caption="Max Speed Mode enabled" name="MAXIMUM" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="DACC_MR__STARTUP">
|
||
|
|
<value caption="0 periods of DACClock" name="_0" value="0x0"/>
|
||
|
|
<value caption="8 periods of DACClock" name="_8" value="0x1"/>
|
||
|
|
<value caption="16 periods of DACClock" name="_16" value="0x2"/>
|
||
|
|
<value caption="24 periods of DACClock" name="_24" value="0x3"/>
|
||
|
|
<value caption="64 periods of DACClock" name="_64" value="0x4"/>
|
||
|
|
<value caption="80 periods of DACClock" name="_80" value="0x5"/>
|
||
|
|
<value caption="96 periods of DACClock" name="_96" value="0x6"/>
|
||
|
|
<value caption="112 periods of DACClock" name="_112" value="0x7"/>
|
||
|
|
<value caption="512 periods of DACClock" name="_512" value="0x8"/>
|
||
|
|
<value caption="576 periods of DACClock" name="_576" value="0x9"/>
|
||
|
|
<value caption="640 periods of DACClock" name="_640" value="0xA"/>
|
||
|
|
<value caption="704 periods of DACClock" name="_704" value="0xB"/>
|
||
|
|
<value caption="768 periods of DACClock" name="_768" value="0xC"/>
|
||
|
|
<value caption="832 periods of DACClock" name="_832" value="0xD"/>
|
||
|
|
<value caption="896 periods of DACClock" name="_896" value="0xE"/>
|
||
|
|
<value caption="960 periods of DACClock" name="_960" value="0xF"/>
|
||
|
|
<value caption="1024 periods of DACClock" name="_1024" value="0x10"/>
|
||
|
|
<value caption="1088 periods of DACClock" name="_1088" value="0x11"/>
|
||
|
|
<value caption="1152 periods of DACClock" name="_1152" value="0x12"/>
|
||
|
|
<value caption="1216 periods of DACClock" name="_1216" value="0x13"/>
|
||
|
|
<value caption="1280 periods of DACClock" name="_1280" value="0x14"/>
|
||
|
|
<value caption="1344 periods of DACClock" name="_1344" value="0x15"/>
|
||
|
|
<value caption="1408 periods of DACClock" name="_1408" value="0x16"/>
|
||
|
|
<value caption="1472 periods of DACClock" name="_1472" value="0x17"/>
|
||
|
|
<value caption="1536 periods of DACClock" name="_1536" value="0x18"/>
|
||
|
|
<value caption="1600 periods of DACClock" name="_1600" value="0x19"/>
|
||
|
|
<value caption="1664 periods of DACClock" name="_1664" value="0x1A"/>
|
||
|
|
<value caption="1728 periods of DACClock" name="_1728" value="0x1B"/>
|
||
|
|
<value caption="1792 periods of DACClock" name="_1792" value="0x1C"/>
|
||
|
|
<value caption="1856 periods of DACClock" name="_1856" value="0x1D"/>
|
||
|
|
<value caption="1920 periods of DACClock" name="_1920" value="0x1E"/>
|
||
|
|
<value caption="1984 periods of DACClock" name="_1984" value="0x1F"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Embedded Flash Controller" name="EFC" version="6450G">
|
||
|
|
<register-group name="EFC">
|
||
|
|
<register caption="EEFC Flash Mode Register" name="EEFC_FMR" offset="0x00" rw="RW" size="4">
|
||
|
|
<bitfield caption="Ready Interrupt Enable" mask="0x00000001" name="FRDY"/>
|
||
|
|
<bitfield caption="Flash Wait State" mask="0x00000F00" name="FWS"/>
|
||
|
|
<bitfield caption="Sequential Code Optimization Disable" mask="0x00010000" name="SCOD"/>
|
||
|
|
<bitfield caption="Flash Access Mode" mask="0x01000000" name="FAM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="EEFC Flash Command Register" name="EEFC_FCR" offset="0x04" rw="W" size="4">
|
||
|
|
<bitfield caption="Flash Command" mask="0x000000FF" name="FCMD" values="EEFC_FCR__FCMD"/>
|
||
|
|
<bitfield caption="Flash Command Argument" mask="0x00FFFF00" name="FARG"/>
|
||
|
|
<bitfield caption="Flash Writing Protection Key" mask="0xFF000000" name="FKEY" values="EEFC_FCR__FKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="EEFC Flash Status Register" name="EEFC_FSR" offset="0x08" rw="R" size="4">
|
||
|
|
<bitfield caption="Flash Ready Status" mask="0x00000001" name="FRDY"/>
|
||
|
|
<bitfield caption="Flash Command Error Status" mask="0x00000002" name="FCMDE"/>
|
||
|
|
<bitfield caption="Flash Lock Error Status" mask="0x00000004" name="FLOCKE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="EEFC Flash Result Register" name="EEFC_FRR" offset="0x0C" rw="R" size="4">
|
||
|
|
<bitfield caption="Flash Result Value" mask="0xFFFFFFFF" name="FVALUE"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="EEFC_FCR__FCMD">
|
||
|
|
<value caption="Get Flash Descriptor" name="GETD" value="0x00"/>
|
||
|
|
<value caption="Write page" name="WP" value="0x01"/>
|
||
|
|
<value caption="Write page and lock" name="WPL" value="0x02"/>
|
||
|
|
<value caption="Erase page and write page" name="EWP" value="0x03"/>
|
||
|
|
<value caption="Erase page and write page then lock" name="EWPL" value="0x04"/>
|
||
|
|
<value caption="Erase all" name="EA" value="0x05"/>
|
||
|
|
<value caption="Set Lock Bit" name="SLB" value="0x08"/>
|
||
|
|
<value caption="Clear Lock Bit" name="CLB" value="0x09"/>
|
||
|
|
<value caption="Get Lock Bit" name="GLB" value="0x0A"/>
|
||
|
|
<value caption="Set GPNVM Bit" name="SGPB" value="0x0B"/>
|
||
|
|
<value caption="Clear GPNVM Bit" name="CGPB" value="0x0C"/>
|
||
|
|
<value caption="Get GPNVM Bit" name="GGPB" value="0x0D"/>
|
||
|
|
<value caption="Start Read Unique Identifier" name="STUI" value="0x0E"/>
|
||
|
|
<value caption="Stop Read Unique Identifier" name="SPUI" value="0x0F"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="EEFC_FCR__FKEY">
|
||
|
|
<value caption="The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started." name="PASSWD" value="0x5A"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="General Purpose Backup Register" name="GPBR" version="6378C">
|
||
|
|
<register-group name="GPBR">
|
||
|
|
<register caption="General Purpose Backup Register 0" name="SYS_GPBR0" offset="0x0" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 1" name="SYS_GPBR1" offset="0x4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 2" name="SYS_GPBR2" offset="0x8" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 3" name="SYS_GPBR3" offset="0xC" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 4" name="SYS_GPBR4" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 5" name="SYS_GPBR5" offset="0x14" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 6" name="SYS_GPBR6" offset="0x18" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="General Purpose Backup Register 7" name="SYS_GPBR7" offset="0x1C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module caption="High Speed MultiMedia Card Interface" name="HSMCI" version="6449H">
|
||
|
|
<register-group name="HSMCI">
|
||
|
|
<register caption="Control Register" name="HSMCI_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Multi-Media Interface Enable" mask="0x00000001" name="MCIEN"/>
|
||
|
|
<bitfield caption="Multi-Media Interface Disable" mask="0x00000002" name="MCIDIS"/>
|
||
|
|
<bitfield caption="Power Save Mode Enable" mask="0x00000004" name="PWSEN"/>
|
||
|
|
<bitfield caption="Power Save Mode Disable" mask="0x00000008" name="PWSDIS"/>
|
||
|
|
<bitfield caption="Software Reset" mask="0x00000080" name="SWRST"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="HSMCI_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Divider" mask="0x000000FF" name="CLKDIV"/>
|
||
|
|
<bitfield caption="Power Saving Divider" mask="0x00000700" name="PWSDIV"/>
|
||
|
|
<bitfield caption="" mask="0x00000800" name="RDPROOF"/>
|
||
|
|
<bitfield caption="" mask="0x00001000" name="WRPROOF"/>
|
||
|
|
<bitfield caption="Force Byte Transfer" mask="0x00002000" name="FBYTE"/>
|
||
|
|
<bitfield caption="Padding Value" mask="0x00004000" name="PADV"/>
|
||
|
|
<bitfield caption="PDC-oriented Mode" mask="0x00008000" name="PDCMODE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Data Timeout Register" name="HSMCI_DTOR" offset="0x08" rw="RW" size="4">
|
||
|
|
<bitfield caption="Data Timeout Cycle Number" mask="0x0000000F" name="DTOCYC"/>
|
||
|
|
<bitfield caption="Data Timeout Multiplier" mask="0x00000070" name="DTOMUL" values="HSMCI_DTOR__DTOMUL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="SD/SDIO Card Register" name="HSMCI_SDCR" offset="0x0C" rw="RW" size="4">
|
||
|
|
<bitfield caption="SDCard/SDIO Slot" mask="0x00000003" name="SDCSEL" values="HSMCI_SDCR__SDCSEL"/>
|
||
|
|
<bitfield caption="SDCard/SDIO Bus Width" mask="0x000000C0" name="SDCBUS" values="HSMCI_SDCR__SDCBUS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Argument Register" name="HSMCI_ARGR" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Command Argument" mask="0xFFFFFFFF" name="ARG"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Command Register" name="HSMCI_CMDR" offset="0x14" rw="W" size="4">
|
||
|
|
<bitfield caption="Command Number" mask="0x0000003F" name="CMDNB"/>
|
||
|
|
<bitfield caption="Response Type" mask="0x000000C0" name="RSPTYP" values="HSMCI_CMDR__RSPTYP"/>
|
||
|
|
<bitfield caption="Special Command" mask="0x00000700" name="SPCMD" values="HSMCI_CMDR__SPCMD"/>
|
||
|
|
<bitfield caption="Open Drain Command" mask="0x00000800" name="OPDCMD" values="HSMCI_CMDR__OPDCMD"/>
|
||
|
|
<bitfield caption="Max Latency for Command to Response" mask="0x00001000" name="MAXLAT" values="HSMCI_CMDR__MAXLAT"/>
|
||
|
|
<bitfield caption="Transfer Command" mask="0x00030000" name="TRCMD" values="HSMCI_CMDR__TRCMD"/>
|
||
|
|
<bitfield caption="Transfer Direction" mask="0x00040000" name="TRDIR" values="HSMCI_CMDR__TRDIR"/>
|
||
|
|
<bitfield caption="Transfer Type" mask="0x00380000" name="TRTYP" values="HSMCI_CMDR__TRTYP"/>
|
||
|
|
<bitfield caption="SDIO Special Command" mask="0x03000000" name="IOSPCMD" values="HSMCI_CMDR__IOSPCMD"/>
|
||
|
|
<bitfield caption="ATA with Command Completion Signal" mask="0x04000000" name="ATACS" values="HSMCI_CMDR__ATACS"/>
|
||
|
|
<bitfield caption="Boot Operation Acknowledge." mask="0x08000000" name="BOOT_ACK"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Block Register" name="HSMCI_BLKR" offset="0x18" rw="RW" size="4">
|
||
|
|
<bitfield caption="MMC/SDIO Block Count - SDIO Byte Count" mask="0x0000FFFF" name="BCNT" values="HSMCI_BLKR__BCNT"/>
|
||
|
|
<bitfield caption="Data Block Length" mask="0xFFFF0000" name="BLKLEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Completion Signal Timeout Register" name="HSMCI_CSTOR" offset="0x1C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Completion Signal Timeout Cycle Number" mask="0x0000000F" name="CSTOCYC"/>
|
||
|
|
<bitfield caption="Completion Signal Timeout Multiplier" mask="0x00000070" name="CSTOMUL" values="HSMCI_CSTOR__CSTOMUL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Response Register 0" name="HSMCI_RSPR0" offset="0x20" rw="R" size="4">
|
||
|
|
<bitfield caption="Response" mask="0xFFFFFFFF" name="RSP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Response Register 1" name="HSMCI_RSPR1" offset="0x24" rw="R" size="4">
|
||
|
|
<bitfield caption="Response" mask="0xFFFFFFFF" name="RSP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Response Register 2" name="HSMCI_RSPR2" offset="0x28" rw="R" size="4">
|
||
|
|
<bitfield caption="Response" mask="0xFFFFFFFF" name="RSP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Response Register 3" name="HSMCI_RSPR3" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="Response" mask="0xFFFFFFFF" name="RSP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Data Register" name="HSMCI_RDR" offset="0x30" rw="R" size="4">
|
||
|
|
<bitfield caption="Data to Read" mask="0xFFFFFFFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Data Register" name="HSMCI_TDR" offset="0x34" rw="W" size="4">
|
||
|
|
<bitfield caption="Data to Write" mask="0xFFFFFFFF" name="DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="HSMCI_SR" offset="0x40" rw="R" size="4">
|
||
|
|
<bitfield caption="Command Ready" mask="0x00000001" name="CMDRDY"/>
|
||
|
|
<bitfield caption="Receiver Ready" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Ready" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Data Block Ended" mask="0x00000008" name="BLKE"/>
|
||
|
|
<bitfield caption="Data Transfer in Progress" mask="0x00000010" name="DTIP"/>
|
||
|
|
<bitfield caption="HSMCI Not Busy" mask="0x00000020" name="NOTBUSY"/>
|
||
|
|
<bitfield caption="End of RX Buffer" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of TX Buffer" mask="0x00000080" name="ENDTX"/>
|
||
|
|
<bitfield caption="SDIO Interrupt for Slot A" mask="0x00000100" name="SDIOIRQA"/>
|
||
|
|
<bitfield caption="SDIO Read Wait Operation Status" mask="0x00001000" name="SDIOWAIT"/>
|
||
|
|
<bitfield caption="CE-ATA Completion Signal Received" mask="0x00002000" name="CSRCV"/>
|
||
|
|
<bitfield caption="RX Buffer Full" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="TX Buffer Empty" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Response Index Error" mask="0x00010000" name="RINDE"/>
|
||
|
|
<bitfield caption="Response Direction Error" mask="0x00020000" name="RDIRE"/>
|
||
|
|
<bitfield caption="Response CRC Error" mask="0x00040000" name="RCRCE"/>
|
||
|
|
<bitfield caption="Response End Bit Error" mask="0x00080000" name="RENDE"/>
|
||
|
|
<bitfield caption="Response Time-out Error" mask="0x00100000" name="RTOE"/>
|
||
|
|
<bitfield caption="Data CRC Error" mask="0x00200000" name="DCRCE"/>
|
||
|
|
<bitfield caption="Data Time-out Error" mask="0x00400000" name="DTOE"/>
|
||
|
|
<bitfield caption="Completion Signal Time-out Error" mask="0x00800000" name="CSTOE"/>
|
||
|
|
<bitfield caption="FIFO empty flag" mask="0x04000000" name="FIFOEMPTY"/>
|
||
|
|
<bitfield caption="Transfer Done flag" mask="0x08000000" name="XFRDONE"/>
|
||
|
|
<bitfield caption="Boot Operation Acknowledge Received" mask="0x10000000" name="ACKRCV"/>
|
||
|
|
<bitfield caption="Boot Operation Acknowledge Error" mask="0x20000000" name="ACKRCVE"/>
|
||
|
|
<bitfield caption="Overrun" mask="0x40000000" name="OVRE"/>
|
||
|
|
<bitfield caption="Underrun" mask="0x80000000" name="UNRE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="HSMCI_IER" offset="0x44" rw="W" size="4">
|
||
|
|
<bitfield caption="Command Ready Interrupt Enable" mask="0x00000001" name="CMDRDY"/>
|
||
|
|
<bitfield caption="Receiver Ready Interrupt Enable" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Enable" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Data Block Ended Interrupt Enable" mask="0x00000008" name="BLKE"/>
|
||
|
|
<bitfield caption="Data Transfer in Progress Interrupt Enable" mask="0x00000010" name="DTIP"/>
|
||
|
|
<bitfield caption="Data Not Busy Interrupt Enable" mask="0x00000020" name="NOTBUSY"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Enable" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Enable" mask="0x00000080" name="ENDTX"/>
|
||
|
|
<bitfield caption="SDIO Interrupt for Slot A Interrupt Enable" mask="0x00000100" name="SDIOIRQA"/>
|
||
|
|
<bitfield caption="SDIO Read Wait Operation Status Interrupt Enable" mask="0x00001000" name="SDIOWAIT"/>
|
||
|
|
<bitfield caption="Completion Signal Received Interrupt Enable" mask="0x00002000" name="CSRCV"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Enable" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Enable" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Response Index Error Interrupt Enable" mask="0x00010000" name="RINDE"/>
|
||
|
|
<bitfield caption="Response Direction Error Interrupt Enable" mask="0x00020000" name="RDIRE"/>
|
||
|
|
<bitfield caption="Response CRC Error Interrupt Enable" mask="0x00040000" name="RCRCE"/>
|
||
|
|
<bitfield caption="Response End Bit Error Interrupt Enable" mask="0x00080000" name="RENDE"/>
|
||
|
|
<bitfield caption="Response Time-out Error Interrupt Enable" mask="0x00100000" name="RTOE"/>
|
||
|
|
<bitfield caption="Data CRC Error Interrupt Enable" mask="0x00200000" name="DCRCE"/>
|
||
|
|
<bitfield caption="Data Time-out Error Interrupt Enable" mask="0x00400000" name="DTOE"/>
|
||
|
|
<bitfield caption="Completion Signal Timeout Error Interrupt Enable" mask="0x00800000" name="CSTOE"/>
|
||
|
|
<bitfield caption="FIFO empty Interrupt enable" mask="0x04000000" name="FIFOEMPTY"/>
|
||
|
|
<bitfield caption="Transfer Done Interrupt enable" mask="0x08000000" name="XFRDONE"/>
|
||
|
|
<bitfield caption="Boot Acknowledge Interrupt Enable" mask="0x10000000" name="ACKRCV"/>
|
||
|
|
<bitfield caption="Boot Acknowledge Error Interrupt Enable" mask="0x20000000" name="ACKRCVE"/>
|
||
|
|
<bitfield caption="Overrun Interrupt Enable" mask="0x40000000" name="OVRE"/>
|
||
|
|
<bitfield caption="Underrun Interrupt Enable" mask="0x80000000" name="UNRE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="HSMCI_IDR" offset="0x48" rw="W" size="4">
|
||
|
|
<bitfield caption="Command Ready Interrupt Disable" mask="0x00000001" name="CMDRDY"/>
|
||
|
|
<bitfield caption="Receiver Ready Interrupt Disable" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Disable" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Data Block Ended Interrupt Disable" mask="0x00000008" name="BLKE"/>
|
||
|
|
<bitfield caption="Data Transfer in Progress Interrupt Disable" mask="0x00000010" name="DTIP"/>
|
||
|
|
<bitfield caption="Data Not Busy Interrupt Disable" mask="0x00000020" name="NOTBUSY"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Disable" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Disable" mask="0x00000080" name="ENDTX"/>
|
||
|
|
<bitfield caption="SDIO Interrupt for Slot A Interrupt Disable" mask="0x00000100" name="SDIOIRQA"/>
|
||
|
|
<bitfield caption="SDIO Read Wait Operation Status Interrupt Disable" mask="0x00001000" name="SDIOWAIT"/>
|
||
|
|
<bitfield caption="Completion Signal received interrupt Disable" mask="0x00002000" name="CSRCV"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Disable" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Disable" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Response Index Error Interrupt Disable" mask="0x00010000" name="RINDE"/>
|
||
|
|
<bitfield caption="Response Direction Error Interrupt Disable" mask="0x00020000" name="RDIRE"/>
|
||
|
|
<bitfield caption="Response CRC Error Interrupt Disable" mask="0x00040000" name="RCRCE"/>
|
||
|
|
<bitfield caption="Response End Bit Error Interrupt Disable" mask="0x00080000" name="RENDE"/>
|
||
|
|
<bitfield caption="Response Time-out Error Interrupt Disable" mask="0x00100000" name="RTOE"/>
|
||
|
|
<bitfield caption="Data CRC Error Interrupt Disable" mask="0x00200000" name="DCRCE"/>
|
||
|
|
<bitfield caption="Data Time-out Error Interrupt Disable" mask="0x00400000" name="DTOE"/>
|
||
|
|
<bitfield caption="Completion Signal Time out Error Interrupt Disable" mask="0x00800000" name="CSTOE"/>
|
||
|
|
<bitfield caption="FIFO empty Interrupt Disable" mask="0x04000000" name="FIFOEMPTY"/>
|
||
|
|
<bitfield caption="Transfer Done Interrupt Disable" mask="0x08000000" name="XFRDONE"/>
|
||
|
|
<bitfield caption="Boot Acknowledge Interrupt Disable" mask="0x10000000" name="ACKRCV"/>
|
||
|
|
<bitfield caption="Boot Acknowledge Error Interrupt Disable" mask="0x20000000" name="ACKRCVE"/>
|
||
|
|
<bitfield caption="Overrun Interrupt Disable" mask="0x40000000" name="OVRE"/>
|
||
|
|
<bitfield caption="Underrun Interrupt Disable" mask="0x80000000" name="UNRE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="HSMCI_IMR" offset="0x4C" rw="R" size="4">
|
||
|
|
<bitfield caption="Command Ready Interrupt Mask" mask="0x00000001" name="CMDRDY"/>
|
||
|
|
<bitfield caption="Receiver Ready Interrupt Mask" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Mask" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Data Block Ended Interrupt Mask" mask="0x00000008" name="BLKE"/>
|
||
|
|
<bitfield caption="Data Transfer in Progress Interrupt Mask" mask="0x00000010" name="DTIP"/>
|
||
|
|
<bitfield caption="Data Not Busy Interrupt Mask" mask="0x00000020" name="NOTBUSY"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Mask" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Mask" mask="0x00000080" name="ENDTX"/>
|
||
|
|
<bitfield caption="SDIO Interrupt for Slot A Interrupt Mask" mask="0x00000100" name="SDIOIRQA"/>
|
||
|
|
<bitfield caption="SDIO Read Wait Operation Status Interrupt Mask" mask="0x00001000" name="SDIOWAIT"/>
|
||
|
|
<bitfield caption="Completion Signal Received Interrupt Mask" mask="0x00002000" name="CSRCV"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Mask" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Mask" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Response Index Error Interrupt Mask" mask="0x00010000" name="RINDE"/>
|
||
|
|
<bitfield caption="Response Direction Error Interrupt Mask" mask="0x00020000" name="RDIRE"/>
|
||
|
|
<bitfield caption="Response CRC Error Interrupt Mask" mask="0x00040000" name="RCRCE"/>
|
||
|
|
<bitfield caption="Response End Bit Error Interrupt Mask" mask="0x00080000" name="RENDE"/>
|
||
|
|
<bitfield caption="Response Time-out Error Interrupt Mask" mask="0x00100000" name="RTOE"/>
|
||
|
|
<bitfield caption="Data CRC Error Interrupt Mask" mask="0x00200000" name="DCRCE"/>
|
||
|
|
<bitfield caption="Data Time-out Error Interrupt Mask" mask="0x00400000" name="DTOE"/>
|
||
|
|
<bitfield caption="Completion Signal Time-out Error Interrupt Mask" mask="0x00800000" name="CSTOE"/>
|
||
|
|
<bitfield caption="FIFO Empty Interrupt Mask" mask="0x04000000" name="FIFOEMPTY"/>
|
||
|
|
<bitfield caption="Transfer Done Interrupt Mask" mask="0x08000000" name="XFRDONE"/>
|
||
|
|
<bitfield caption="Boot Operation Acknowledge Received Interrupt Mask" mask="0x10000000" name="ACKRCV"/>
|
||
|
|
<bitfield caption="Boot Operation Acknowledge Error Interrupt Mask" mask="0x20000000" name="ACKRCVE"/>
|
||
|
|
<bitfield caption="Overrun Interrupt Mask" mask="0x40000000" name="OVRE"/>
|
||
|
|
<bitfield caption="Underrun Interrupt Mask" mask="0x80000000" name="UNRE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Configuration Register" name="HSMCI_CFG" offset="0x54" rw="RW" size="4">
|
||
|
|
<bitfield caption="HSMCI Internal FIFO control mode" mask="0x00000001" name="FIFOMODE"/>
|
||
|
|
<bitfield caption="Flow Error flag reset control mode" mask="0x00000010" name="FERRCTRL"/>
|
||
|
|
<bitfield caption="High Speed Mode" mask="0x00000100" name="HSMODE"/>
|
||
|
|
<bitfield caption="Synchronize on the last block" mask="0x00001000" name="LSYNC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protection Mode Register" name="HSMCI_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protection Enable" mask="0x00000001" name="WP_EN"/>
|
||
|
|
<bitfield caption="Write Protection Key password" mask="0xFFFFFF00" name="WP_KEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protection Status Register" name="HSMCI_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protection Violation Status" mask="0x0000000F" name="WP_VS" values="HSMCI_WPSR__WP_VS"/>
|
||
|
|
<bitfield caption="Write Protection Violation SouRCe" mask="0x00FFFF00" name="WP_VSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="FIFO Memory Aperture0 0" name="HSMCI_FIFO0" offset="0x200" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 1" name="HSMCI_FIFO1" offset="0x204" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 2" name="HSMCI_FIFO2" offset="0x208" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 3" name="HSMCI_FIFO3" offset="0x20C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 4" name="HSMCI_FIFO4" offset="0x210" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 5" name="HSMCI_FIFO5" offset="0x214" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 6" name="HSMCI_FIFO6" offset="0x218" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 7" name="HSMCI_FIFO7" offset="0x21C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 8" name="HSMCI_FIFO8" offset="0x220" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 9" name="HSMCI_FIFO9" offset="0x224" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 10" name="HSMCI_FIFO10" offset="0x228" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 11" name="HSMCI_FIFO11" offset="0x22C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 12" name="HSMCI_FIFO12" offset="0x230" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 13" name="HSMCI_FIFO13" offset="0x234" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 14" name="HSMCI_FIFO14" offset="0x238" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 15" name="HSMCI_FIFO15" offset="0x23C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 16" name="HSMCI_FIFO16" offset="0x240" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 17" name="HSMCI_FIFO17" offset="0x244" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 18" name="HSMCI_FIFO18" offset="0x248" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 19" name="HSMCI_FIFO19" offset="0x24C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 20" name="HSMCI_FIFO20" offset="0x250" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 21" name="HSMCI_FIFO21" offset="0x254" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 22" name="HSMCI_FIFO22" offset="0x258" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 23" name="HSMCI_FIFO23" offset="0x25C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 24" name="HSMCI_FIFO24" offset="0x260" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 25" name="HSMCI_FIFO25" offset="0x264" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 26" name="HSMCI_FIFO26" offset="0x268" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 27" name="HSMCI_FIFO27" offset="0x26C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 28" name="HSMCI_FIFO28" offset="0x270" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 29" name="HSMCI_FIFO29" offset="0x274" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 30" name="HSMCI_FIFO30" offset="0x278" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 31" name="HSMCI_FIFO31" offset="0x27C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 32" name="HSMCI_FIFO32" offset="0x280" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 33" name="HSMCI_FIFO33" offset="0x284" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 34" name="HSMCI_FIFO34" offset="0x288" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 35" name="HSMCI_FIFO35" offset="0x28C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 36" name="HSMCI_FIFO36" offset="0x290" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 37" name="HSMCI_FIFO37" offset="0x294" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 38" name="HSMCI_FIFO38" offset="0x298" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 39" name="HSMCI_FIFO39" offset="0x29C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 40" name="HSMCI_FIFO40" offset="0x2A0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 41" name="HSMCI_FIFO41" offset="0x2A4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 42" name="HSMCI_FIFO42" offset="0x2A8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 43" name="HSMCI_FIFO43" offset="0x2AC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 44" name="HSMCI_FIFO44" offset="0x2B0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 45" name="HSMCI_FIFO45" offset="0x2B4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 46" name="HSMCI_FIFO46" offset="0x2B8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 47" name="HSMCI_FIFO47" offset="0x2BC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 48" name="HSMCI_FIFO48" offset="0x2C0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 49" name="HSMCI_FIFO49" offset="0x2C4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 50" name="HSMCI_FIFO50" offset="0x2C8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 51" name="HSMCI_FIFO51" offset="0x2CC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 52" name="HSMCI_FIFO52" offset="0x2D0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 53" name="HSMCI_FIFO53" offset="0x2D4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 54" name="HSMCI_FIFO54" offset="0x2D8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 55" name="HSMCI_FIFO55" offset="0x2DC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 56" name="HSMCI_FIFO56" offset="0x2E0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 57" name="HSMCI_FIFO57" offset="0x2E4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 58" name="HSMCI_FIFO58" offset="0x2E8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 59" name="HSMCI_FIFO59" offset="0x2EC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 60" name="HSMCI_FIFO60" offset="0x2F0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 61" name="HSMCI_FIFO61" offset="0x2F4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 62" name="HSMCI_FIFO62" offset="0x2F8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 63" name="HSMCI_FIFO63" offset="0x2FC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 64" name="HSMCI_FIFO64" offset="0x300" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 65" name="HSMCI_FIFO65" offset="0x304" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 66" name="HSMCI_FIFO66" offset="0x308" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 67" name="HSMCI_FIFO67" offset="0x30C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 68" name="HSMCI_FIFO68" offset="0x310" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 69" name="HSMCI_FIFO69" offset="0x314" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 70" name="HSMCI_FIFO70" offset="0x318" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 71" name="HSMCI_FIFO71" offset="0x31C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 72" name="HSMCI_FIFO72" offset="0x320" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 73" name="HSMCI_FIFO73" offset="0x324" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 74" name="HSMCI_FIFO74" offset="0x328" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 75" name="HSMCI_FIFO75" offset="0x32C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 76" name="HSMCI_FIFO76" offset="0x330" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 77" name="HSMCI_FIFO77" offset="0x334" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 78" name="HSMCI_FIFO78" offset="0x338" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 79" name="HSMCI_FIFO79" offset="0x33C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 80" name="HSMCI_FIFO80" offset="0x340" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 81" name="HSMCI_FIFO81" offset="0x344" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 82" name="HSMCI_FIFO82" offset="0x348" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 83" name="HSMCI_FIFO83" offset="0x34C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 84" name="HSMCI_FIFO84" offset="0x350" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 85" name="HSMCI_FIFO85" offset="0x354" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 86" name="HSMCI_FIFO86" offset="0x358" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 87" name="HSMCI_FIFO87" offset="0x35C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 88" name="HSMCI_FIFO88" offset="0x360" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 89" name="HSMCI_FIFO89" offset="0x364" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 90" name="HSMCI_FIFO90" offset="0x368" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 91" name="HSMCI_FIFO91" offset="0x36C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 92" name="HSMCI_FIFO92" offset="0x370" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 93" name="HSMCI_FIFO93" offset="0x374" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 94" name="HSMCI_FIFO94" offset="0x378" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 95" name="HSMCI_FIFO95" offset="0x37C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 96" name="HSMCI_FIFO96" offset="0x380" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 97" name="HSMCI_FIFO97" offset="0x384" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 98" name="HSMCI_FIFO98" offset="0x388" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 99" name="HSMCI_FIFO99" offset="0x38C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 100" name="HSMCI_FIFO100" offset="0x390" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 101" name="HSMCI_FIFO101" offset="0x394" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 102" name="HSMCI_FIFO102" offset="0x398" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 103" name="HSMCI_FIFO103" offset="0x39C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 104" name="HSMCI_FIFO104" offset="0x3A0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 105" name="HSMCI_FIFO105" offset="0x3A4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 106" name="HSMCI_FIFO106" offset="0x3A8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 107" name="HSMCI_FIFO107" offset="0x3AC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 108" name="HSMCI_FIFO108" offset="0x3B0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 109" name="HSMCI_FIFO109" offset="0x3B4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 110" name="HSMCI_FIFO110" offset="0x3B8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 111" name="HSMCI_FIFO111" offset="0x3BC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 112" name="HSMCI_FIFO112" offset="0x3C0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 113" name="HSMCI_FIFO113" offset="0x3C4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 114" name="HSMCI_FIFO114" offset="0x3C8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 115" name="HSMCI_FIFO115" offset="0x3CC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 116" name="HSMCI_FIFO116" offset="0x3D0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 117" name="HSMCI_FIFO117" offset="0x3D4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 118" name="HSMCI_FIFO118" offset="0x3D8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 119" name="HSMCI_FIFO119" offset="0x3DC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 120" name="HSMCI_FIFO120" offset="0x3E0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 121" name="HSMCI_FIFO121" offset="0x3E4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 122" name="HSMCI_FIFO122" offset="0x3E8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 123" name="HSMCI_FIFO123" offset="0x3EC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 124" name="HSMCI_FIFO124" offset="0x3F0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 125" name="HSMCI_FIFO125" offset="0x3F4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 126" name="HSMCI_FIFO126" offset="0x3F8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 127" name="HSMCI_FIFO127" offset="0x3FC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 128" name="HSMCI_FIFO128" offset="0x400" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 129" name="HSMCI_FIFO129" offset="0x404" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 130" name="HSMCI_FIFO130" offset="0x408" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 131" name="HSMCI_FIFO131" offset="0x40C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 132" name="HSMCI_FIFO132" offset="0x410" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 133" name="HSMCI_FIFO133" offset="0x414" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 134" name="HSMCI_FIFO134" offset="0x418" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 135" name="HSMCI_FIFO135" offset="0x41C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 136" name="HSMCI_FIFO136" offset="0x420" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 137" name="HSMCI_FIFO137" offset="0x424" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 138" name="HSMCI_FIFO138" offset="0x428" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 139" name="HSMCI_FIFO139" offset="0x42C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 140" name="HSMCI_FIFO140" offset="0x430" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 141" name="HSMCI_FIFO141" offset="0x434" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 142" name="HSMCI_FIFO142" offset="0x438" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 143" name="HSMCI_FIFO143" offset="0x43C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 144" name="HSMCI_FIFO144" offset="0x440" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 145" name="HSMCI_FIFO145" offset="0x444" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 146" name="HSMCI_FIFO146" offset="0x448" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 147" name="HSMCI_FIFO147" offset="0x44C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 148" name="HSMCI_FIFO148" offset="0x450" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 149" name="HSMCI_FIFO149" offset="0x454" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 150" name="HSMCI_FIFO150" offset="0x458" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 151" name="HSMCI_FIFO151" offset="0x45C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 152" name="HSMCI_FIFO152" offset="0x460" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 153" name="HSMCI_FIFO153" offset="0x464" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 154" name="HSMCI_FIFO154" offset="0x468" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 155" name="HSMCI_FIFO155" offset="0x46C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 156" name="HSMCI_FIFO156" offset="0x470" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 157" name="HSMCI_FIFO157" offset="0x474" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 158" name="HSMCI_FIFO158" offset="0x478" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 159" name="HSMCI_FIFO159" offset="0x47C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 160" name="HSMCI_FIFO160" offset="0x480" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 161" name="HSMCI_FIFO161" offset="0x484" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 162" name="HSMCI_FIFO162" offset="0x488" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 163" name="HSMCI_FIFO163" offset="0x48C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 164" name="HSMCI_FIFO164" offset="0x490" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 165" name="HSMCI_FIFO165" offset="0x494" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 166" name="HSMCI_FIFO166" offset="0x498" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 167" name="HSMCI_FIFO167" offset="0x49C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 168" name="HSMCI_FIFO168" offset="0x4A0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 169" name="HSMCI_FIFO169" offset="0x4A4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 170" name="HSMCI_FIFO170" offset="0x4A8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 171" name="HSMCI_FIFO171" offset="0x4AC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 172" name="HSMCI_FIFO172" offset="0x4B0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 173" name="HSMCI_FIFO173" offset="0x4B4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 174" name="HSMCI_FIFO174" offset="0x4B8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 175" name="HSMCI_FIFO175" offset="0x4BC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 176" name="HSMCI_FIFO176" offset="0x4C0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 177" name="HSMCI_FIFO177" offset="0x4C4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 178" name="HSMCI_FIFO178" offset="0x4C8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 179" name="HSMCI_FIFO179" offset="0x4CC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 180" name="HSMCI_FIFO180" offset="0x4D0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 181" name="HSMCI_FIFO181" offset="0x4D4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 182" name="HSMCI_FIFO182" offset="0x4D8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 183" name="HSMCI_FIFO183" offset="0x4DC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 184" name="HSMCI_FIFO184" offset="0x4E0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 185" name="HSMCI_FIFO185" offset="0x4E4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 186" name="HSMCI_FIFO186" offset="0x4E8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 187" name="HSMCI_FIFO187" offset="0x4EC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 188" name="HSMCI_FIFO188" offset="0x4F0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 189" name="HSMCI_FIFO189" offset="0x4F4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 190" name="HSMCI_FIFO190" offset="0x4F8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 191" name="HSMCI_FIFO191" offset="0x4FC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 192" name="HSMCI_FIFO192" offset="0x500" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 193" name="HSMCI_FIFO193" offset="0x504" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 194" name="HSMCI_FIFO194" offset="0x508" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 195" name="HSMCI_FIFO195" offset="0x50C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 196" name="HSMCI_FIFO196" offset="0x510" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 197" name="HSMCI_FIFO197" offset="0x514" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 198" name="HSMCI_FIFO198" offset="0x518" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 199" name="HSMCI_FIFO199" offset="0x51C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 200" name="HSMCI_FIFO200" offset="0x520" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 201" name="HSMCI_FIFO201" offset="0x524" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 202" name="HSMCI_FIFO202" offset="0x528" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 203" name="HSMCI_FIFO203" offset="0x52C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 204" name="HSMCI_FIFO204" offset="0x530" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 205" name="HSMCI_FIFO205" offset="0x534" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 206" name="HSMCI_FIFO206" offset="0x538" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 207" name="HSMCI_FIFO207" offset="0x53C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 208" name="HSMCI_FIFO208" offset="0x540" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 209" name="HSMCI_FIFO209" offset="0x544" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 210" name="HSMCI_FIFO210" offset="0x548" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 211" name="HSMCI_FIFO211" offset="0x54C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 212" name="HSMCI_FIFO212" offset="0x550" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 213" name="HSMCI_FIFO213" offset="0x554" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 214" name="HSMCI_FIFO214" offset="0x558" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 215" name="HSMCI_FIFO215" offset="0x55C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 216" name="HSMCI_FIFO216" offset="0x560" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 217" name="HSMCI_FIFO217" offset="0x564" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 218" name="HSMCI_FIFO218" offset="0x568" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 219" name="HSMCI_FIFO219" offset="0x56C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 220" name="HSMCI_FIFO220" offset="0x570" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 221" name="HSMCI_FIFO221" offset="0x574" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 222" name="HSMCI_FIFO222" offset="0x578" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 223" name="HSMCI_FIFO223" offset="0x57C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 224" name="HSMCI_FIFO224" offset="0x580" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 225" name="HSMCI_FIFO225" offset="0x584" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 226" name="HSMCI_FIFO226" offset="0x588" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 227" name="HSMCI_FIFO227" offset="0x58C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 228" name="HSMCI_FIFO228" offset="0x590" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 229" name="HSMCI_FIFO229" offset="0x594" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 230" name="HSMCI_FIFO230" offset="0x598" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 231" name="HSMCI_FIFO231" offset="0x59C" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 232" name="HSMCI_FIFO232" offset="0x5A0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 233" name="HSMCI_FIFO233" offset="0x5A4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 234" name="HSMCI_FIFO234" offset="0x5A8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 235" name="HSMCI_FIFO235" offset="0x5AC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 236" name="HSMCI_FIFO236" offset="0x5B0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 237" name="HSMCI_FIFO237" offset="0x5B4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 238" name="HSMCI_FIFO238" offset="0x5B8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 239" name="HSMCI_FIFO239" offset="0x5BC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 240" name="HSMCI_FIFO240" offset="0x5C0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 241" name="HSMCI_FIFO241" offset="0x5C4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 242" name="HSMCI_FIFO242" offset="0x5C8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 243" name="HSMCI_FIFO243" offset="0x5CC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 244" name="HSMCI_FIFO244" offset="0x5D0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 245" name="HSMCI_FIFO245" offset="0x5D4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 246" name="HSMCI_FIFO246" offset="0x5D8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 247" name="HSMCI_FIFO247" offset="0x5DC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 248" name="HSMCI_FIFO248" offset="0x5E0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 249" name="HSMCI_FIFO249" offset="0x5E4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 250" name="HSMCI_FIFO250" offset="0x5E8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 251" name="HSMCI_FIFO251" offset="0x5EC" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 252" name="HSMCI_FIFO252" offset="0x5F0" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 253" name="HSMCI_FIFO253" offset="0x5F4" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 254" name="HSMCI_FIFO254" offset="0x5F8" rw="RW" size="4"/>
|
||
|
|
<register caption="FIFO Memory Aperture0 255" name="HSMCI_FIFO255" offset="0x5FC" rw="RW" size="4"/>
|
||
|
|
<register caption="Receive Pointer Register" name="HSMCI_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="HSMCI_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="HSMCI_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="HSMCI_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="HSMCI_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="HSMCI_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="HSMCI_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="HSMCI_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="HSMCI_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="HSMCI_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="HSMCI_DTOR__DTOMUL">
|
||
|
|
<value caption="DTOCYC" name="_1" value="0x0"/>
|
||
|
|
<value caption="DTOCYC x 16" name="_16" value="0x1"/>
|
||
|
|
<value caption="DTOCYC x 128" name="_128" value="0x2"/>
|
||
|
|
<value caption="DTOCYC x 256" name="_256" value="0x3"/>
|
||
|
|
<value caption="DTOCYC x 1024" name="_1024" value="0x4"/>
|
||
|
|
<value caption="DTOCYC x 4096" name="_4096" value="0x5"/>
|
||
|
|
<value caption="DTOCYC x 65536" name="_65536" value="0x6"/>
|
||
|
|
<value caption="DTOCYC x 1048576" name="_1048576" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_SDCR__SDCSEL">
|
||
|
|
<value caption="Slot A is selected." name="SLOTA" value="0x0"/>
|
||
|
|
<value caption="-" name="SLOTB" value="0x1"/>
|
||
|
|
<value caption="-" name="SLOTC" value="0x2"/>
|
||
|
|
<value caption="-" name="SLOTD" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_SDCR__SDCBUS">
|
||
|
|
<value caption="1 bit" name="_1" value="0x0"/>
|
||
|
|
<value caption="4 bit" name="_4" value="0x2"/>
|
||
|
|
<value caption="8 bit" name="_8" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__RSPTYP">
|
||
|
|
<value caption="No response." name="NORESP" value="0x0"/>
|
||
|
|
<value caption="48-bit response." name="_48_BIT" value="0x1"/>
|
||
|
|
<value caption="136-bit response." name="_136_BIT" value="0x2"/>
|
||
|
|
<value caption="R1b response type" name="R1B" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__SPCMD">
|
||
|
|
<value caption="Not a special CMD." name="STD" value="0x0"/>
|
||
|
|
<value caption="Initialization CMD: 74 clock cycles for initialization sequence." name="INIT" value="0x1"/>
|
||
|
|
<value caption="Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command." name="SYNC" value="0x2"/>
|
||
|
|
<value caption="CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line." name="CE_ATA" value="0x3"/>
|
||
|
|
<value caption="Interrupt command: Corresponds to the Interrupt Mode (CMD40)." name="IT_CMD" value="0x4"/>
|
||
|
|
<value caption="Interrupt response: Corresponds to the Interrupt Mode (CMD40)." name="IT_RESP" value="0x5"/>
|
||
|
|
<value caption="Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly." name="BOR" value="0x6"/>
|
||
|
|
<value caption="End Boot Operation. This command allows the host processor to terminate the boot operation mode." name="EBO" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__OPDCMD">
|
||
|
|
<value caption="Push pull command." name="PUSHPULL" value="0"/>
|
||
|
|
<value caption="Open drain command." name="OPENDRAIN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__MAXLAT">
|
||
|
|
<value caption="5-cycle max latency." name="_5" value="0"/>
|
||
|
|
<value caption="64-cycle max latency." name="_64" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__TRCMD">
|
||
|
|
<value caption="No data transfer" name="NO_DATA" value="0x0"/>
|
||
|
|
<value caption="Start data transfer" name="START_DATA" value="0x1"/>
|
||
|
|
<value caption="Stop data transfer" name="STOP_DATA" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__TRDIR">
|
||
|
|
<value caption="Write." name="WRITE" value="0"/>
|
||
|
|
<value caption="Read." name="READ" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__TRTYP">
|
||
|
|
<value caption="MMC/SDCard Single Block" name="SINGLE" value="0x0"/>
|
||
|
|
<value caption="MMC/SDCard Multiple Block" name="MULTIPLE" value="0x1"/>
|
||
|
|
<value caption="MMC Stream" name="STREAM" value="0x2"/>
|
||
|
|
<value caption="SDIO Byte" name="BYTE" value="0x4"/>
|
||
|
|
<value caption="SDIO Block" name="BLOCK" value="0x5"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__IOSPCMD">
|
||
|
|
<value caption="Not an SDIO Special Command" name="STD" value="0x0"/>
|
||
|
|
<value caption="SDIO Suspend Command" name="SUSPEND" value="0x1"/>
|
||
|
|
<value caption="SDIO Resume Command" name="RESUME" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CMDR__ATACS">
|
||
|
|
<value caption="Normal operation mode." name="NORMAL" value="0"/>
|
||
|
|
<value caption="This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR)." name="COMPLETION" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_BLKR__BCNT">
|
||
|
|
<value caption="MMC/SDCARD Multiple BlockFrom 1 to 65635: Value 0 corresponds to an infinite block transfer." name="MULTIPLE" value="0x0"/>
|
||
|
|
<value caption="SDIO ByteFrom 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.Values from 0x200 to 0xFFFF are forbidden." name="BYTE" value="0x4"/>
|
||
|
|
<value caption="SDIO BlockFrom 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.Values from 0x200 to 0xFFFF are forbidden." name="BLOCK" value="0x5"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_CSTOR__CSTOMUL">
|
||
|
|
<value caption="CSTOCYC x 1" name="_1" value="0x0"/>
|
||
|
|
<value caption="CSTOCYC x 16" name="_16" value="0x1"/>
|
||
|
|
<value caption="CSTOCYC x 128" name="_128" value="0x2"/>
|
||
|
|
<value caption="CSTOCYC x 256" name="_256" value="0x3"/>
|
||
|
|
<value caption="CSTOCYC x 1024" name="_1024" value="0x4"/>
|
||
|
|
<value caption="CSTOCYC x 4096" name="_4096" value="0x5"/>
|
||
|
|
<value caption="CSTOCYC x 65536" name="_65536" value="0x6"/>
|
||
|
|
<value caption="CSTOCYC x 1048576" name="_1048576" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="HSMCI_WPSR__WP_VS">
|
||
|
|
<value caption="No Write Protection Violation occurred since the last read of this register (WP_SR)" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Write Protection detected unauthorized attempt to write a control register had occurred (since the last read.)" name="WRITE" value="0x1"/>
|
||
|
|
<value caption="Software reset had been performed while Write Protection was enabled (since the last read)." name="RESET" value="0x2"/>
|
||
|
|
<value caption="Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read." name="BOTH" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="AHB Bus Matrix" name="MATRIX" version="6499A">
|
||
|
|
<register-group name="MATRIX">
|
||
|
|
<register caption="Master Configuration Register 0" name="MATRIX_MCFG0" offset="0x0" rw="RW" size="4">
|
||
|
|
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Master Configuration Register 1" name="MATRIX_MCFG1" offset="0x4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Master Configuration Register 2" name="MATRIX_MCFG2" offset="0x8" rw="RW" size="4">
|
||
|
|
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Master Configuration Register 3" name="MATRIX_MCFG3" offset="0xC" rw="RW" size="4">
|
||
|
|
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slave Configuration Register 0" name="MATRIX_SCFG0" offset="0x40" rw="RW" size="4">
|
||
|
|
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
|
||
|
|
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
|
||
|
|
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
|
||
|
|
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slave Configuration Register 1" name="MATRIX_SCFG1" offset="0x44" rw="RW" size="4">
|
||
|
|
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
|
||
|
|
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
|
||
|
|
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
|
||
|
|
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slave Configuration Register 2" name="MATRIX_SCFG2" offset="0x48" rw="RW" size="4">
|
||
|
|
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
|
||
|
|
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
|
||
|
|
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
|
||
|
|
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slave Configuration Register 3" name="MATRIX_SCFG3" offset="0x4C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
|
||
|
|
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
|
||
|
|
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
|
||
|
|
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slave Configuration Register 4" name="MATRIX_SCFG4" offset="0x50" rw="RW" size="4">
|
||
|
|
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
|
||
|
|
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
|
||
|
|
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
|
||
|
|
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Priority Register A for Slave 0" name="MATRIX_PRAS0" offset="0x0080" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
|
||
|
|
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
|
||
|
|
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
|
||
|
|
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
|
||
|
|
<bitfield caption="Master 4 Priority" mask="0x00030000" name="M4PR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Priority Register A for Slave 1" name="MATRIX_PRAS1" offset="0x0088" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
|
||
|
|
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
|
||
|
|
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
|
||
|
|
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
|
||
|
|
<bitfield caption="Master 4 Priority" mask="0x00030000" name="M4PR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Priority Register A for Slave 2" name="MATRIX_PRAS2" offset="0x0090" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
|
||
|
|
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
|
||
|
|
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
|
||
|
|
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
|
||
|
|
<bitfield caption="Master 4 Priority" mask="0x00030000" name="M4PR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Priority Register A for Slave 3" name="MATRIX_PRAS3" offset="0x0098" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
|
||
|
|
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
|
||
|
|
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
|
||
|
|
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
|
||
|
|
<bitfield caption="Master 4 Priority" mask="0x00030000" name="M4PR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Priority Register A for Slave 4" name="MATRIX_PRAS4" offset="0x00A0" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
|
||
|
|
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
|
||
|
|
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
|
||
|
|
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
|
||
|
|
<bitfield caption="Master 4 Priority" mask="0x00030000" name="M4PR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="System I/O Configuration register" name="CCFG_SYSIO" offset="0x0114" rw="RW" size="4">
|
||
|
|
<bitfield caption="PB4 or TDI Assignment" mask="0x00000010" name="SYSIO4"/>
|
||
|
|
<bitfield caption="PB5 or TDO/TRACESWO Assignment" mask="0x00000020" name="SYSIO5"/>
|
||
|
|
<bitfield caption="PB6 or TMS/SWDIO Assignment" mask="0x00000040" name="SYSIO6"/>
|
||
|
|
<bitfield caption="PB7 or TCK/SWCLK Assignment" mask="0x00000080" name="SYSIO7"/>
|
||
|
|
<bitfield caption="PB10 or DDM Assignment" mask="0x00000400" name="SYSIO10"/>
|
||
|
|
<bitfield caption="PB11 or DDP Assignment" mask="0x00000800" name="SYSIO11"/>
|
||
|
|
<bitfield caption="PB12 or ERASE Assignment" mask="0x00001000" name="SYSIO12"/>
|
||
|
|
</register>
|
||
|
|
<register caption="SMC Chip Select NAND Flash Assignment Register" name="CCFG_SMCNFCS" offset="0x011C" rw="RW" size="4">
|
||
|
|
<bitfield caption="SMC NAND Flash Chip Select 0 Assignment" mask="0x00000001" name="SMC_NFCS0"/>
|
||
|
|
<bitfield caption="SMC NAND Flash Chip Select 1 Assignment" mask="0x00000002" name="SMC_NFCS1"/>
|
||
|
|
<bitfield caption="SMC NAND Flash Chip Select 2 Assignment" mask="0x00000004" name="SMC_NFCS2"/>
|
||
|
|
<bitfield caption="SMC NAND Flash Chip Select 3 Assignment" mask="0x00000008" name="SMC_NFCS3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="MATRIX_WPMR" offset="0x1E4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect ENable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY (Write-only)" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="MATRIX_WPSR" offset="0x1E8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Peripheral DMA Controller" name="PDC" version="6031C">
|
||
|
|
<register-group name="PDC">
|
||
|
|
<register caption="Receive Pointer Register" name="PERIPH_RPR" offset="0x0" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="PERIPH_RCR" offset="0x4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="PERIPH_TPR" offset="0x8" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="PERIPH_TCR" offset="0xC" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="PERIPH_RNPR" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="PERIPH_RNCR" offset="0x14" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="PERIPH_TNPR" offset="0x18" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="PERIPH_TNCR" offset="0x1C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="PERIPH_PTCR" offset="0x20" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="PERIPH_PTSR" offset="0x24" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Parallel Input/Output Controller" name="PIO" version="11004F">
|
||
|
|
<register-group name="PIO">
|
||
|
|
<register caption="PIO Enable Register" name="PIO_PER" offset="0x0000" rw="W" size="4">
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="PIO Enable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PIO Disable Register" name="PIO_PDR" offset="0x0004" rw="W" size="4">
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="PIO Disable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PIO Status Register" name="PIO_PSR" offset="0x0008" rw="R" size="4">
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="PIO Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Enable Register" name="PIO_OER" offset="0x0010" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Enable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Disable Register" name="PIO_ODR" offset="0x0014" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Disable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Status Register" name="PIO_OSR" offset="0x0018" rw="R" size="4">
|
||
|
|
<bitfield caption="Output Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Glitch Input Filter Enable Register" name="PIO_IFER" offset="0x0020" rw="W" size="4">
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Filter Enable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Glitch Input Filter Disable Register" name="PIO_IFDR" offset="0x0024" rw="W" size="4">
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Filter Disable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Glitch Input Filter Status Register" name="PIO_IFSR" offset="0x0028" rw="R" size="4">
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Filer Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Set Output Data Register" name="PIO_SODR" offset="0x0030" rw="W" size="4">
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Set Output Data" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Clear Output Data Register" name="PIO_CODR" offset="0x0034" rw="W" size="4">
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Clear Output Data" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Data Status Register" name="PIO_ODSR" offset="0x0038" rw="RW" size="4">
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pin Data Status Register" name="PIO_PDSR" offset="0x003C" rw="R" size="4">
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Data Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="PIO_IER" offset="0x0040" rw="W" size="4">
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Enable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="PIO_IDR" offset="0x0044" rw="W" size="4">
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Disable" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="PIO_IMR" offset="0x0048" rw="R" size="4">
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Mask" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Status Register" name="PIO_ISR" offset="0x004C" rw="R" size="4">
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Input Change Interrupt Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Multi-driver Enable Register" name="PIO_MDER" offset="0x0050" rw="W" size="4">
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Multi Drive Enable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Multi-driver Disable Register" name="PIO_MDDR" offset="0x0054" rw="W" size="4">
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Multi Drive Disable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Multi-driver Status Register" name="PIO_MDSR" offset="0x0058" rw="R" size="4">
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Multi Drive Status." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pull-up Disable Register" name="PIO_PUDR" offset="0x0060" rw="W" size="4">
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Pull Up Disable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pull-up Enable Register" name="PIO_PUER" offset="0x0064" rw="W" size="4">
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Pull Up Enable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pad Pull-up Status Register" name="PIO_PUSR" offset="0x0068" rw="R" size="4">
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Pull Up Status." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Select Register 0" name="PIO_ABCDSR0" offset="0x70" rw="RW" size="4">
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Select Register 1" name="PIO_ABCDSR1" offset="0x74" rw="RW" size="4">
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Peripheral Select." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Input Filter Slow Clock Disable Register" name="PIO_IFSCDR" offset="0x0080" rw="W" size="4">
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="PIO Clock Glitch Filtering Select." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Input Filter Slow Clock Enable Register" name="PIO_IFSCER" offset="0x0084" rw="W" size="4">
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Debouncing Filtering Select." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Input Filter Slow Clock Status Register" name="PIO_IFSCSR" offset="0x0088" rw="R" size="4">
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Glitch or Debouncing Filter Selection Status" mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slow Clock Divider Debouncing Register" name="PIO_SCDR" offset="0x008C" rw="RW" size="4">
|
||
|
|
<bitfield mask="0x00003FFF" name="DIV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pad Pull-down Disable Register" name="PIO_PPDDR" offset="0x0090" rw="W" size="4">
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Pull Down Disable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pad Pull-down Enable Register" name="PIO_PPDER" offset="0x0094" rw="W" size="4">
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Pull Down Enable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Pad Pull-down Status Register" name="PIO_PPDSR" offset="0x0098" rw="R" size="4">
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Pull Down Status." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Write Enable" name="PIO_OWER" offset="0x00A0" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Write Enable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Write Disable" name="PIO_OWDR" offset="0x00A4" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Write Disable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Output Write Status Register" name="PIO_OWSR" offset="0x00A8" rw="R" size="4">
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Output Write Status." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Additional Interrupt Modes Enable Register" name="PIO_AIMER" offset="0x00B0" rw="W" size="4">
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Enable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Additional Interrupt Modes Disables Register" name="PIO_AIMDR" offset="0x00B4" rw="W" size="4">
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Additional Interrupt Modes Disable." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Additional Interrupt Modes Mask Register" name="PIO_AIMMR" offset="0x00B8" rw="R" size="4">
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Peripheral CD Status." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Edge Select Register" name="PIO_ESR" offset="0x00C0" rw="W" size="4">
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Edge Interrupt Selection." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Level Select Register" name="PIO_LSR" offset="0x00C4" rw="W" size="4">
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Level Interrupt Selection." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Edge/Level Status Register" name="PIO_ELSR" offset="0x00C8" rw="R" size="4">
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Edge/Level Interrupt source selection." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Falling Edge/Low Level Select Register" name="PIO_FELLSR" offset="0x00D0" rw="W" size="4">
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Falling Edge/Low Level Interrupt Selection." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Rising Edge/ High Level Select Register" name="PIO_REHLSR" offset="0x00D4" rw="W" size="4">
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Rising Edge /High Level Interrupt Selection." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Fall/Rise - Low/High Status Register" name="PIO_FRLHSR" offset="0x00D8" rw="R" size="4">
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Edge /Level Interrupt Source Selection." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Lock Status" name="PIO_LOCKSR" offset="0x00E0" rw="R" size="4">
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000001" name="P0"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000002" name="P1"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000004" name="P2"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000008" name="P3"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000010" name="P4"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000020" name="P5"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000040" name="P6"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000080" name="P7"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000100" name="P8"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000200" name="P9"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000400" name="P10"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00000800" name="P11"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00001000" name="P12"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00002000" name="P13"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00004000" name="P14"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00008000" name="P15"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00010000" name="P16"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00020000" name="P17"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00040000" name="P18"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00080000" name="P19"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00100000" name="P20"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00200000" name="P21"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00400000" name="P22"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x00800000" name="P23"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x01000000" name="P24"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x02000000" name="P25"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x04000000" name="P26"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x08000000" name="P27"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x10000000" name="P28"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x20000000" name="P29"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x40000000" name="P30"/>
|
||
|
|
<bitfield caption="Lock Status." mask="0x80000000" name="P31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="PIO_WPMR" offset="0x00E4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="PIO_WPSR" offset="0x00E8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Schmitt Trigger Register" name="PIO_SCHMITT" offset="0x0100" rw="RW" size="4">
|
||
|
|
<bitfield caption="" mask="0x00000001" name="SCHMITT0"/>
|
||
|
|
<bitfield caption="" mask="0x00000002" name="SCHMITT1"/>
|
||
|
|
<bitfield caption="" mask="0x00000004" name="SCHMITT2"/>
|
||
|
|
<bitfield caption="" mask="0x00000008" name="SCHMITT3"/>
|
||
|
|
<bitfield caption="" mask="0x00000010" name="SCHMITT4"/>
|
||
|
|
<bitfield caption="" mask="0x00000020" name="SCHMITT5"/>
|
||
|
|
<bitfield caption="" mask="0x00000040" name="SCHMITT6"/>
|
||
|
|
<bitfield caption="" mask="0x00000080" name="SCHMITT7"/>
|
||
|
|
<bitfield caption="" mask="0x00000100" name="SCHMITT8"/>
|
||
|
|
<bitfield caption="" mask="0x00000200" name="SCHMITT9"/>
|
||
|
|
<bitfield caption="" mask="0x00000400" name="SCHMITT10"/>
|
||
|
|
<bitfield caption="" mask="0x00000800" name="SCHMITT11"/>
|
||
|
|
<bitfield caption="" mask="0x00001000" name="SCHMITT12"/>
|
||
|
|
<bitfield caption="" mask="0x00002000" name="SCHMITT13"/>
|
||
|
|
<bitfield caption="" mask="0x00004000" name="SCHMITT14"/>
|
||
|
|
<bitfield caption="" mask="0x00008000" name="SCHMITT15"/>
|
||
|
|
<bitfield caption="" mask="0x00010000" name="SCHMITT16"/>
|
||
|
|
<bitfield caption="" mask="0x00020000" name="SCHMITT17"/>
|
||
|
|
<bitfield caption="" mask="0x00040000" name="SCHMITT18"/>
|
||
|
|
<bitfield caption="" mask="0x00080000" name="SCHMITT19"/>
|
||
|
|
<bitfield caption="" mask="0x00100000" name="SCHMITT20"/>
|
||
|
|
<bitfield caption="" mask="0x00200000" name="SCHMITT21"/>
|
||
|
|
<bitfield caption="" mask="0x00400000" name="SCHMITT22"/>
|
||
|
|
<bitfield caption="" mask="0x00800000" name="SCHMITT23"/>
|
||
|
|
<bitfield caption="" mask="0x01000000" name="SCHMITT24"/>
|
||
|
|
<bitfield caption="" mask="0x02000000" name="SCHMITT25"/>
|
||
|
|
<bitfield caption="" mask="0x04000000" name="SCHMITT26"/>
|
||
|
|
<bitfield caption="" mask="0x08000000" name="SCHMITT27"/>
|
||
|
|
<bitfield caption="" mask="0x10000000" name="SCHMITT28"/>
|
||
|
|
<bitfield caption="" mask="0x20000000" name="SCHMITT29"/>
|
||
|
|
<bitfield caption="" mask="0x40000000" name="SCHMITT30"/>
|
||
|
|
<bitfield caption="" mask="0x80000000" name="SCHMITT31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Parallel Capture Mode Register" name="PIO_PCMR" offset="0x150" rw="RW" size="4">
|
||
|
|
<bitfield caption="Parallel Capture Mode Enable" mask="0x00000001" name="PCEN"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Data Size" mask="0x00000030" name="DSIZE" values="PIO_PCMR__DSIZE"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Always Sampling" mask="0x00000200" name="ALWYS"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Half Sampling" mask="0x00000400" name="HALFS"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode First Sample" mask="0x00000800" name="FRSTS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Parallel Capture Interrupt Enable Register" name="PIO_PCIER" offset="0x154" rw="W" size="4">
|
||
|
|
<bitfield caption="Parallel Capture Mode Data Ready Interrupt Enable" mask="0x00000001" name="DRDY"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Overrun Error Interrupt Enable" mask="0x00000002" name="OVRE"/>
|
||
|
|
<bitfield caption="End of Reception Transfer Interrupt Enable" mask="0x00000004" name="ENDRX"/>
|
||
|
|
<bitfield caption="Reception Buffer Full Interrupt Enable" mask="0x00000008" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Parallel Capture Interrupt Disable Register" name="PIO_PCIDR" offset="0x158" rw="W" size="4">
|
||
|
|
<bitfield caption="Parallel Capture Mode Data Ready Interrupt Disable" mask="0x00000001" name="DRDY"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Overrun Error Interrupt Disable" mask="0x00000002" name="OVRE"/>
|
||
|
|
<bitfield caption="End of Reception Transfer Interrupt Disable" mask="0x00000004" name="ENDRX"/>
|
||
|
|
<bitfield caption="Reception Buffer Full Interrupt Disable" mask="0x00000008" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Parallel Capture Interrupt Mask Register" name="PIO_PCIMR" offset="0x15C" rw="R" size="4">
|
||
|
|
<bitfield caption="Parallel Capture Mode Data Ready Interrupt Mask" mask="0x00000001" name="DRDY"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Overrun Error Interrupt Mask" mask="0x00000002" name="OVRE"/>
|
||
|
|
<bitfield caption="End of Reception Transfer Interrupt Mask" mask="0x00000004" name="ENDRX"/>
|
||
|
|
<bitfield caption="Reception Buffer Full Interrupt Mask" mask="0x00000008" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Parallel Capture Interrupt Status Register" name="PIO_PCISR" offset="0x160" rw="R" size="4">
|
||
|
|
<bitfield caption="Parallel Capture Mode Data Ready" mask="0x00000001" name="DRDY"/>
|
||
|
|
<bitfield caption="Parallel Capture Mode Overrun Error." mask="0x00000002" name="OVRE"/>
|
||
|
|
<bitfield caption="End of Reception Transfer." mask="0x00000004" name="ENDRX"/>
|
||
|
|
<bitfield caption="Reception Buffer Full" mask="0x00000008" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Parallel Capture Reception Holding Register" name="PIO_PCRHR" offset="0x164" rw="R" size="4">
|
||
|
|
<bitfield caption="Parallel Capture Mode Reception Data." mask="0xFFFFFFFF" name="RDATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="PIO_RPR" offset="0x168" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="PIO_RCR" offset="0x16C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="PIO_RNPR" offset="0x178" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="PIO_RNCR" offset="0x17C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="PIO_PTCR" offset="0x188" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="PIO_PTSR" offset="0x18C" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="PIO_PCMR__DSIZE">
|
||
|
|
<value caption="The reception data in the PIO_PCRHR register is a BYTE (8-bit)" name="BYTE" value="0x0"/>
|
||
|
|
<value caption="The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit)" name="HALFWORD" value="0x1"/>
|
||
|
|
<value caption="The reception data in the PIO_PCRHR register is a WORD (32-bit)" name="WORD" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Power Management Controller" name="PMC" version="11116D">
|
||
|
|
<register-group name="PMC">
|
||
|
|
<register caption="System Clock Enable Register" name="PMC_SCER" offset="0x0000" rw="W" size="4">
|
||
|
|
<bitfield caption="USB Device Port Clock Enable" mask="0x00000080" name="UDP"/>
|
||
|
|
<bitfield caption="Programmable Clock 0 Output Enable" mask="0x00000100" name="PCK0"/>
|
||
|
|
<bitfield caption="Programmable Clock 1 Output Enable" mask="0x00000200" name="PCK1"/>
|
||
|
|
<bitfield caption="Programmable Clock 2 Output Enable" mask="0x00000400" name="PCK2"/>
|
||
|
|
</register>
|
||
|
|
<register caption="System Clock Disable Register" name="PMC_SCDR" offset="0x0004" rw="W" size="4">
|
||
|
|
<bitfield caption="USB Device Port Clock Disable" mask="0x00000080" name="UDP"/>
|
||
|
|
<bitfield caption="Programmable Clock 0 Output Disable" mask="0x00000100" name="PCK0"/>
|
||
|
|
<bitfield caption="Programmable Clock 1 Output Disable" mask="0x00000200" name="PCK1"/>
|
||
|
|
<bitfield caption="Programmable Clock 2 Output Disable" mask="0x00000400" name="PCK2"/>
|
||
|
|
</register>
|
||
|
|
<register caption="System Clock Status Register" name="PMC_SCSR" offset="0x0008" rw="R" size="4">
|
||
|
|
<bitfield caption="USB Device Port Clock Status" mask="0x00000080" name="UDP"/>
|
||
|
|
<bitfield caption="Programmable Clock 0 Output Status" mask="0x00000100" name="PCK0"/>
|
||
|
|
<bitfield caption="Programmable Clock 1 Output Status" mask="0x00000200" name="PCK1"/>
|
||
|
|
<bitfield caption="Programmable Clock 2 Output Status" mask="0x00000400" name="PCK2"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Clock Enable Register 0" name="PMC_PCER0" offset="0x0010" rw="W" size="4">
|
||
|
|
<bitfield caption="Peripheral Clock 2 Enable" mask="0x00000004" name="PID2"/>
|
||
|
|
<bitfield caption="Peripheral Clock 3 Enable" mask="0x00000008" name="PID3"/>
|
||
|
|
<bitfield caption="Peripheral Clock 4 Enable" mask="0x00000010" name="PID4"/>
|
||
|
|
<bitfield caption="Peripheral Clock 5 Enable" mask="0x00000020" name="PID5"/>
|
||
|
|
<bitfield caption="Peripheral Clock 6 Enable" mask="0x00000040" name="PID6"/>
|
||
|
|
<bitfield caption="Peripheral Clock 7 Enable" mask="0x00000080" name="PID7"/>
|
||
|
|
<bitfield caption="Peripheral Clock 8 Enable" mask="0x00000100" name="PID8"/>
|
||
|
|
<bitfield caption="Peripheral Clock 9 Enable" mask="0x00000200" name="PID9"/>
|
||
|
|
<bitfield caption="Peripheral Clock 10 Enable" mask="0x00000400" name="PID10"/>
|
||
|
|
<bitfield caption="Peripheral Clock 11 Enable" mask="0x00000800" name="PID11"/>
|
||
|
|
<bitfield caption="Peripheral Clock 12 Enable" mask="0x00001000" name="PID12"/>
|
||
|
|
<bitfield caption="Peripheral Clock 13 Enable" mask="0x00002000" name="PID13"/>
|
||
|
|
<bitfield caption="Peripheral Clock 14 Enable" mask="0x00004000" name="PID14"/>
|
||
|
|
<bitfield caption="Peripheral Clock 15 Enable" mask="0x00008000" name="PID15"/>
|
||
|
|
<bitfield caption="Peripheral Clock 16 Enable" mask="0x00010000" name="PID16"/>
|
||
|
|
<bitfield caption="Peripheral Clock 18 Enable" mask="0x00040000" name="PID18"/>
|
||
|
|
<bitfield caption="Peripheral Clock 19 Enable" mask="0x00080000" name="PID19"/>
|
||
|
|
<bitfield caption="Peripheral Clock 20 Enable" mask="0x00100000" name="PID20"/>
|
||
|
|
<bitfield caption="Peripheral Clock 21 Enable" mask="0x00200000" name="PID21"/>
|
||
|
|
<bitfield caption="Peripheral Clock 22 Enable" mask="0x00400000" name="PID22"/>
|
||
|
|
<bitfield caption="Peripheral Clock 23 Enable" mask="0x00800000" name="PID23"/>
|
||
|
|
<bitfield caption="Peripheral Clock 24 Enable" mask="0x01000000" name="PID24"/>
|
||
|
|
<bitfield caption="Peripheral Clock 25 Enable" mask="0x02000000" name="PID25"/>
|
||
|
|
<bitfield caption="Peripheral Clock 26 Enable" mask="0x04000000" name="PID26"/>
|
||
|
|
<bitfield caption="Peripheral Clock 27 Enable" mask="0x08000000" name="PID27"/>
|
||
|
|
<bitfield caption="Peripheral Clock 28 Enable" mask="0x10000000" name="PID28"/>
|
||
|
|
<bitfield caption="Peripheral Clock 29 Enable" mask="0x20000000" name="PID29"/>
|
||
|
|
<bitfield caption="Peripheral Clock 30 Enable" mask="0x40000000" name="PID30"/>
|
||
|
|
<bitfield caption="Peripheral Clock 31 Enable" mask="0x80000000" name="PID31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Clock Disable Register 0" name="PMC_PCDR0" offset="0x0014" rw="W" size="4">
|
||
|
|
<bitfield caption="Peripheral Clock 2 Disable" mask="0x00000004" name="PID2"/>
|
||
|
|
<bitfield caption="Peripheral Clock 3 Disable" mask="0x00000008" name="PID3"/>
|
||
|
|
<bitfield caption="Peripheral Clock 4 Disable" mask="0x00000010" name="PID4"/>
|
||
|
|
<bitfield caption="Peripheral Clock 5 Disable" mask="0x00000020" name="PID5"/>
|
||
|
|
<bitfield caption="Peripheral Clock 6 Disable" mask="0x00000040" name="PID6"/>
|
||
|
|
<bitfield caption="Peripheral Clock 7 Disable" mask="0x00000080" name="PID7"/>
|
||
|
|
<bitfield caption="Peripheral Clock 8 Disable" mask="0x00000100" name="PID8"/>
|
||
|
|
<bitfield caption="Peripheral Clock 9 Disable" mask="0x00000200" name="PID9"/>
|
||
|
|
<bitfield caption="Peripheral Clock 10 Disable" mask="0x00000400" name="PID10"/>
|
||
|
|
<bitfield caption="Peripheral Clock 11 Disable" mask="0x00000800" name="PID11"/>
|
||
|
|
<bitfield caption="Peripheral Clock 12 Disable" mask="0x00001000" name="PID12"/>
|
||
|
|
<bitfield caption="Peripheral Clock 13 Disable" mask="0x00002000" name="PID13"/>
|
||
|
|
<bitfield caption="Peripheral Clock 14 Disable" mask="0x00004000" name="PID14"/>
|
||
|
|
<bitfield caption="Peripheral Clock 15 Disable" mask="0x00008000" name="PID15"/>
|
||
|
|
<bitfield caption="Peripheral Clock 16 Disable" mask="0x00010000" name="PID16"/>
|
||
|
|
<bitfield caption="Peripheral Clock 18 Disable" mask="0x00040000" name="PID18"/>
|
||
|
|
<bitfield caption="Peripheral Clock 19 Disable" mask="0x00080000" name="PID19"/>
|
||
|
|
<bitfield caption="Peripheral Clock 20 Disable" mask="0x00100000" name="PID20"/>
|
||
|
|
<bitfield caption="Peripheral Clock 21 Disable" mask="0x00200000" name="PID21"/>
|
||
|
|
<bitfield caption="Peripheral Clock 22 Disable" mask="0x00400000" name="PID22"/>
|
||
|
|
<bitfield caption="Peripheral Clock 23 Disable" mask="0x00800000" name="PID23"/>
|
||
|
|
<bitfield caption="Peripheral Clock 24 Disable" mask="0x01000000" name="PID24"/>
|
||
|
|
<bitfield caption="Peripheral Clock 25 Disable" mask="0x02000000" name="PID25"/>
|
||
|
|
<bitfield caption="Peripheral Clock 26 Disable" mask="0x04000000" name="PID26"/>
|
||
|
|
<bitfield caption="Peripheral Clock 27 Disable" mask="0x08000000" name="PID27"/>
|
||
|
|
<bitfield caption="Peripheral Clock 28 Disable" mask="0x10000000" name="PID28"/>
|
||
|
|
<bitfield caption="Peripheral Clock 29 Disable" mask="0x20000000" name="PID29"/>
|
||
|
|
<bitfield caption="Peripheral Clock 30 Disable" mask="0x40000000" name="PID30"/>
|
||
|
|
<bitfield caption="Peripheral Clock 31 Disable" mask="0x80000000" name="PID31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Clock Status Register 0" name="PMC_PCSR0" offset="0x0018" rw="R" size="4">
|
||
|
|
<bitfield caption="Peripheral Clock 2 Status" mask="0x00000004" name="PID2"/>
|
||
|
|
<bitfield caption="Peripheral Clock 3 Status" mask="0x00000008" name="PID3"/>
|
||
|
|
<bitfield caption="Peripheral Clock 4 Status" mask="0x00000010" name="PID4"/>
|
||
|
|
<bitfield caption="Peripheral Clock 5 Status" mask="0x00000020" name="PID5"/>
|
||
|
|
<bitfield caption="Peripheral Clock 6 Status" mask="0x00000040" name="PID6"/>
|
||
|
|
<bitfield caption="Peripheral Clock 7 Status" mask="0x00000080" name="PID7"/>
|
||
|
|
<bitfield caption="Peripheral Clock 8 Status" mask="0x00000100" name="PID8"/>
|
||
|
|
<bitfield caption="Peripheral Clock 9 Status" mask="0x00000200" name="PID9"/>
|
||
|
|
<bitfield caption="Peripheral Clock 10 Status" mask="0x00000400" name="PID10"/>
|
||
|
|
<bitfield caption="Peripheral Clock 11 Status" mask="0x00000800" name="PID11"/>
|
||
|
|
<bitfield caption="Peripheral Clock 12 Status" mask="0x00001000" name="PID12"/>
|
||
|
|
<bitfield caption="Peripheral Clock 13 Status" mask="0x00002000" name="PID13"/>
|
||
|
|
<bitfield caption="Peripheral Clock 14 Status" mask="0x00004000" name="PID14"/>
|
||
|
|
<bitfield caption="Peripheral Clock 15 Status" mask="0x00008000" name="PID15"/>
|
||
|
|
<bitfield caption="Peripheral Clock 16 Status" mask="0x00010000" name="PID16"/>
|
||
|
|
<bitfield caption="Peripheral Clock 18 Status" mask="0x00040000" name="PID18"/>
|
||
|
|
<bitfield caption="Peripheral Clock 19 Status" mask="0x00080000" name="PID19"/>
|
||
|
|
<bitfield caption="Peripheral Clock 20 Status" mask="0x00100000" name="PID20"/>
|
||
|
|
<bitfield caption="Peripheral Clock 21 Status" mask="0x00200000" name="PID21"/>
|
||
|
|
<bitfield caption="Peripheral Clock 22 Status" mask="0x00400000" name="PID22"/>
|
||
|
|
<bitfield caption="Peripheral Clock 23 Status" mask="0x00800000" name="PID23"/>
|
||
|
|
<bitfield caption="Peripheral Clock 24 Status" mask="0x01000000" name="PID24"/>
|
||
|
|
<bitfield caption="Peripheral Clock 25 Status" mask="0x02000000" name="PID25"/>
|
||
|
|
<bitfield caption="Peripheral Clock 26 Status" mask="0x04000000" name="PID26"/>
|
||
|
|
<bitfield caption="Peripheral Clock 27 Status" mask="0x08000000" name="PID27"/>
|
||
|
|
<bitfield caption="Peripheral Clock 28 Status" mask="0x10000000" name="PID28"/>
|
||
|
|
<bitfield caption="Peripheral Clock 29 Status" mask="0x20000000" name="PID29"/>
|
||
|
|
<bitfield caption="Peripheral Clock 30 Status" mask="0x40000000" name="PID30"/>
|
||
|
|
<bitfield caption="Peripheral Clock 31 Status" mask="0x80000000" name="PID31"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Main Oscillator Register" name="CKGR_MOR" offset="0x0020" rw="RW" size="4">
|
||
|
|
<bitfield caption="Main Crystal Oscillator Enable" mask="0x00000001" name="MOSCXTEN"/>
|
||
|
|
<bitfield caption="Main Crystal Oscillator Bypass" mask="0x00000002" name="MOSCXTBY"/>
|
||
|
|
<bitfield caption="Main On-Chip RC Oscillator Enable" mask="0x00000008" name="MOSCRCEN"/>
|
||
|
|
<bitfield caption="Main On-Chip RC Oscillator Frequency Selection" mask="0x00000070" name="MOSCRCF" values="CKGR_MOR__MOSCRCF"/>
|
||
|
|
<bitfield caption="Main Crystal Oscillator Start-up Time" mask="0x0000FF00" name="MOSCXTST"/>
|
||
|
|
<bitfield caption="Password" mask="0x00FF0000" name="KEY"/>
|
||
|
|
<bitfield caption="Main Oscillator Selection" mask="0x01000000" name="MOSCSEL"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Enable" mask="0x02000000" name="CFDEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Main Clock Frequency Register" name="CKGR_MCFR" offset="0x0024" rw="RW" size="4">
|
||
|
|
<bitfield caption="Main Clock Frequency" mask="0x0000FFFF" name="MAINF"/>
|
||
|
|
<bitfield caption="Main Clock Ready" mask="0x00010000" name="MAINFRDY"/>
|
||
|
|
<bitfield caption="RC Oscillator Frequency Measure (write-only)" mask="0x00100000" name="RCMEAS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PLLA Register" name="CKGR_PLLAR" offset="0x0028" rw="RW" size="4">
|
||
|
|
<bitfield caption="Divider" mask="0x000000FF" name="DIVA"/>
|
||
|
|
<bitfield caption="PLLA Counter" mask="0x00003F00" name="PLLACOUNT"/>
|
||
|
|
<bitfield caption="PLLA Multiplier" mask="0x07FF0000" name="MULA"/>
|
||
|
|
<bitfield caption="Must Be Set to 1" mask="0x20000000" name="ONE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PLLB Register" name="CKGR_PLLBR" offset="0x002C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Divider" mask="0x000000FF" name="DIVB"/>
|
||
|
|
<bitfield caption="PLLB Counter" mask="0x00003F00" name="PLLBCOUNT"/>
|
||
|
|
<bitfield caption="PLLB Multiplier" mask="0x07FF0000" name="MULB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Master Clock Register" name="PMC_MCKR" offset="0x0030" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master Clock Source Selection" mask="0x00000003" name="CSS" values="PMC_MCKR__CSS"/>
|
||
|
|
<bitfield caption="Processor Clock Prescaler" mask="0x00000070" name="PRES" values="PMC_MCKR__PRES"/>
|
||
|
|
<bitfield caption="PLLA Divisor by 2" mask="0x00001000" name="PLLADIV2"/>
|
||
|
|
<bitfield caption="PLLB Divisor by 2" mask="0x00002000" name="PLLBDIV2"/>
|
||
|
|
</register>
|
||
|
|
<register caption="USB Clock Register" name="PMC_USB" offset="0x0038" rw="RW" size="4">
|
||
|
|
<bitfield caption="USB Input Clock Selection" mask="0x00000001" name="USBS"/>
|
||
|
|
<bitfield caption="Divider for USB Clock." mask="0x00000F00" name="USBDIV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Programmable Clock 0 Register 0" name="PMC_PCK0" offset="0x40" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master Clock Source Selection" mask="0x00000007" name="CSS" values="PMC_PCK__CSS"/>
|
||
|
|
<bitfield caption="Programmable Clock Prescaler" mask="0x00000070" name="PRES" values="PMC_PCK__PRES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Programmable Clock 0 Register 1" name="PMC_PCK1" offset="0x44" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master Clock Source Selection" mask="0x00000007" name="CSS" values="PMC_PCK__CSS"/>
|
||
|
|
<bitfield caption="Programmable Clock Prescaler" mask="0x00000070" name="PRES" values="PMC_PCK__PRES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Programmable Clock 0 Register 2" name="PMC_PCK2" offset="0x48" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master Clock Source Selection" mask="0x00000007" name="CSS" values="PMC_PCK__CSS"/>
|
||
|
|
<bitfield caption="Programmable Clock Prescaler" mask="0x00000070" name="PRES" values="PMC_PCK__PRES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="PMC_IER" offset="0x0060" rw="W" size="4">
|
||
|
|
<bitfield caption="Main Crystal Oscillator Status Interrupt Enable" mask="0x00000001" name="MOSCXTS"/>
|
||
|
|
<bitfield caption="PLLA Lock Interrupt Enable" mask="0x00000002" name="LOCKA"/>
|
||
|
|
<bitfield caption="PLLB Lock Interrupt Enable" mask="0x00000004" name="LOCKB"/>
|
||
|
|
<bitfield caption="Master Clock Ready Interrupt Enable" mask="0x00000008" name="MCKRDY"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 0 Interrupt Enable" mask="0x00000100" name="PCKRDY0"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 1 Interrupt Enable" mask="0x00000200" name="PCKRDY1"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 2 Interrupt Enable" mask="0x00000400" name="PCKRDY2"/>
|
||
|
|
<bitfield caption="Main Oscillator Selection Status Interrupt Enable" mask="0x00010000" name="MOSCSELS"/>
|
||
|
|
<bitfield caption="Main On-Chip RC Status Interrupt Enable" mask="0x00020000" name="MOSCRCS"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Event Interrupt Enable" mask="0x00040000" name="CFDEV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="PMC_IDR" offset="0x0064" rw="W" size="4">
|
||
|
|
<bitfield caption="Main Crystal Oscillator Status Interrupt Disable" mask="0x00000001" name="MOSCXTS"/>
|
||
|
|
<bitfield caption="PLLA Lock Interrupt Disable" mask="0x00000002" name="LOCKA"/>
|
||
|
|
<bitfield caption="PLLB Lock Interrupt Disable" mask="0x00000004" name="LOCKB"/>
|
||
|
|
<bitfield caption="Master Clock Ready Interrupt Disable" mask="0x00000008" name="MCKRDY"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 0 Interrupt Disable" mask="0x00000100" name="PCKRDY0"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 1 Interrupt Disable" mask="0x00000200" name="PCKRDY1"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 2 Interrupt Disable" mask="0x00000400" name="PCKRDY2"/>
|
||
|
|
<bitfield caption="Main Oscillator Selection Status Interrupt Disable" mask="0x00010000" name="MOSCSELS"/>
|
||
|
|
<bitfield caption="Main On-Chip RC Status Interrupt Disable" mask="0x00020000" name="MOSCRCS"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Event Interrupt Disable" mask="0x00040000" name="CFDEV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="PMC_SR" offset="0x0068" rw="R" size="4">
|
||
|
|
<bitfield caption="Main XTAL Oscillator Status" mask="0x00000001" name="MOSCXTS"/>
|
||
|
|
<bitfield caption="PLLA Lock Status" mask="0x00000002" name="LOCKA"/>
|
||
|
|
<bitfield caption="PLLB Lock Status" mask="0x00000004" name="LOCKB"/>
|
||
|
|
<bitfield caption="Master Clock Status" mask="0x00000008" name="MCKRDY"/>
|
||
|
|
<bitfield caption="Slow Clock Oscillator Selection" mask="0x00000080" name="OSCSELS"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready Status" mask="0x00000100" name="PCKRDY0"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready Status" mask="0x00000200" name="PCKRDY1"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready Status" mask="0x00000400" name="PCKRDY2"/>
|
||
|
|
<bitfield caption="Main Oscillator Selection Status" mask="0x00010000" name="MOSCSELS"/>
|
||
|
|
<bitfield caption="Main On-Chip RC Oscillator Status" mask="0x00020000" name="MOSCRCS"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Event" mask="0x00040000" name="CFDEV"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Status" mask="0x00080000" name="CFDS"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Fault Output Status" mask="0x00100000" name="FOS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="PMC_IMR" offset="0x006C" rw="R" size="4">
|
||
|
|
<bitfield caption="Main Crystal Oscillator Status Interrupt Mask" mask="0x00000001" name="MOSCXTS"/>
|
||
|
|
<bitfield caption="PLLA Lock Interrupt Mask" mask="0x00000002" name="LOCKA"/>
|
||
|
|
<bitfield caption="PLLB Lock Interrupt Mask" mask="0x00000004" name="LOCKB"/>
|
||
|
|
<bitfield caption="Master Clock Ready Interrupt Mask" mask="0x00000008" name="MCKRDY"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 0 Interrupt Mask" mask="0x00000100" name="PCKRDY0"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 1 Interrupt Mask" mask="0x00000200" name="PCKRDY1"/>
|
||
|
|
<bitfield caption="Programmable Clock Ready 2 Interrupt Mask" mask="0x00000400" name="PCKRDY2"/>
|
||
|
|
<bitfield caption="Main Oscillator Selection Status Interrupt Mask" mask="0x00010000" name="MOSCSELS"/>
|
||
|
|
<bitfield caption="Main On-Chip RC Status Interrupt Mask" mask="0x00020000" name="MOSCRCS"/>
|
||
|
|
<bitfield caption="Clock Failure Detector Event Interrupt Mask" mask="0x00040000" name="CFDEV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Fast Startup Mode Register" name="PMC_FSMR" offset="0x0070" rw="RW" size="4">
|
||
|
|
<bitfield caption="Fast Startup Input Enable 0" mask="0x00000001" name="FSTT0"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 1" mask="0x00000002" name="FSTT1"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 2" mask="0x00000004" name="FSTT2"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 3" mask="0x00000008" name="FSTT3"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 4" mask="0x00000010" name="FSTT4"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 5" mask="0x00000020" name="FSTT5"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 6" mask="0x00000040" name="FSTT6"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 7" mask="0x00000080" name="FSTT7"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 8" mask="0x00000100" name="FSTT8"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 9" mask="0x00000200" name="FSTT9"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 10" mask="0x00000400" name="FSTT10"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 11" mask="0x00000800" name="FSTT11"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 12" mask="0x00001000" name="FSTT12"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 13" mask="0x00002000" name="FSTT13"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 14" mask="0x00004000" name="FSTT14"/>
|
||
|
|
<bitfield caption="Fast Startup Input Enable 15" mask="0x00008000" name="FSTT15"/>
|
||
|
|
<bitfield caption="RTT Alarm Enable" mask="0x00010000" name="RTTAL"/>
|
||
|
|
<bitfield caption="RTC Alarm Enable" mask="0x00020000" name="RTCAL"/>
|
||
|
|
<bitfield caption="USB Alarm Enable" mask="0x00040000" name="USBAL"/>
|
||
|
|
<bitfield caption="Low Power Mode" mask="0x00100000" name="LPM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Fast Startup Polarity Register" name="PMC_FSPR" offset="0x0074" rw="RW" size="4">
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000001" name="FSTP0"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000002" name="FSTP1"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000004" name="FSTP2"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000008" name="FSTP3"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000010" name="FSTP4"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000020" name="FSTP5"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000040" name="FSTP6"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000080" name="FSTP7"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000100" name="FSTP8"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000200" name="FSTP9"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000400" name="FSTP10"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00000800" name="FSTP11"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00001000" name="FSTP12"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00002000" name="FSTP13"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00004000" name="FSTP14"/>
|
||
|
|
<bitfield caption="Fast Startup Input Polarityx" mask="0x00008000" name="FSTP15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Fault Output Clear Register" name="PMC_FOCR" offset="0x0078" rw="W" size="4">
|
||
|
|
<bitfield caption="Fault Output Clear" mask="0x00000001" name="FOCLR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="PMC_WPMR" offset="0x00E4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="PMC_WPSR" offset="0x00E8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Clock Enable Register 1" name="PMC_PCER1" offset="0x0100" rw="W" size="4">
|
||
|
|
<bitfield caption="Peripheral Clock 32 Enable" mask="0x00000001" name="PID32"/>
|
||
|
|
<bitfield caption="Peripheral Clock 33 Enable" mask="0x00000002" name="PID33"/>
|
||
|
|
<bitfield caption="Peripheral Clock 34 Enable" mask="0x00000004" name="PID34"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Clock Disable Register 1" name="PMC_PCDR1" offset="0x0104" rw="W" size="4">
|
||
|
|
<bitfield caption="Peripheral Clock 32 Disable" mask="0x00000001" name="PID32"/>
|
||
|
|
<bitfield caption="Peripheral Clock 33 Disable" mask="0x00000002" name="PID33"/>
|
||
|
|
<bitfield caption="Peripheral Clock 34 Disable" mask="0x00000004" name="PID34"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Peripheral Clock Status Register 1" name="PMC_PCSR1" offset="0x0108" rw="R" size="4">
|
||
|
|
<bitfield caption="Peripheral Clock 32 Status" mask="0x00000001" name="PID32"/>
|
||
|
|
<bitfield caption="Peripheral Clock 33 Status" mask="0x00000002" name="PID33"/>
|
||
|
|
<bitfield caption="Peripheral Clock 34 Status" mask="0x00000004" name="PID34"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Oscillator Calibration Register" name="PMC_OCR" offset="0x0110" rw="RW" size="4">
|
||
|
|
<bitfield caption="RC Oscillator Calibration bits for 4 Mhz" mask="0x0000007F" name="CAL4"/>
|
||
|
|
<bitfield caption="Selection of RC Oscillator Calibration bits for 4 Mhz" mask="0x00000080" name="SEL4"/>
|
||
|
|
<bitfield caption="RC Oscillator Calibration bits for 8 Mhz" mask="0x00007F00" name="CAL8"/>
|
||
|
|
<bitfield caption="Selection of RC Oscillator Calibration bits for 8 Mhz" mask="0x00008000" name="SEL8"/>
|
||
|
|
<bitfield caption="RC Oscillator Calibration bits for 12 Mhz" mask="0x007F0000" name="CAL12"/>
|
||
|
|
<bitfield caption="Selection of RC Oscillator Calibration bits for 12 Mhz" mask="0x00800000" name="SEL12"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="CKGR_MOR__MOSCRCF">
|
||
|
|
<value caption="The Fast RC Oscillator Frequency is at 4 MHz (default)" name="_4_MHz" value="0x0"/>
|
||
|
|
<value caption="The Fast RC Oscillator Frequency is at 8 MHz" name="_8_MHz" value="0x1"/>
|
||
|
|
<value caption="The Fast RC Oscillator Frequency is at 12 MHz" name="_12_MHz" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_MCKR__CSS">
|
||
|
|
<value caption="Slow Clock is selected" name="SLOW_CLK" value="0x0"/>
|
||
|
|
<value caption="Main Clock is selected" name="MAIN_CLK" value="0x1"/>
|
||
|
|
<value caption="PLLA Clock is selected" name="PLLA_CLK" value="0x2"/>
|
||
|
|
<value caption="PLLBClock is selected" name="PLLB_CLK" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_MCKR__PRES">
|
||
|
|
<value caption="Selected clock" name="CLK_1" value="0x0"/>
|
||
|
|
<value caption="Selected clock divided by 2" name="CLK_2" value="0x1"/>
|
||
|
|
<value caption="Selected clock divided by 4" name="CLK_4" value="0x2"/>
|
||
|
|
<value caption="Selected clock divided by 8" name="CLK_8" value="0x3"/>
|
||
|
|
<value caption="Selected clock divided by 16" name="CLK_16" value="0x4"/>
|
||
|
|
<value caption="Selected clock divided by 32" name="CLK_32" value="0x5"/>
|
||
|
|
<value caption="Selected clock divided by 64" name="CLK_64" value="0x6"/>
|
||
|
|
<value caption="Selected clock divided by 3" name="CLK_3" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_PCK__CSS">
|
||
|
|
<value caption="Slow Clock is selected" name="SLOW_CLK" value="0x0"/>
|
||
|
|
<value caption="Main Clock is selected" name="MAIN_CLK" value="0x1"/>
|
||
|
|
<value caption="PLLA Clock is selected" name="PLLA_CLK" value="0x2"/>
|
||
|
|
<value caption="PLLB Clock is selected" name="PLLB_CLK" value="0x3"/>
|
||
|
|
<value caption="Master Clock is selected" name="MCK" value="0x4"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_PCK__PRES">
|
||
|
|
<value caption="Selected clock" name="CLK_1" value="0x0"/>
|
||
|
|
<value caption="Selected clock divided by 2" name="CLK_2" value="0x1"/>
|
||
|
|
<value caption="Selected clock divided by 4" name="CLK_4" value="0x2"/>
|
||
|
|
<value caption="Selected clock divided by 8" name="CLK_8" value="0x3"/>
|
||
|
|
<value caption="Selected clock divided by 16" name="CLK_16" value="0x4"/>
|
||
|
|
<value caption="Selected clock divided by 32" name="CLK_32" value="0x5"/>
|
||
|
|
<value caption="Selected clock divided by 64" name="CLK_64" value="0x6"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_PCK__CSS">
|
||
|
|
<value caption="Slow Clock is selected" name="SLOW_CLK" value="0x0"/>
|
||
|
|
<value caption="Main Clock is selected" name="MAIN_CLK" value="0x1"/>
|
||
|
|
<value caption="PLLA Clock is selected" name="PLLA_CLK" value="0x2"/>
|
||
|
|
<value caption="PLLB Clock is selected" name="PLLB_CLK" value="0x3"/>
|
||
|
|
<value caption="Master Clock is selected" name="MCK" value="0x4"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_PCK__PRES">
|
||
|
|
<value caption="Selected clock" name="CLK_1" value="0x0"/>
|
||
|
|
<value caption="Selected clock divided by 2" name="CLK_2" value="0x1"/>
|
||
|
|
<value caption="Selected clock divided by 4" name="CLK_4" value="0x2"/>
|
||
|
|
<value caption="Selected clock divided by 8" name="CLK_8" value="0x3"/>
|
||
|
|
<value caption="Selected clock divided by 16" name="CLK_16" value="0x4"/>
|
||
|
|
<value caption="Selected clock divided by 32" name="CLK_32" value="0x5"/>
|
||
|
|
<value caption="Selected clock divided by 64" name="CLK_64" value="0x6"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_PCK__CSS">
|
||
|
|
<value caption="Slow Clock is selected" name="SLOW_CLK" value="0x0"/>
|
||
|
|
<value caption="Main Clock is selected" name="MAIN_CLK" value="0x1"/>
|
||
|
|
<value caption="PLLA Clock is selected" name="PLLA_CLK" value="0x2"/>
|
||
|
|
<value caption="PLLB Clock is selected" name="PLLB_CLK" value="0x3"/>
|
||
|
|
<value caption="Master Clock is selected" name="MCK" value="0x4"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PMC_PCK__PRES">
|
||
|
|
<value caption="Selected clock" name="CLK_1" value="0x0"/>
|
||
|
|
<value caption="Selected clock divided by 2" name="CLK_2" value="0x1"/>
|
||
|
|
<value caption="Selected clock divided by 4" name="CLK_4" value="0x2"/>
|
||
|
|
<value caption="Selected clock divided by 8" name="CLK_8" value="0x3"/>
|
||
|
|
<value caption="Selected clock divided by 16" name="CLK_16" value="0x4"/>
|
||
|
|
<value caption="Selected clock divided by 32" name="CLK_32" value="0x5"/>
|
||
|
|
<value caption="Selected clock divided by 64" name="CLK_64" value="0x6"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Pulse Width Modulation Controller" name="PWM" version="6343H">
|
||
|
|
<register-group name="PWM">
|
||
|
|
<register caption="PWM Clock Register" name="PWM_CLK" offset="0x00" rw="RW" size="4">
|
||
|
|
<bitfield caption="CLKA, CLKB Divide Factor" mask="0x000000FF" name="DIVA"/>
|
||
|
|
<bitfield caption="CLKA, CLKB Source Clock Selection" mask="0x00000F00" name="PREA"/>
|
||
|
|
<bitfield caption="CLKA, CLKB Divide Factor" mask="0x00FF0000" name="DIVB"/>
|
||
|
|
<bitfield caption="CLKA, CLKB Source Clock Selection" mask="0x0F000000" name="PREB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Enable Register" name="PWM_ENA" offset="0x04" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000008" name="CHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Disable Register" name="PWM_DIS" offset="0x08" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000008" name="CHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Status Register" name="PWM_SR" offset="0x0C" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Channel ID" mask="0x00000008" name="CHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Enable Register 1" name="PWM_IER1" offset="0x10" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Event on Channel 0 Interrupt Enable" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 1 Interrupt Enable" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 2 Interrupt Enable" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 3 Interrupt Enable" mask="0x00000008" name="CHID3"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 0 Interrupt Enable" mask="0x00010000" name="FCHID0"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 1 Interrupt Enable" mask="0x00020000" name="FCHID1"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 2 Interrupt Enable" mask="0x00040000" name="FCHID2"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 3 Interrupt Enable" mask="0x00080000" name="FCHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Disable Register 1" name="PWM_IDR1" offset="0x14" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Event on Channel 0 Interrupt Disable" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 1 Interrupt Disable" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 2 Interrupt Disable" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 3 Interrupt Disable" mask="0x00000008" name="CHID3"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 0 Interrupt Disable" mask="0x00010000" name="FCHID0"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 1 Interrupt Disable" mask="0x00020000" name="FCHID1"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 2 Interrupt Disable" mask="0x00040000" name="FCHID2"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 3 Interrupt Disable" mask="0x00080000" name="FCHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Mask Register 1" name="PWM_IMR1" offset="0x18" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Event on Channel 0 Interrupt Mask" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 1 Interrupt Mask" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 2 Interrupt Mask" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 3 Interrupt Mask" mask="0x00000008" name="CHID3"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 0 Interrupt Mask" mask="0x00010000" name="FCHID0"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 1 Interrupt Mask" mask="0x00020000" name="FCHID1"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 2 Interrupt Mask" mask="0x00040000" name="FCHID2"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 3 Interrupt Mask" mask="0x00080000" name="FCHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Status Register 1" name="PWM_ISR1" offset="0x1C" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Event on Channel 0" mask="0x00000001" name="CHID0"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 1" mask="0x00000002" name="CHID1"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 2" mask="0x00000004" name="CHID2"/>
|
||
|
|
<bitfield caption="Counter Event on Channel 3" mask="0x00000008" name="CHID3"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 0" mask="0x00010000" name="FCHID0"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 1" mask="0x00020000" name="FCHID1"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 2" mask="0x00040000" name="FCHID2"/>
|
||
|
|
<bitfield caption="Fault Protection Trigger on Channel 3" mask="0x00080000" name="FCHID3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Sync Channels Mode Register" name="PWM_SCM" offset="0x20" rw="RW" size="4">
|
||
|
|
<bitfield caption="Synchronous Channel 0" mask="0x00000001" name="SYNC0"/>
|
||
|
|
<bitfield caption="Synchronous Channel 1" mask="0x00000002" name="SYNC1"/>
|
||
|
|
<bitfield caption="Synchronous Channel 2" mask="0x00000004" name="SYNC2"/>
|
||
|
|
<bitfield caption="Synchronous Channel 3" mask="0x00000008" name="SYNC3"/>
|
||
|
|
<bitfield caption="Synchronous Channels Update Mode" mask="0x00030000" name="UPDM" values="PWM_SCM__UPDM"/>
|
||
|
|
<bitfield caption="PDC Transfer Request Mode" mask="0x00100000" name="PTRM"/>
|
||
|
|
<bitfield caption="PDC Transfer Request Comparison Selection" mask="0x00E00000" name="PTRCS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Sync Channels Update Control Register" name="PWM_SCUC" offset="0x28" rw="RW" size="4">
|
||
|
|
<bitfield caption="Synchronous Channels Update Unlock" mask="0x00000001" name="UPDULOCK"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Sync Channels Update Period Register" name="PWM_SCUP" offset="0x2C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Update Period" mask="0x0000000F" name="UPR"/>
|
||
|
|
<bitfield caption="Update Period Counter" mask="0x000000F0" name="UPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Sync Channels Update Period Update Register" name="PWM_SCUPUPD" offset="0x30" rw="W" size="4">
|
||
|
|
<bitfield caption="Update Period Update" mask="0x0000000F" name="UPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Enable Register 2" name="PWM_IER2" offset="0x34" rw="W" size="4">
|
||
|
|
<bitfield caption="Write Ready for Synchronous Channels Update Interrupt Enable" mask="0x00000001" name="WRDY"/>
|
||
|
|
<bitfield caption="PDC End of TX Buffer Interrupt Enable" mask="0x00000002" name="ENDTX"/>
|
||
|
|
<bitfield caption="PDC TX Buffer Empty Interrupt Enable" mask="0x00000004" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Synchronous Channels Update Underrun Error Interrupt Enable" mask="0x00000008" name="UNRE"/>
|
||
|
|
<bitfield caption="Comparison 0 Match Interrupt Enable" mask="0x00000100" name="CMPM0"/>
|
||
|
|
<bitfield caption="Comparison 1 Match Interrupt Enable" mask="0x00000200" name="CMPM1"/>
|
||
|
|
<bitfield caption="Comparison 2 Match Interrupt Enable" mask="0x00000400" name="CMPM2"/>
|
||
|
|
<bitfield caption="Comparison 3 Match Interrupt Enable" mask="0x00000800" name="CMPM3"/>
|
||
|
|
<bitfield caption="Comparison 4 Match Interrupt Enable" mask="0x00001000" name="CMPM4"/>
|
||
|
|
<bitfield caption="Comparison 5 Match Interrupt Enable" mask="0x00002000" name="CMPM5"/>
|
||
|
|
<bitfield caption="Comparison 6 Match Interrupt Enable" mask="0x00004000" name="CMPM6"/>
|
||
|
|
<bitfield caption="Comparison 7 Match Interrupt Enable" mask="0x00008000" name="CMPM7"/>
|
||
|
|
<bitfield caption="Comparison 0 Update Interrupt Enable" mask="0x00010000" name="CMPU0"/>
|
||
|
|
<bitfield caption="Comparison 1 Update Interrupt Enable" mask="0x00020000" name="CMPU1"/>
|
||
|
|
<bitfield caption="Comparison 2 Update Interrupt Enable" mask="0x00040000" name="CMPU2"/>
|
||
|
|
<bitfield caption="Comparison 3 Update Interrupt Enable" mask="0x00080000" name="CMPU3"/>
|
||
|
|
<bitfield caption="Comparison 4 Update Interrupt Enable" mask="0x00100000" name="CMPU4"/>
|
||
|
|
<bitfield caption="Comparison 5 Update Interrupt Enable" mask="0x00200000" name="CMPU5"/>
|
||
|
|
<bitfield caption="Comparison 6 Update Interrupt Enable" mask="0x00400000" name="CMPU6"/>
|
||
|
|
<bitfield caption="Comparison 7 Update Interrupt Enable" mask="0x00800000" name="CMPU7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Disable Register 2" name="PWM_IDR2" offset="0x38" rw="W" size="4">
|
||
|
|
<bitfield caption="Write Ready for Synchronous Channels Update Interrupt Disable" mask="0x00000001" name="WRDY"/>
|
||
|
|
<bitfield caption="PDC End of TX Buffer Interrupt Disable" mask="0x00000002" name="ENDTX"/>
|
||
|
|
<bitfield caption="PDC TX Buffer Empty Interrupt Disable" mask="0x00000004" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Synchronous Channels Update Underrun Error Interrupt Disable" mask="0x00000008" name="UNRE"/>
|
||
|
|
<bitfield caption="Comparison 0 Match Interrupt Disable" mask="0x00000100" name="CMPM0"/>
|
||
|
|
<bitfield caption="Comparison 1 Match Interrupt Disable" mask="0x00000200" name="CMPM1"/>
|
||
|
|
<bitfield caption="Comparison 2 Match Interrupt Disable" mask="0x00000400" name="CMPM2"/>
|
||
|
|
<bitfield caption="Comparison 3 Match Interrupt Disable" mask="0x00000800" name="CMPM3"/>
|
||
|
|
<bitfield caption="Comparison 4 Match Interrupt Disable" mask="0x00001000" name="CMPM4"/>
|
||
|
|
<bitfield caption="Comparison 5 Match Interrupt Disable" mask="0x00002000" name="CMPM5"/>
|
||
|
|
<bitfield caption="Comparison 6 Match Interrupt Disable" mask="0x00004000" name="CMPM6"/>
|
||
|
|
<bitfield caption="Comparison 7 Match Interrupt Disable" mask="0x00008000" name="CMPM7"/>
|
||
|
|
<bitfield caption="Comparison 0 Update Interrupt Disable" mask="0x00010000" name="CMPU0"/>
|
||
|
|
<bitfield caption="Comparison 1 Update Interrupt Disable" mask="0x00020000" name="CMPU1"/>
|
||
|
|
<bitfield caption="Comparison 2 Update Interrupt Disable" mask="0x00040000" name="CMPU2"/>
|
||
|
|
<bitfield caption="Comparison 3 Update Interrupt Disable" mask="0x00080000" name="CMPU3"/>
|
||
|
|
<bitfield caption="Comparison 4 Update Interrupt Disable" mask="0x00100000" name="CMPU4"/>
|
||
|
|
<bitfield caption="Comparison 5 Update Interrupt Disable" mask="0x00200000" name="CMPU5"/>
|
||
|
|
<bitfield caption="Comparison 6 Update Interrupt Disable" mask="0x00400000" name="CMPU6"/>
|
||
|
|
<bitfield caption="Comparison 7 Update Interrupt Disable" mask="0x00800000" name="CMPU7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Mask Register 2" name="PWM_IMR2" offset="0x3C" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Ready for Synchronous Channels Update Interrupt Mask" mask="0x00000001" name="WRDY"/>
|
||
|
|
<bitfield caption="PDC End of TX Buffer Interrupt Mask" mask="0x00000002" name="ENDTX"/>
|
||
|
|
<bitfield caption="PDC TX Buffer Empty Interrupt Mask" mask="0x00000004" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Synchronous Channels Update Underrun Error Interrupt Mask" mask="0x00000008" name="UNRE"/>
|
||
|
|
<bitfield caption="Comparison 0 Match Interrupt Mask" mask="0x00000100" name="CMPM0"/>
|
||
|
|
<bitfield caption="Comparison 1 Match Interrupt Mask" mask="0x00000200" name="CMPM1"/>
|
||
|
|
<bitfield caption="Comparison 2 Match Interrupt Mask" mask="0x00000400" name="CMPM2"/>
|
||
|
|
<bitfield caption="Comparison 3 Match Interrupt Mask" mask="0x00000800" name="CMPM3"/>
|
||
|
|
<bitfield caption="Comparison 4 Match Interrupt Mask" mask="0x00001000" name="CMPM4"/>
|
||
|
|
<bitfield caption="Comparison 5 Match Interrupt Mask" mask="0x00002000" name="CMPM5"/>
|
||
|
|
<bitfield caption="Comparison 6 Match Interrupt Mask" mask="0x00004000" name="CMPM6"/>
|
||
|
|
<bitfield caption="Comparison 7 Match Interrupt Mask" mask="0x00008000" name="CMPM7"/>
|
||
|
|
<bitfield caption="Comparison 0 Update Interrupt Mask" mask="0x00010000" name="CMPU0"/>
|
||
|
|
<bitfield caption="Comparison 1 Update Interrupt Mask" mask="0x00020000" name="CMPU1"/>
|
||
|
|
<bitfield caption="Comparison 2 Update Interrupt Mask" mask="0x00040000" name="CMPU2"/>
|
||
|
|
<bitfield caption="Comparison 3 Update Interrupt Mask" mask="0x00080000" name="CMPU3"/>
|
||
|
|
<bitfield caption="Comparison 4 Update Interrupt Mask" mask="0x00100000" name="CMPU4"/>
|
||
|
|
<bitfield caption="Comparison 5 Update Interrupt Mask" mask="0x00200000" name="CMPU5"/>
|
||
|
|
<bitfield caption="Comparison 6 Update Interrupt Mask" mask="0x00400000" name="CMPU6"/>
|
||
|
|
<bitfield caption="Comparison 7 Update Interrupt Mask" mask="0x00800000" name="CMPU7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Interrupt Status Register 2" name="PWM_ISR2" offset="0x40" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Ready for Synchronous Channels Update" mask="0x00000001" name="WRDY"/>
|
||
|
|
<bitfield caption="PDC End of TX Buffer" mask="0x00000002" name="ENDTX"/>
|
||
|
|
<bitfield caption="PDC TX Buffer Empty" mask="0x00000004" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Synchronous Channels Update Underrun Error" mask="0x00000008" name="UNRE"/>
|
||
|
|
<bitfield caption="Comparison 0 Match" mask="0x00000100" name="CMPM0"/>
|
||
|
|
<bitfield caption="Comparison 1 Match" mask="0x00000200" name="CMPM1"/>
|
||
|
|
<bitfield caption="Comparison 2 Match" mask="0x00000400" name="CMPM2"/>
|
||
|
|
<bitfield caption="Comparison 3 Match" mask="0x00000800" name="CMPM3"/>
|
||
|
|
<bitfield caption="Comparison 4 Match" mask="0x00001000" name="CMPM4"/>
|
||
|
|
<bitfield caption="Comparison 5 Match" mask="0x00002000" name="CMPM5"/>
|
||
|
|
<bitfield caption="Comparison 6 Match" mask="0x00004000" name="CMPM6"/>
|
||
|
|
<bitfield caption="Comparison 7 Match" mask="0x00008000" name="CMPM7"/>
|
||
|
|
<bitfield caption="Comparison 0 Update" mask="0x00010000" name="CMPU0"/>
|
||
|
|
<bitfield caption="Comparison 1 Update" mask="0x00020000" name="CMPU1"/>
|
||
|
|
<bitfield caption="Comparison 2 Update" mask="0x00040000" name="CMPU2"/>
|
||
|
|
<bitfield caption="Comparison 3 Update" mask="0x00080000" name="CMPU3"/>
|
||
|
|
<bitfield caption="Comparison 4 Update" mask="0x00100000" name="CMPU4"/>
|
||
|
|
<bitfield caption="Comparison 5 Update" mask="0x00200000" name="CMPU5"/>
|
||
|
|
<bitfield caption="Comparison 6 Update" mask="0x00400000" name="CMPU6"/>
|
||
|
|
<bitfield caption="Comparison 7 Update" mask="0x00800000" name="CMPU7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Output Override Value Register" name="PWM_OOV" offset="0x44" rw="RW" size="4">
|
||
|
|
<bitfield caption="Output Override Value for PWMH output of the channel 0" mask="0x00000001" name="OOVH0"/>
|
||
|
|
<bitfield caption="Output Override Value for PWMH output of the channel 1" mask="0x00000002" name="OOVH1"/>
|
||
|
|
<bitfield caption="Output Override Value for PWMH output of the channel 2" mask="0x00000004" name="OOVH2"/>
|
||
|
|
<bitfield caption="Output Override Value for PWMH output of the channel 3" mask="0x00000008" name="OOVH3"/>
|
||
|
|
<bitfield caption="Output Override Value for PWML output of the channel 0" mask="0x00010000" name="OOVL0"/>
|
||
|
|
<bitfield caption="Output Override Value for PWML output of the channel 1" mask="0x00020000" name="OOVL1"/>
|
||
|
|
<bitfield caption="Output Override Value for PWML output of the channel 2" mask="0x00040000" name="OOVL2"/>
|
||
|
|
<bitfield caption="Output Override Value for PWML output of the channel 3" mask="0x00080000" name="OOVL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Output Selection Register" name="PWM_OS" offset="0x48" rw="RW" size="4">
|
||
|
|
<bitfield caption="Output Selection for PWMH output of the channel 0" mask="0x00000001" name="OSH0"/>
|
||
|
|
<bitfield caption="Output Selection for PWMH output of the channel 1" mask="0x00000002" name="OSH1"/>
|
||
|
|
<bitfield caption="Output Selection for PWMH output of the channel 2" mask="0x00000004" name="OSH2"/>
|
||
|
|
<bitfield caption="Output Selection for PWMH output of the channel 3" mask="0x00000008" name="OSH3"/>
|
||
|
|
<bitfield caption="Output Selection for PWML output of the channel 0" mask="0x00010000" name="OSL0"/>
|
||
|
|
<bitfield caption="Output Selection for PWML output of the channel 1" mask="0x00020000" name="OSL1"/>
|
||
|
|
<bitfield caption="Output Selection for PWML output of the channel 2" mask="0x00040000" name="OSL2"/>
|
||
|
|
<bitfield caption="Output Selection for PWML output of the channel 3" mask="0x00080000" name="OSL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Output Selection Set Register" name="PWM_OSS" offset="0x4C" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 0" mask="0x00000001" name="OSSH0"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 1" mask="0x00000002" name="OSSH1"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 2" mask="0x00000004" name="OSSH2"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 3" mask="0x00000008" name="OSSH3"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 0" mask="0x00010000" name="OSSL0"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 1" mask="0x00020000" name="OSSL1"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 2" mask="0x00040000" name="OSSL2"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 3" mask="0x00080000" name="OSSL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Output Selection Clear Register" name="PWM_OSC" offset="0x50" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 0" mask="0x00000001" name="OSCH0"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 1" mask="0x00000002" name="OSCH1"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 2" mask="0x00000004" name="OSCH2"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 3" mask="0x00000008" name="OSCH3"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 0" mask="0x00010000" name="OSCL0"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 1" mask="0x00020000" name="OSCL1"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 2" mask="0x00040000" name="OSCL2"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 3" mask="0x00080000" name="OSCL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Output Selection Set Update Register" name="PWM_OSSUPD" offset="0x54" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 0" mask="0x00000001" name="OSSUPH0"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 1" mask="0x00000002" name="OSSUPH1"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 2" mask="0x00000004" name="OSSUPH2"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWMH output of the channel 3" mask="0x00000008" name="OSSUPH3"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 0" mask="0x00010000" name="OSSUPL0"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 1" mask="0x00020000" name="OSSUPL1"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 2" mask="0x00040000" name="OSSUPL2"/>
|
||
|
|
<bitfield caption="Output Selection Set for PWML output of the channel 3" mask="0x00080000" name="OSSUPL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Output Selection Clear Update Register" name="PWM_OSCUPD" offset="0x58" rw="W" size="4">
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 0" mask="0x00000001" name="OSCUPH0"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 1" mask="0x00000002" name="OSCUPH1"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 2" mask="0x00000004" name="OSCUPH2"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWMH output of the channel 3" mask="0x00000008" name="OSCUPH3"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 0" mask="0x00010000" name="OSCUPL0"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 1" mask="0x00020000" name="OSCUPL1"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 2" mask="0x00040000" name="OSCUPL2"/>
|
||
|
|
<bitfield caption="Output Selection Clear for PWML output of the channel 3" mask="0x00080000" name="OSCUPL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Fault Mode Register" name="PWM_FMR" offset="0x5C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Fault Polarity (fault input bit varies from 0 to 5)" mask="0x000000FF" name="FPOL"/>
|
||
|
|
<bitfield caption="Fault Activation Mode (fault input bit varies from 0 to 5)" mask="0x0000FF00" name="FMOD"/>
|
||
|
|
<bitfield caption="Fault Filtering (fault input bit varies from 0 to 5)" mask="0x00FF0000" name="FFIL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Fault Status Register" name="PWM_FSR" offset="0x60" rw="R" size="4">
|
||
|
|
<bitfield caption="Fault Input Value (fault input bit varies from 0 to 5)" mask="0x000000FF" name="FIV"/>
|
||
|
|
<bitfield caption="Fault Status (fault input bit varies from 0 to 5)" mask="0x0000FF00" name="FS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Fault Clear Register" name="PWM_FCR" offset="0x64" rw="W" size="4">
|
||
|
|
<bitfield caption="Fault Clear (fault input bit varies from 0 to 5)" mask="0x000000FF" name="FCLR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Fault Protection Value Register" name="PWM_FPV" offset="0x68" rw="RW" size="4">
|
||
|
|
<bitfield caption="Fault Protection Value for PWMH output on channel 0" mask="0x00000001" name="FPVH0"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWMH output on channel 1" mask="0x00000002" name="FPVH1"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWMH output on channel 2" mask="0x00000004" name="FPVH2"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWMH output on channel 3" mask="0x00000008" name="FPVH3"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWML output on channel 0" mask="0x00010000" name="FPVL0"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWML output on channel 1" mask="0x00020000" name="FPVL1"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWML output on channel 2" mask="0x00040000" name="FPVL2"/>
|
||
|
|
<bitfield caption="Fault Protection Value for PWML output on channel 3" mask="0x00080000" name="FPVL3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Fault Protection Enable Register" name="PWM_FPE" offset="0x6C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Fault Protection Enable for channel 0 (fault input bit varies from 0 to 5)" mask="0x000000FF" name="FPE0"/>
|
||
|
|
<bitfield caption="Fault Protection Enable for channel 1 (fault input bit varies from 0 to 5)" mask="0x0000FF00" name="FPE1"/>
|
||
|
|
<bitfield caption="Fault Protection Enable for channel 2 (fault input bit varies from 0 to 5)" mask="0x00FF0000" name="FPE2"/>
|
||
|
|
<bitfield caption="Fault Protection Enable for channel 3 (fault input bit varies from 0 to 5)" mask="0xFF000000" name="FPE3"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Event Line 0 Mode Register 0" name="PWM_ELMR0" offset="0x7C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison 0 Selection" mask="0x00000001" name="CSEL0"/>
|
||
|
|
<bitfield caption="Comparison 1 Selection" mask="0x00000002" name="CSEL1"/>
|
||
|
|
<bitfield caption="Comparison 2 Selection" mask="0x00000004" name="CSEL2"/>
|
||
|
|
<bitfield caption="Comparison 3 Selection" mask="0x00000008" name="CSEL3"/>
|
||
|
|
<bitfield caption="Comparison 4 Selection" mask="0x00000010" name="CSEL4"/>
|
||
|
|
<bitfield caption="Comparison 5 Selection" mask="0x00000020" name="CSEL5"/>
|
||
|
|
<bitfield caption="Comparison 6 Selection" mask="0x00000040" name="CSEL6"/>
|
||
|
|
<bitfield caption="Comparison 7 Selection" mask="0x00000080" name="CSEL7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Event Line 0 Mode Register 1" name="PWM_ELMR1" offset="0x80" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison 0 Selection" mask="0x00000001" name="CSEL0"/>
|
||
|
|
<bitfield caption="Comparison 1 Selection" mask="0x00000002" name="CSEL1"/>
|
||
|
|
<bitfield caption="Comparison 2 Selection" mask="0x00000004" name="CSEL2"/>
|
||
|
|
<bitfield caption="Comparison 3 Selection" mask="0x00000008" name="CSEL3"/>
|
||
|
|
<bitfield caption="Comparison 4 Selection" mask="0x00000010" name="CSEL4"/>
|
||
|
|
<bitfield caption="Comparison 5 Selection" mask="0x00000020" name="CSEL5"/>
|
||
|
|
<bitfield caption="Comparison 6 Selection" mask="0x00000040" name="CSEL6"/>
|
||
|
|
<bitfield caption="Comparison 7 Selection" mask="0x00000080" name="CSEL7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Write Protect Control Register" name="PWM_WPCR" offset="0xE4" rw="W" size="4">
|
||
|
|
<bitfield caption="Write Protect Command" mask="0x00000003" name="WPCMD"/>
|
||
|
|
<bitfield caption="Write Protect Register Group 0" mask="0x00000004" name="WPRG0"/>
|
||
|
|
<bitfield caption="Write Protect Register Group 1" mask="0x00000008" name="WPRG1"/>
|
||
|
|
<bitfield caption="Write Protect Register Group 2" mask="0x00000010" name="WPRG2"/>
|
||
|
|
<bitfield caption="Write Protect Register Group 3" mask="0x00000020" name="WPRG3"/>
|
||
|
|
<bitfield caption="Write Protect Register Group 4" mask="0x00000040" name="WPRG4"/>
|
||
|
|
<bitfield caption="Write Protect Register Group 5" mask="0x00000080" name="WPRG5"/>
|
||
|
|
<bitfield caption="Write Protect Key" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Write Protect Status Register" name="PWM_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect SW Status" mask="0x00000001" name="WPSWS0"/>
|
||
|
|
<bitfield caption="Write Protect SW Status" mask="0x00000002" name="WPSWS1"/>
|
||
|
|
<bitfield caption="Write Protect SW Status" mask="0x00000004" name="WPSWS2"/>
|
||
|
|
<bitfield caption="Write Protect SW Status" mask="0x00000008" name="WPSWS3"/>
|
||
|
|
<bitfield caption="Write Protect SW Status" mask="0x00000010" name="WPSWS4"/>
|
||
|
|
<bitfield caption="Write Protect SW Status" mask="0x00000020" name="WPSWS5"/>
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000080" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect HW Status" mask="0x00000100" name="WPHWS0"/>
|
||
|
|
<bitfield caption="Write Protect HW Status" mask="0x00000200" name="WPHWS1"/>
|
||
|
|
<bitfield caption="Write Protect HW Status" mask="0x00000400" name="WPHWS2"/>
|
||
|
|
<bitfield caption="Write Protect HW Status" mask="0x00000800" name="WPHWS3"/>
|
||
|
|
<bitfield caption="Write Protect HW Status" mask="0x00001000" name="WPHWS4"/>
|
||
|
|
<bitfield caption="Write Protect HW Status" mask="0x00002000" name="WPHWS5"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0xFFFF0000" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 0 Value Register" name="PWM_CMPV0" offset="0x130" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 0 Value Update Register" name="PWM_CMPVUPD0" offset="0x134" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 0 Mode Register" name="PWM_CMPM0" offset="0x138" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 0 Mode Update Register" name="PWM_CMPMUPD0" offset="0x13C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 1 Value Register" name="PWM_CMPV1" offset="0x140" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 1 Value Update Register" name="PWM_CMPVUPD1" offset="0x144" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 1 Mode Register" name="PWM_CMPM1" offset="0x148" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 1 Mode Update Register" name="PWM_CMPMUPD1" offset="0x14C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 2 Value Register" name="PWM_CMPV2" offset="0x150" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 2 Value Update Register" name="PWM_CMPVUPD2" offset="0x154" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 2 Mode Register" name="PWM_CMPM2" offset="0x158" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 2 Mode Update Register" name="PWM_CMPMUPD2" offset="0x15C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 3 Value Register" name="PWM_CMPV3" offset="0x160" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 3 Value Update Register" name="PWM_CMPVUPD3" offset="0x164" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 3 Mode Register" name="PWM_CMPM3" offset="0x168" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 3 Mode Update Register" name="PWM_CMPMUPD3" offset="0x16C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 4 Value Register" name="PWM_CMPV4" offset="0x170" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 4 Value Update Register" name="PWM_CMPVUPD4" offset="0x174" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 4 Mode Register" name="PWM_CMPM4" offset="0x178" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 4 Mode Update Register" name="PWM_CMPMUPD4" offset="0x17C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 5 Value Register" name="PWM_CMPV5" offset="0x180" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 5 Value Update Register" name="PWM_CMPVUPD5" offset="0x184" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 5 Mode Register" name="PWM_CMPM5" offset="0x188" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 5 Mode Update Register" name="PWM_CMPMUPD5" offset="0x18C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 6 Value Register" name="PWM_CMPV6" offset="0x190" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 6 Value Update Register" name="PWM_CMPVUPD6" offset="0x194" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 6 Mode Register" name="PWM_CMPM6" offset="0x198" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 6 Mode Update Register" name="PWM_CMPMUPD6" offset="0x19C" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 7 Value Register" name="PWM_CMPV7" offset="0x1A0" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Value" mask="0x00FFFFFF" name="CV"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode" mask="0x01000000" name="CVM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 7 Value Update Register" name="PWM_CMPVUPD7" offset="0x1A4" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Value Update" mask="0x00FFFFFF" name="CVUPD"/>
|
||
|
|
<bitfield caption="Comparison x Value Mode Update" mask="0x01000000" name="CVMUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 7 Mode Register" name="PWM_CMPM7" offset="0x1A8" rw="RW" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable" mask="0x00000001" name="CEN"/>
|
||
|
|
<bitfield caption="Comparison x Trigger" mask="0x000000F0" name="CTR"/>
|
||
|
|
<bitfield caption="Comparison x Period" mask="0x00000F00" name="CPR"/>
|
||
|
|
<bitfield caption="Comparison x Period Counter" mask="0x0000F000" name="CPRCNT"/>
|
||
|
|
<bitfield caption="Comparison x Update Period" mask="0x000F0000" name="CUPR"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Counter" mask="0x00F00000" name="CUPRCNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Comparison 7 Mode Update Register" name="PWM_CMPMUPD7" offset="0x1AC" rw="W" size="4">
|
||
|
|
<bitfield caption="Comparison x Enable Update" mask="0x00000001" name="CENUPD"/>
|
||
|
|
<bitfield caption="Comparison x Trigger Update" mask="0x000000F0" name="CTRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Period Update" mask="0x00000F00" name="CPRUPD"/>
|
||
|
|
<bitfield caption="Comparison x Update Period Update" mask="0x000F0000" name="CUPRUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Mode Register (ch_num = 0)" name="PWM_CMR0" offset="0x200" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Pre-scaler" mask="0x0000000F" name="CPRE" values="PWM_CMR0__CPRE"/>
|
||
|
|
<bitfield caption="Channel Alignment" mask="0x00000100" name="CALG"/>
|
||
|
|
<bitfield caption="Channel Polarity" mask="0x00000200" name="CPOL"/>
|
||
|
|
<bitfield caption="Counter Event Selection" mask="0x00000400" name="CES"/>
|
||
|
|
<bitfield caption="Dead-Time Generator Enable" mask="0x00010000" name="DTE"/>
|
||
|
|
<bitfield caption="Dead-Time PWMHx Output Inverted" mask="0x00020000" name="DTHI"/>
|
||
|
|
<bitfield caption="Dead-Time PWMLx Output Inverted" mask="0x00040000" name="DTLI"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Register (ch_num = 0)" name="PWM_CDTY0" offset="0x204" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle" mask="0x00FFFFFF" name="CDTY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Update Register (ch_num = 0)" name="PWM_CDTYUPD0" offset="0x208" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle Update" mask="0x00FFFFFF" name="CDTYUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Register (ch_num = 0)" name="PWM_CPRD0" offset="0x20C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Period" mask="0x00FFFFFF" name="CPRD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Update Register (ch_num = 0)" name="PWM_CPRDUPD0" offset="0x210" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Period Update" mask="0x00FFFFFF" name="CPRDUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Counter Register (ch_num = 0)" name="PWM_CCNT0" offset="0x214" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel Counter Register" mask="0x00FFFFFF" name="CNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Register (ch_num = 0)" name="PWM_DT0" offset="0x218" rw="RW" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value for PWMHx Output" mask="0x0000FFFF" name="DTH"/>
|
||
|
|
<bitfield caption="Dead-Time Value for PWMLx Output" mask="0xFFFF0000" name="DTL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Update Register (ch_num = 0)" name="PWM_DTUPD0" offset="0x21C" rw="W" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMHx Output" mask="0x0000FFFF" name="DTHUPD"/>
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMLx Output" mask="0xFFFF0000" name="DTLUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Mode Register (ch_num = 1)" name="PWM_CMR1" offset="0x220" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Pre-scaler" mask="0x0000000F" name="CPRE" values="PWM_CMR1__CPRE"/>
|
||
|
|
<bitfield caption="Channel Alignment" mask="0x00000100" name="CALG"/>
|
||
|
|
<bitfield caption="Channel Polarity" mask="0x00000200" name="CPOL"/>
|
||
|
|
<bitfield caption="Counter Event Selection" mask="0x00000400" name="CES"/>
|
||
|
|
<bitfield caption="Dead-Time Generator Enable" mask="0x00010000" name="DTE"/>
|
||
|
|
<bitfield caption="Dead-Time PWMHx Output Inverted" mask="0x00020000" name="DTHI"/>
|
||
|
|
<bitfield caption="Dead-Time PWMLx Output Inverted" mask="0x00040000" name="DTLI"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Register (ch_num = 1)" name="PWM_CDTY1" offset="0x224" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle" mask="0x00FFFFFF" name="CDTY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Update Register (ch_num = 1)" name="PWM_CDTYUPD1" offset="0x228" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle Update" mask="0x00FFFFFF" name="CDTYUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Register (ch_num = 1)" name="PWM_CPRD1" offset="0x22C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Period" mask="0x00FFFFFF" name="CPRD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Update Register (ch_num = 1)" name="PWM_CPRDUPD1" offset="0x230" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Period Update" mask="0x00FFFFFF" name="CPRDUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Counter Register (ch_num = 1)" name="PWM_CCNT1" offset="0x234" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel Counter Register" mask="0x00FFFFFF" name="CNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Register (ch_num = 1)" name="PWM_DT1" offset="0x238" rw="RW" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value for PWMHx Output" mask="0x0000FFFF" name="DTH"/>
|
||
|
|
<bitfield caption="Dead-Time Value for PWMLx Output" mask="0xFFFF0000" name="DTL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Update Register (ch_num = 1)" name="PWM_DTUPD1" offset="0x23C" rw="W" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMHx Output" mask="0x0000FFFF" name="DTHUPD"/>
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMLx Output" mask="0xFFFF0000" name="DTLUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Mode Register (ch_num = 2)" name="PWM_CMR2" offset="0x240" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Pre-scaler" mask="0x0000000F" name="CPRE" values="PWM_CMR2__CPRE"/>
|
||
|
|
<bitfield caption="Channel Alignment" mask="0x00000100" name="CALG"/>
|
||
|
|
<bitfield caption="Channel Polarity" mask="0x00000200" name="CPOL"/>
|
||
|
|
<bitfield caption="Counter Event Selection" mask="0x00000400" name="CES"/>
|
||
|
|
<bitfield caption="Dead-Time Generator Enable" mask="0x00010000" name="DTE"/>
|
||
|
|
<bitfield caption="Dead-Time PWMHx Output Inverted" mask="0x00020000" name="DTHI"/>
|
||
|
|
<bitfield caption="Dead-Time PWMLx Output Inverted" mask="0x00040000" name="DTLI"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Register (ch_num = 2)" name="PWM_CDTY2" offset="0x244" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle" mask="0x00FFFFFF" name="CDTY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Update Register (ch_num = 2)" name="PWM_CDTYUPD2" offset="0x248" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle Update" mask="0x00FFFFFF" name="CDTYUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Register (ch_num = 2)" name="PWM_CPRD2" offset="0x24C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Period" mask="0x00FFFFFF" name="CPRD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Update Register (ch_num = 2)" name="PWM_CPRDUPD2" offset="0x250" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Period Update" mask="0x00FFFFFF" name="CPRDUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Counter Register (ch_num = 2)" name="PWM_CCNT2" offset="0x254" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel Counter Register" mask="0x00FFFFFF" name="CNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Register (ch_num = 2)" name="PWM_DT2" offset="0x258" rw="RW" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value for PWMHx Output" mask="0x0000FFFF" name="DTH"/>
|
||
|
|
<bitfield caption="Dead-Time Value for PWMLx Output" mask="0xFFFF0000" name="DTL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Update Register (ch_num = 2)" name="PWM_DTUPD2" offset="0x25C" rw="W" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMHx Output" mask="0x0000FFFF" name="DTHUPD"/>
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMLx Output" mask="0xFFFF0000" name="DTLUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Mode Register (ch_num = 3)" name="PWM_CMR3" offset="0x260" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Pre-scaler" mask="0x0000000F" name="CPRE" values="PWM_CMR3__CPRE"/>
|
||
|
|
<bitfield caption="Channel Alignment" mask="0x00000100" name="CALG"/>
|
||
|
|
<bitfield caption="Channel Polarity" mask="0x00000200" name="CPOL"/>
|
||
|
|
<bitfield caption="Counter Event Selection" mask="0x00000400" name="CES"/>
|
||
|
|
<bitfield caption="Dead-Time Generator Enable" mask="0x00010000" name="DTE"/>
|
||
|
|
<bitfield caption="Dead-Time PWMHx Output Inverted" mask="0x00020000" name="DTHI"/>
|
||
|
|
<bitfield caption="Dead-Time PWMLx Output Inverted" mask="0x00040000" name="DTLI"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Register (ch_num = 3)" name="PWM_CDTY3" offset="0x264" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle" mask="0x00FFFFFF" name="CDTY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Duty Cycle Update Register (ch_num = 3)" name="PWM_CDTYUPD3" offset="0x268" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Duty-Cycle Update" mask="0x00FFFFFF" name="CDTYUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Register (ch_num = 3)" name="PWM_CPRD3" offset="0x26C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Channel Period" mask="0x00FFFFFF" name="CPRD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Period Update Register (ch_num = 3)" name="PWM_CPRDUPD3" offset="0x270" rw="W" size="4">
|
||
|
|
<bitfield caption="Channel Period Update" mask="0x00FFFFFF" name="CPRDUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Counter Register (ch_num = 3)" name="PWM_CCNT3" offset="0x274" rw="R" size="4">
|
||
|
|
<bitfield caption="Channel Counter Register" mask="0x00FFFFFF" name="CNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Register (ch_num = 3)" name="PWM_DT3" offset="0x278" rw="RW" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value for PWMHx Output" mask="0x0000FFFF" name="DTH"/>
|
||
|
|
<bitfield caption="Dead-Time Value for PWMLx Output" mask="0xFFFF0000" name="DTL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="PWM Channel Dead Time Update Register (ch_num = 3)" name="PWM_DTUPD3" offset="0x27C" rw="W" size="4">
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMHx Output" mask="0x0000FFFF" name="DTHUPD"/>
|
||
|
|
<bitfield caption="Dead-Time Value Update for PWMLx Output" mask="0xFFFF0000" name="DTLUPD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="PWM_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="PWM_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="PWM_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="PWM_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="PWM_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="PWM_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="PWM_SCM__UPDM">
|
||
|
|
<value caption="Manual write of double buffer registers and manual update of synchronous channels" name="MODE0" value="0x0"/>
|
||
|
|
<value caption="Manual write of double buffer registers and automatic update of synchronous channels" name="MODE1" value="0x1"/>
|
||
|
|
<value caption="Automatic write of duty-cycle update registers by the PDC and automatic update of synchronous channels" name="MODE2" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PWM_CMR0__CPRE">
|
||
|
|
<value caption="Master clock" name="MCK" value="0x0"/>
|
||
|
|
<value caption="Master clock/2" name="MCK_DIV_2" value="0x1"/>
|
||
|
|
<value caption="Master clock/4" name="MCK_DIV_4" value="0x2"/>
|
||
|
|
<value caption="Master clock/8" name="MCK_DIV_8" value="0x3"/>
|
||
|
|
<value caption="Master clock/16" name="MCK_DIV_16" value="0x4"/>
|
||
|
|
<value caption="Master clock/32" name="MCK_DIV_32" value="0x5"/>
|
||
|
|
<value caption="Master clock/64" name="MCK_DIV_64" value="0x6"/>
|
||
|
|
<value caption="Master clock/128" name="MCK_DIV_128" value="0x7"/>
|
||
|
|
<value caption="Master clock/256" name="MCK_DIV_256" value="0x8"/>
|
||
|
|
<value caption="Master clock/512" name="MCK_DIV_512" value="0x9"/>
|
||
|
|
<value caption="Master clock/1024" name="MCK_DIV_1024" value="0xA"/>
|
||
|
|
<value caption="Clock A" name="CLKA" value="0xB"/>
|
||
|
|
<value caption="Clock B" name="CLKB" value="0xC"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PWM_CMR1__CPRE">
|
||
|
|
<value caption="Master clock" name="MCK" value="0x0"/>
|
||
|
|
<value caption="Master clock/2" name="MCK_DIV_2" value="0x1"/>
|
||
|
|
<value caption="Master clock/4" name="MCK_DIV_4" value="0x2"/>
|
||
|
|
<value caption="Master clock/8" name="MCK_DIV_8" value="0x3"/>
|
||
|
|
<value caption="Master clock/16" name="MCK_DIV_16" value="0x4"/>
|
||
|
|
<value caption="Master clock/32" name="MCK_DIV_32" value="0x5"/>
|
||
|
|
<value caption="Master clock/64" name="MCK_DIV_64" value="0x6"/>
|
||
|
|
<value caption="Master clock/128" name="MCK_DIV_128" value="0x7"/>
|
||
|
|
<value caption="Master clock/256" name="MCK_DIV_256" value="0x8"/>
|
||
|
|
<value caption="Master clock/512" name="MCK_DIV_512" value="0x9"/>
|
||
|
|
<value caption="Master clock/1024" name="MCK_DIV_1024" value="0xA"/>
|
||
|
|
<value caption="Clock A" name="CLKA" value="0xB"/>
|
||
|
|
<value caption="Clock B" name="CLKB" value="0xC"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PWM_CMR2__CPRE">
|
||
|
|
<value caption="Master clock" name="MCK" value="0x0"/>
|
||
|
|
<value caption="Master clock/2" name="MCK_DIV_2" value="0x1"/>
|
||
|
|
<value caption="Master clock/4" name="MCK_DIV_4" value="0x2"/>
|
||
|
|
<value caption="Master clock/8" name="MCK_DIV_8" value="0x3"/>
|
||
|
|
<value caption="Master clock/16" name="MCK_DIV_16" value="0x4"/>
|
||
|
|
<value caption="Master clock/32" name="MCK_DIV_32" value="0x5"/>
|
||
|
|
<value caption="Master clock/64" name="MCK_DIV_64" value="0x6"/>
|
||
|
|
<value caption="Master clock/128" name="MCK_DIV_128" value="0x7"/>
|
||
|
|
<value caption="Master clock/256" name="MCK_DIV_256" value="0x8"/>
|
||
|
|
<value caption="Master clock/512" name="MCK_DIV_512" value="0x9"/>
|
||
|
|
<value caption="Master clock/1024" name="MCK_DIV_1024" value="0xA"/>
|
||
|
|
<value caption="Clock A" name="CLKA" value="0xB"/>
|
||
|
|
<value caption="Clock B" name="CLKB" value="0xC"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="PWM_CMR3__CPRE">
|
||
|
|
<value caption="Master clock" name="MCK" value="0x0"/>
|
||
|
|
<value caption="Master clock/2" name="MCK_DIV_2" value="0x1"/>
|
||
|
|
<value caption="Master clock/4" name="MCK_DIV_4" value="0x2"/>
|
||
|
|
<value caption="Master clock/8" name="MCK_DIV_8" value="0x3"/>
|
||
|
|
<value caption="Master clock/16" name="MCK_DIV_16" value="0x4"/>
|
||
|
|
<value caption="Master clock/32" name="MCK_DIV_32" value="0x5"/>
|
||
|
|
<value caption="Master clock/64" name="MCK_DIV_64" value="0x6"/>
|
||
|
|
<value caption="Master clock/128" name="MCK_DIV_128" value="0x7"/>
|
||
|
|
<value caption="Master clock/256" name="MCK_DIV_256" value="0x8"/>
|
||
|
|
<value caption="Master clock/512" name="MCK_DIV_512" value="0x9"/>
|
||
|
|
<value caption="Master clock/1024" name="MCK_DIV_1024" value="0xA"/>
|
||
|
|
<value caption="Clock A" name="CLKA" value="0xB"/>
|
||
|
|
<value caption="Clock B" name="CLKB" value="0xC"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Reset Controller" name="RSTC" version="11009C">
|
||
|
|
<register-group name="RSTC">
|
||
|
|
<register caption="Control Register" name="RSTC_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Processor Reset" mask="0x00000001" name="PROCRST"/>
|
||
|
|
<bitfield caption="Peripheral Reset" mask="0x00000004" name="PERRST"/>
|
||
|
|
<bitfield caption="External Reset" mask="0x00000008" name="EXTRST"/>
|
||
|
|
<bitfield caption="System Reset Key" mask="0xFF000000" name="KEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="RSTC_SR" offset="0x04" rw="R" size="4">
|
||
|
|
<bitfield caption="User Reset Status" mask="0x00000001" name="URSTS"/>
|
||
|
|
<bitfield caption="Reset Type" mask="0x00000700" name="RSTTYP"/>
|
||
|
|
<bitfield caption="NRST Pin Level" mask="0x00010000" name="NRSTL"/>
|
||
|
|
<bitfield caption="Software Reset Command in Progress" mask="0x00020000" name="SRCMP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="RSTC_MR" offset="0x08" rw="RW" size="4">
|
||
|
|
<bitfield caption="User Reset Enable" mask="0x00000001" name="URSTEN"/>
|
||
|
|
<bitfield caption="User Reset Interrupt Enable" mask="0x00000010" name="URSTIEN"/>
|
||
|
|
<bitfield caption="External Reset Length" mask="0x00000F00" name="ERSTL"/>
|
||
|
|
<bitfield caption="Password" mask="0xFF000000" name="KEY"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Real-time Clock" name="RTC" version="6056K">
|
||
|
|
<register-group name="RTC">
|
||
|
|
<register caption="Control Register" name="RTC_CR" offset="0x00" rw="RW" size="4">
|
||
|
|
<bitfield caption="Update Request Time Register" mask="0x00000001" name="UPDTIM"/>
|
||
|
|
<bitfield caption="Update Request Calendar Register" mask="0x00000002" name="UPDCAL"/>
|
||
|
|
<bitfield caption="Time Event Selection" mask="0x00000300" name="TIMEVSEL" values="RTC_CR__TIMEVSEL"/>
|
||
|
|
<bitfield caption="Calendar Event Selection" mask="0x00030000" name="CALEVSEL" values="RTC_CR__CALEVSEL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="RTC_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="12-/24-hour Mode" mask="0x00000001" name="HRMOD"/>
|
||
|
|
<bitfield caption="PERSIAN Calendar" mask="0x00000002" name="PERSIAN"/>
|
||
|
|
<bitfield caption="NEGative PPM Correction" mask="0x00000010" name="NEGPPM"/>
|
||
|
|
<bitfield caption="Slow Clock Correction" mask="0x00007F00" name="CORRECTION"/>
|
||
|
|
<bitfield caption="HIGH PPM Correction" mask="0x00008000" name="HIGHPPM"/>
|
||
|
|
<bitfield caption="RTCOUT0 Output Source Selection" mask="0x00070000" name="OUT0" values="RTC_MR__OUT0"/>
|
||
|
|
<bitfield caption="RTCOUT1 Output Source Selection" mask="0x00700000" name="OUT1" values="RTC_MR__OUT1"/>
|
||
|
|
<bitfield caption="High Duration of the Output Pulse" mask="0x07000000" name="THIGH" values="RTC_MR__THIGH"/>
|
||
|
|
<bitfield caption="Period of the Output Pulse" mask="0x30000000" name="TPERIOD" values="RTC_MR__TPERIOD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Time Register" name="RTC_TIMR" offset="0x08" rw="RW" size="4">
|
||
|
|
<bitfield caption="Current Second" mask="0x0000007F" name="SEC"/>
|
||
|
|
<bitfield caption="Current Minute" mask="0x00007F00" name="MIN"/>
|
||
|
|
<bitfield caption="Current Hour" mask="0x003F0000" name="HOUR"/>
|
||
|
|
<bitfield caption="Ante Meridiem Post Meridiem Indicator" mask="0x00400000" name="AMPM"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Calendar Register" name="RTC_CALR" offset="0x0C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Current Century" mask="0x0000007F" name="CENT"/>
|
||
|
|
<bitfield caption="Current Year" mask="0x0000FF00" name="YEAR"/>
|
||
|
|
<bitfield caption="Current Month" mask="0x001F0000" name="MONTH"/>
|
||
|
|
<bitfield caption="Current Day in Current Week" mask="0x00E00000" name="DAY"/>
|
||
|
|
<bitfield caption="Current Day in Current Month" mask="0x3F000000" name="DATE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Time Alarm Register" name="RTC_TIMALR" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Second Alarm" mask="0x0000007F" name="SEC"/>
|
||
|
|
<bitfield caption="Second Alarm Enable" mask="0x00000080" name="SECEN"/>
|
||
|
|
<bitfield caption="Minute Alarm" mask="0x00007F00" name="MIN"/>
|
||
|
|
<bitfield caption="Minute Alarm Enable" mask="0x00008000" name="MINEN"/>
|
||
|
|
<bitfield caption="Hour Alarm" mask="0x003F0000" name="HOUR"/>
|
||
|
|
<bitfield caption="AM/PM Indicator" mask="0x00400000" name="AMPM"/>
|
||
|
|
<bitfield caption="Hour Alarm Enable" mask="0x00800000" name="HOUREN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Calendar Alarm Register" name="RTC_CALALR" offset="0x14" rw="RW" size="4">
|
||
|
|
<bitfield caption="Month Alarm" mask="0x001F0000" name="MONTH"/>
|
||
|
|
<bitfield caption="Month Alarm Enable" mask="0x00800000" name="MTHEN"/>
|
||
|
|
<bitfield caption="Date Alarm" mask="0x3F000000" name="DATE"/>
|
||
|
|
<bitfield caption="Date Alarm Enable" mask="0x80000000" name="DATEEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="RTC_SR" offset="0x18" rw="R" size="4">
|
||
|
|
<bitfield caption="Acknowledge for Update" mask="0x00000001" name="ACKUPD" values="RTC_SR__ACKUPD"/>
|
||
|
|
<bitfield caption="Alarm Flag" mask="0x00000002" name="ALARM" values="RTC_SR__ALARM"/>
|
||
|
|
<bitfield caption="Second Event" mask="0x00000004" name="SEC" values="RTC_SR__SEC"/>
|
||
|
|
<bitfield caption="Time Event" mask="0x00000008" name="TIMEV" values="RTC_SR__TIMEV"/>
|
||
|
|
<bitfield caption="Calendar Event" mask="0x00000010" name="CALEV" values="RTC_SR__CALEV"/>
|
||
|
|
<bitfield caption="Time and/or Date Free Running Error" mask="0x00000020" name="TDERR" values="RTC_SR__TDERR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Clear Command Register" name="RTC_SCCR" offset="0x1C" rw="W" size="4">
|
||
|
|
<bitfield caption="Acknowledge Clear" mask="0x00000001" name="ACKCLR"/>
|
||
|
|
<bitfield caption="Alarm Clear" mask="0x00000002" name="ALRCLR"/>
|
||
|
|
<bitfield caption="Second Clear" mask="0x00000004" name="SECCLR"/>
|
||
|
|
<bitfield caption="Time Clear" mask="0x00000008" name="TIMCLR"/>
|
||
|
|
<bitfield caption="Calendar Clear" mask="0x00000010" name="CALCLR"/>
|
||
|
|
<bitfield caption="Time and/or Date Free Running Error Clear" mask="0x00000020" name="TDERRCLR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="RTC_IER" offset="0x20" rw="W" size="4">
|
||
|
|
<bitfield caption="Acknowledge Update Interrupt Enable" mask="0x00000001" name="ACKEN"/>
|
||
|
|
<bitfield caption="Alarm Interrupt Enable" mask="0x00000002" name="ALREN"/>
|
||
|
|
<bitfield caption="Second Event Interrupt Enable" mask="0x00000004" name="SECEN"/>
|
||
|
|
<bitfield caption="Time Event Interrupt Enable" mask="0x00000008" name="TIMEN"/>
|
||
|
|
<bitfield caption="Calendar Event Interrupt Enable" mask="0x00000010" name="CALEN"/>
|
||
|
|
<bitfield caption="Time and/or Date Error Interrupt Enable" mask="0x00000020" name="TDERREN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="RTC_IDR" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="Acknowledge Update Interrupt Disable" mask="0x00000001" name="ACKDIS"/>
|
||
|
|
<bitfield caption="Alarm Interrupt Disable" mask="0x00000002" name="ALRDIS"/>
|
||
|
|
<bitfield caption="Second Event Interrupt Disable" mask="0x00000004" name="SECDIS"/>
|
||
|
|
<bitfield caption="Time Event Interrupt Disable" mask="0x00000008" name="TIMDIS"/>
|
||
|
|
<bitfield caption="Calendar Event Interrupt Disable" mask="0x00000010" name="CALDIS"/>
|
||
|
|
<bitfield caption="Time and/or Date Error Interrupt Disable" mask="0x00000020" name="TDERRDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="RTC_IMR" offset="0x28" rw="R" size="4">
|
||
|
|
<bitfield caption="Acknowledge Update Interrupt Mask" mask="0x00000001" name="ACK"/>
|
||
|
|
<bitfield caption="Alarm Interrupt Mask" mask="0x00000002" name="ALR"/>
|
||
|
|
<bitfield caption="Second Event Interrupt Mask" mask="0x00000004" name="SEC"/>
|
||
|
|
<bitfield caption="Time Event Interrupt Mask" mask="0x00000008" name="TIM"/>
|
||
|
|
<bitfield caption="Calendar Event Interrupt Mask" mask="0x00000010" name="CAL"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Valid Entry Register" name="RTC_VER" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="Non-valid Time" mask="0x00000001" name="NVTIM"/>
|
||
|
|
<bitfield caption="Non-valid Calendar" mask="0x00000002" name="NVCAL"/>
|
||
|
|
<bitfield caption="Non-valid Time Alarm" mask="0x00000004" name="NVTIMALR"/>
|
||
|
|
<bitfield caption="Non-valid Calendar Alarm" mask="0x00000008" name="NVCALALR"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="RTC_CR__TIMEVSEL">
|
||
|
|
<value caption="Minute change" name="MINUTE" value="0x0"/>
|
||
|
|
<value caption="Hour change" name="HOUR" value="0x1"/>
|
||
|
|
<value caption="Every day at midnight" name="MIDNIGHT" value="0x2"/>
|
||
|
|
<value caption="Every day at noon" name="NOON" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_CR__CALEVSEL">
|
||
|
|
<value caption="Week change (every Monday at time 00:00:00)" name="WEEK" value="0x0"/>
|
||
|
|
<value caption="Month change (every 01 of each month at time 00:00:00)" name="MONTH" value="0x1"/>
|
||
|
|
<value caption="Year change (every January 1 at time 00:00:00)" name="YEAR" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_MR__OUT0">
|
||
|
|
<value caption="no waveform, stuck at '0'" name="NO_WAVE" value="0x0"/>
|
||
|
|
<value caption="1 Hz square wave" name="FREQ1HZ" value="0x1"/>
|
||
|
|
<value caption="32 Hz square wave" name="FREQ32HZ" value="0x2"/>
|
||
|
|
<value caption="64 Hz square wave" name="FREQ64HZ" value="0x3"/>
|
||
|
|
<value caption="512 Hz square wave" name="FREQ512HZ" value="0x4"/>
|
||
|
|
<value caption="output toggles when alarm flag rises" name="ALARM_TOGGLE" value="0x5"/>
|
||
|
|
<value caption="output is a copy of the alarm flag" name="ALARM_FLAG" value="0x6"/>
|
||
|
|
<value caption="duty cycle programmable pulse" name="PROG_PULSE" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_MR__OUT1">
|
||
|
|
<value caption="no waveform, stuck at '0'" name="NO_WAVE" value="0x0"/>
|
||
|
|
<value caption="1 Hz square wave" name="FREQ1HZ" value="0x1"/>
|
||
|
|
<value caption="32 Hz square wave" name="FREQ32HZ" value="0x2"/>
|
||
|
|
<value caption="64 Hz square wave" name="FREQ64HZ" value="0x3"/>
|
||
|
|
<value caption="512 Hz square wave" name="FREQ512HZ" value="0x4"/>
|
||
|
|
<value caption="output toggles when alarm flag rises" name="ALARM_TOGGLE" value="0x5"/>
|
||
|
|
<value caption="output is a copy of the alarm flag" name="ALARM_FLAG" value="0x6"/>
|
||
|
|
<value caption="duty cycle programmable pulse" name="PROG_PULSE" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_MR__THIGH">
|
||
|
|
<value caption="31.2 ms" name="H_31MS" value="0x0"/>
|
||
|
|
<value caption="15.6 ms" name="H_16MS" value="0x1"/>
|
||
|
|
<value caption="3.91 ms" name="H_4MS" value="0x2"/>
|
||
|
|
<value caption="976 us" name="H_976US" value="0x3"/>
|
||
|
|
<value caption="488 us" name="H_488US" value="0x4"/>
|
||
|
|
<value caption="122 us" name="H_122US" value="0x5"/>
|
||
|
|
<value caption="30.5 us" name="H_30US" value="0x6"/>
|
||
|
|
<value caption="15.2 us" name="H_15US" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_MR__TPERIOD">
|
||
|
|
<value caption="1 second" name="P_1S" value="0x0"/>
|
||
|
|
<value caption="500 ms" name="P_500MS" value="0x1"/>
|
||
|
|
<value caption="250 ms" name="P_250MS" value="0x2"/>
|
||
|
|
<value caption="125 ms" name="P_125MS" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_SR__ACKUPD">
|
||
|
|
<value caption="Time and calendar registers cannot be updated." name="FREERUN" value="0"/>
|
||
|
|
<value caption="Time and calendar registers can be updated." name="UPDATE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_SR__ALARM">
|
||
|
|
<value caption="No alarm matching condition occurred." name="NO_ALARMEVENT" value="0"/>
|
||
|
|
<value caption="An alarm matching condition has occurred." name="ALARMEVENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_SR__SEC">
|
||
|
|
<value caption="No second event has occurred since the last clear." name="NO_SECEVENT" value="0"/>
|
||
|
|
<value caption="At least one second event has occurred since the last clear." name="SECEVENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_SR__TIMEV">
|
||
|
|
<value caption="No time event has occurred since the last clear." name="NO_TIMEVENT" value="0"/>
|
||
|
|
<value caption="At least one time event has occurred since the last clear." name="TIMEVENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_SR__CALEV">
|
||
|
|
<value caption="No calendar event has occurred since the last clear." name="NO_CALEVENT" value="0"/>
|
||
|
|
<value caption="At least one calendar event has occurred since the last clear." name="CALEVENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="RTC_SR__TDERR">
|
||
|
|
<value caption="The internal free running counters are carrying valid values since the last read of RTC_SR." name="CORRECT" value="0"/>
|
||
|
|
<value caption="The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid." name="ERR_TIMEDATE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Real-time Timer" name="RTT" version="6081F">
|
||
|
|
<register-group name="RTT">
|
||
|
|
<register caption="Mode Register" name="RTT_MR" offset="0x00" rw="RW" size="4">
|
||
|
|
<bitfield caption="Real-time Timer Prescaler Value" mask="0x0000FFFF" name="RTPRES"/>
|
||
|
|
<bitfield caption="Alarm Interrupt Enable" mask="0x00010000" name="ALMIEN"/>
|
||
|
|
<bitfield caption="Real-time Timer Increment Interrupt Enable" mask="0x00020000" name="RTTINCIEN"/>
|
||
|
|
<bitfield caption="Real-time Timer Restart" mask="0x00040000" name="RTTRST"/>
|
||
|
|
<bitfield caption="Real-time Timer Disable" mask="0x00100000" name="RTTDIS"/>
|
||
|
|
<bitfield caption="Real-Time Clock 1Hz Clock Selection" mask="0x01000000" name="RTC1HZ"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Alarm Register" name="RTT_AR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Alarm Value" mask="0xFFFFFFFF" name="ALMV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Value Register" name="RTT_VR" offset="0x08" rw="R" size="4">
|
||
|
|
<bitfield caption="Current Real-time Value" mask="0xFFFFFFFF" name="CRTV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="RTT_SR" offset="0x0C" rw="R" size="4">
|
||
|
|
<bitfield caption="Real-time Alarm Status" mask="0x00000001" name="ALMS"/>
|
||
|
|
<bitfield caption="Real-time Timer Increment" mask="0x00000002" name="RTTINC"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Serial Peripheral Interface" name="SPI" version="6088R">
|
||
|
|
<register-group name="SPI">
|
||
|
|
<register caption="Control Register" name="SPI_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="SPI Enable" mask="0x00000001" name="SPIEN"/>
|
||
|
|
<bitfield caption="SPI Disable" mask="0x00000002" name="SPIDIS"/>
|
||
|
|
<bitfield caption="SPI Software Reset" mask="0x00000080" name="SWRST"/>
|
||
|
|
<bitfield caption="Last Transfer" mask="0x01000000" name="LASTXFER"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="SPI_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Master/Slave Mode" mask="0x00000001" name="MSTR"/>
|
||
|
|
<bitfield caption="Peripheral Select" mask="0x00000002" name="PS"/>
|
||
|
|
<bitfield caption="Chip Select Decode" mask="0x00000004" name="PCSDEC"/>
|
||
|
|
<bitfield caption="Mode Fault Detection" mask="0x00000010" name="MODFDIS"/>
|
||
|
|
<bitfield caption="Wait Data Read Before Transfer" mask="0x00000020" name="WDRBT"/>
|
||
|
|
<bitfield caption="Local Loopback Enable" mask="0x00000080" name="LLB"/>
|
||
|
|
<bitfield caption="Peripheral Chip Select" mask="0x000F0000" name="PCS"/>
|
||
|
|
<bitfield caption="Delay Between Chip Selects" mask="0xFF000000" name="DLYBCS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Data Register" name="SPI_RDR" offset="0x08" rw="R" size="4">
|
||
|
|
<bitfield caption="Receive Data" mask="0x0000FFFF" name="RD"/>
|
||
|
|
<bitfield caption="Peripheral Chip Select" mask="0x000F0000" name="PCS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Data Register" name="SPI_TDR" offset="0x0C" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmit Data" mask="0x0000FFFF" name="TD"/>
|
||
|
|
<bitfield caption="Peripheral Chip Select" mask="0x000F0000" name="PCS"/>
|
||
|
|
<bitfield caption="Last Transfer" mask="0x01000000" name="LASTXFER"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="SPI_SR" offset="0x10" rw="R" size="4">
|
||
|
|
<bitfield caption="Receive Data Register Full" mask="0x00000001" name="RDRF"/>
|
||
|
|
<bitfield caption="Transmit Data Register Empty" mask="0x00000002" name="TDRE"/>
|
||
|
|
<bitfield caption="Mode Fault Error" mask="0x00000004" name="MODF"/>
|
||
|
|
<bitfield caption="Overrun Error Status" mask="0x00000008" name="OVRES"/>
|
||
|
|
<bitfield caption="End of RX buffer" mask="0x00000010" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of TX buffer" mask="0x00000020" name="ENDTX"/>
|
||
|
|
<bitfield caption="RX Buffer Full" mask="0x00000040" name="RXBUFF"/>
|
||
|
|
<bitfield caption="TX Buffer Empty" mask="0x00000080" name="TXBUFE"/>
|
||
|
|
<bitfield caption="NSS Rising" mask="0x00000100" name="NSSR"/>
|
||
|
|
<bitfield caption="Transmission Registers Empty" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Underrun Error Status (Slave Mode Only)" mask="0x00000400" name="UNDES"/>
|
||
|
|
<bitfield caption="SPI Enable Status" mask="0x00010000" name="SPIENS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="SPI_IER" offset="0x14" rw="W" size="4">
|
||
|
|
<bitfield caption="Receive Data Register Full Interrupt Enable" mask="0x00000001" name="RDRF"/>
|
||
|
|
<bitfield caption="SPI Transmit Data Register Empty Interrupt Enable" mask="0x00000002" name="TDRE"/>
|
||
|
|
<bitfield caption="Mode Fault Error Interrupt Enable" mask="0x00000004" name="MODF"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Enable" mask="0x00000008" name="OVRES"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Enable" mask="0x00000010" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Enable" mask="0x00000020" name="ENDTX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Enable" mask="0x00000040" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Enable" mask="0x00000080" name="TXBUFE"/>
|
||
|
|
<bitfield caption="NSS Rising Interrupt Enable" mask="0x00000100" name="NSSR"/>
|
||
|
|
<bitfield caption="Transmission Registers Empty Enable" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Underrun Error Interrupt Enable" mask="0x00000400" name="UNDES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="SPI_IDR" offset="0x18" rw="W" size="4">
|
||
|
|
<bitfield caption="Receive Data Register Full Interrupt Disable" mask="0x00000001" name="RDRF"/>
|
||
|
|
<bitfield caption="SPI Transmit Data Register Empty Interrupt Disable" mask="0x00000002" name="TDRE"/>
|
||
|
|
<bitfield caption="Mode Fault Error Interrupt Disable" mask="0x00000004" name="MODF"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Disable" mask="0x00000008" name="OVRES"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Disable" mask="0x00000010" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Disable" mask="0x00000020" name="ENDTX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Disable" mask="0x00000040" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Disable" mask="0x00000080" name="TXBUFE"/>
|
||
|
|
<bitfield caption="NSS Rising Interrupt Disable" mask="0x00000100" name="NSSR"/>
|
||
|
|
<bitfield caption="Transmission Registers Empty Disable" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Underrun Error Interrupt Disable" mask="0x00000400" name="UNDES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="SPI_IMR" offset="0x1C" rw="R" size="4">
|
||
|
|
<bitfield caption="Receive Data Register Full Interrupt Mask" mask="0x00000001" name="RDRF"/>
|
||
|
|
<bitfield caption="SPI Transmit Data Register Empty Interrupt Mask" mask="0x00000002" name="TDRE"/>
|
||
|
|
<bitfield caption="Mode Fault Error Interrupt Mask" mask="0x00000004" name="MODF"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Mask" mask="0x00000008" name="OVRES"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Mask" mask="0x00000010" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Mask" mask="0x00000020" name="ENDTX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Mask" mask="0x00000040" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Mask" mask="0x00000080" name="TXBUFE"/>
|
||
|
|
<bitfield caption="NSS Rising Interrupt Mask" mask="0x00000100" name="NSSR"/>
|
||
|
|
<bitfield caption="Transmission Registers Empty Mask" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Underrun Error Interrupt Mask" mask="0x00000400" name="UNDES"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Chip Select Register 0" name="SPI_CSR0" offset="0x30" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Polarity" mask="0x00000001" name="CPOL"/>
|
||
|
|
<bitfield caption="Clock Phase" mask="0x00000002" name="NCPHA"/>
|
||
|
|
<bitfield caption="Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" mask="0x00000004" name="CSNAAT"/>
|
||
|
|
<bitfield caption="Chip Select Active After Transfer" mask="0x00000008" name="CSAAT"/>
|
||
|
|
<bitfield caption="Bits Per Transfer" mask="0x000000F0" name="BITS" values="SPI_CSR__BITS"/>
|
||
|
|
<bitfield caption="Serial Clock Baud Rate" mask="0x0000FF00" name="SCBR"/>
|
||
|
|
<bitfield caption="Delay Before SPCK" mask="0x00FF0000" name="DLYBS"/>
|
||
|
|
<bitfield caption="Delay Between Consecutive Transfers" mask="0xFF000000" name="DLYBCT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Chip Select Register 1" name="SPI_CSR1" offset="0x34" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Polarity" mask="0x00000001" name="CPOL"/>
|
||
|
|
<bitfield caption="Clock Phase" mask="0x00000002" name="NCPHA"/>
|
||
|
|
<bitfield caption="Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" mask="0x00000004" name="CSNAAT"/>
|
||
|
|
<bitfield caption="Chip Select Active After Transfer" mask="0x00000008" name="CSAAT"/>
|
||
|
|
<bitfield caption="Bits Per Transfer" mask="0x000000F0" name="BITS" values="SPI_CSR__BITS"/>
|
||
|
|
<bitfield caption="Serial Clock Baud Rate" mask="0x0000FF00" name="SCBR"/>
|
||
|
|
<bitfield caption="Delay Before SPCK" mask="0x00FF0000" name="DLYBS"/>
|
||
|
|
<bitfield caption="Delay Between Consecutive Transfers" mask="0xFF000000" name="DLYBCT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Chip Select Register 2" name="SPI_CSR2" offset="0x38" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Polarity" mask="0x00000001" name="CPOL"/>
|
||
|
|
<bitfield caption="Clock Phase" mask="0x00000002" name="NCPHA"/>
|
||
|
|
<bitfield caption="Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" mask="0x00000004" name="CSNAAT"/>
|
||
|
|
<bitfield caption="Chip Select Active After Transfer" mask="0x00000008" name="CSAAT"/>
|
||
|
|
<bitfield caption="Bits Per Transfer" mask="0x000000F0" name="BITS" values="SPI_CSR__BITS"/>
|
||
|
|
<bitfield caption="Serial Clock Baud Rate" mask="0x0000FF00" name="SCBR"/>
|
||
|
|
<bitfield caption="Delay Before SPCK" mask="0x00FF0000" name="DLYBS"/>
|
||
|
|
<bitfield caption="Delay Between Consecutive Transfers" mask="0xFF000000" name="DLYBCT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Chip Select Register 3" name="SPI_CSR3" offset="0x3C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Polarity" mask="0x00000001" name="CPOL"/>
|
||
|
|
<bitfield caption="Clock Phase" mask="0x00000002" name="NCPHA"/>
|
||
|
|
<bitfield caption="Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" mask="0x00000004" name="CSNAAT"/>
|
||
|
|
<bitfield caption="Chip Select Active After Transfer" mask="0x00000008" name="CSAAT"/>
|
||
|
|
<bitfield caption="Bits Per Transfer" mask="0x000000F0" name="BITS" values="SPI_CSR__BITS"/>
|
||
|
|
<bitfield caption="Serial Clock Baud Rate" mask="0x0000FF00" name="SCBR"/>
|
||
|
|
<bitfield caption="Delay Before SPCK" mask="0x00FF0000" name="DLYBS"/>
|
||
|
|
<bitfield caption="Delay Between Consecutive Transfers" mask="0xFF000000" name="DLYBCT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protection Control Register" name="SPI_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protection Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protection Key Password" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protection Status Register" name="SPI_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protection Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protection Violation Source" mask="0x0000FF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="SPI_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="SPI_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="SPI_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="SPI_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="SPI_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="SPI_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="SPI_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="SPI_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="SPI_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="SPI_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="SPI_CSR__BITS">
|
||
|
|
<value caption="8 bits for transfer" name="_8_BIT" value="0x0"/>
|
||
|
|
<value caption="9 bits for transfer" name="_9_BIT" value="0x1"/>
|
||
|
|
<value caption="10 bits for transfer" name="_10_BIT" value="0x2"/>
|
||
|
|
<value caption="11 bits for transfer" name="_11_BIT" value="0x3"/>
|
||
|
|
<value caption="12 bits for transfer" name="_12_BIT" value="0x4"/>
|
||
|
|
<value caption="13 bits for transfer" name="_13_BIT" value="0x5"/>
|
||
|
|
<value caption="14 bits for transfer" name="_14_BIT" value="0x6"/>
|
||
|
|
<value caption="15 bits for transfer" name="_15_BIT" value="0x7"/>
|
||
|
|
<value caption="16 bits for transfer" name="_16_BIT" value="0x8"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SPI_CSR__BITS">
|
||
|
|
<value caption="8 bits for transfer" name="_8_BIT" value="0x0"/>
|
||
|
|
<value caption="9 bits for transfer" name="_9_BIT" value="0x1"/>
|
||
|
|
<value caption="10 bits for transfer" name="_10_BIT" value="0x2"/>
|
||
|
|
<value caption="11 bits for transfer" name="_11_BIT" value="0x3"/>
|
||
|
|
<value caption="12 bits for transfer" name="_12_BIT" value="0x4"/>
|
||
|
|
<value caption="13 bits for transfer" name="_13_BIT" value="0x5"/>
|
||
|
|
<value caption="14 bits for transfer" name="_14_BIT" value="0x6"/>
|
||
|
|
<value caption="15 bits for transfer" name="_15_BIT" value="0x7"/>
|
||
|
|
<value caption="16 bits for transfer" name="_16_BIT" value="0x8"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SPI_CSR__BITS">
|
||
|
|
<value caption="8 bits for transfer" name="_8_BIT" value="0x0"/>
|
||
|
|
<value caption="9 bits for transfer" name="_9_BIT" value="0x1"/>
|
||
|
|
<value caption="10 bits for transfer" name="_10_BIT" value="0x2"/>
|
||
|
|
<value caption="11 bits for transfer" name="_11_BIT" value="0x3"/>
|
||
|
|
<value caption="12 bits for transfer" name="_12_BIT" value="0x4"/>
|
||
|
|
<value caption="13 bits for transfer" name="_13_BIT" value="0x5"/>
|
||
|
|
<value caption="14 bits for transfer" name="_14_BIT" value="0x6"/>
|
||
|
|
<value caption="15 bits for transfer" name="_15_BIT" value="0x7"/>
|
||
|
|
<value caption="16 bits for transfer" name="_16_BIT" value="0x8"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SPI_CSR__BITS">
|
||
|
|
<value caption="8 bits for transfer" name="_8_BIT" value="0x0"/>
|
||
|
|
<value caption="9 bits for transfer" name="_9_BIT" value="0x1"/>
|
||
|
|
<value caption="10 bits for transfer" name="_10_BIT" value="0x2"/>
|
||
|
|
<value caption="11 bits for transfer" name="_11_BIT" value="0x3"/>
|
||
|
|
<value caption="12 bits for transfer" name="_12_BIT" value="0x4"/>
|
||
|
|
<value caption="13 bits for transfer" name="_13_BIT" value="0x5"/>
|
||
|
|
<value caption="14 bits for transfer" name="_14_BIT" value="0x6"/>
|
||
|
|
<value caption="15 bits for transfer" name="_15_BIT" value="0x7"/>
|
||
|
|
<value caption="16 bits for transfer" name="_16_BIT" value="0x8"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Synchronous Serial Controller" name="SSC" version="6078J">
|
||
|
|
<register-group name="SSC">
|
||
|
|
<register caption="Control Register" name="SSC_CR" offset="0x0" rw="W" size="4">
|
||
|
|
<bitfield caption="Receive Enable" mask="0x00000001" name="RXEN"/>
|
||
|
|
<bitfield caption="Receive Disable" mask="0x00000002" name="RXDIS"/>
|
||
|
|
<bitfield caption="Transmit Enable" mask="0x00000100" name="TXEN"/>
|
||
|
|
<bitfield caption="Transmit Disable" mask="0x00000200" name="TXDIS"/>
|
||
|
|
<bitfield caption="Software Reset" mask="0x00008000" name="SWRST"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Clock Mode Register" name="SSC_CMR" offset="0x4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Divider" mask="0x00000FFF" name="DIV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Clock Mode Register" name="SSC_RCMR" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Clock Selection" mask="0x00000003" name="CKS" values="SSC_RCMR__CKS"/>
|
||
|
|
<bitfield caption="Receive Clock Output Mode Selection" mask="0x0000001C" name="CKO" values="SSC_RCMR__CKO"/>
|
||
|
|
<bitfield caption="Receive Clock Inversion" mask="0x00000020" name="CKI"/>
|
||
|
|
<bitfield caption="Receive Clock Gating Selection" mask="0x000000C0" name="CKG" values="SSC_RCMR__CKG"/>
|
||
|
|
<bitfield caption="Receive Start Selection" mask="0x00000F00" name="START" values="SSC_RCMR__START"/>
|
||
|
|
<bitfield caption="Receive Stop Selection" mask="0x00001000" name="STOP"/>
|
||
|
|
<bitfield caption="Receive Start Delay" mask="0x00FF0000" name="STTDLY"/>
|
||
|
|
<bitfield caption="Receive Period Divider Selection" mask="0xFF000000" name="PERIOD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Frame Mode Register" name="SSC_RFMR" offset="0x14" rw="RW" size="4">
|
||
|
|
<bitfield caption="Data Length" mask="0x0000001F" name="DATLEN"/>
|
||
|
|
<bitfield caption="Loop Mode" mask="0x00000020" name="LOOP"/>
|
||
|
|
<bitfield caption="Most Significant Bit First" mask="0x00000080" name="MSBF"/>
|
||
|
|
<bitfield caption="Data Number per Frame" mask="0x00000F00" name="DATNB"/>
|
||
|
|
<bitfield caption="Receive Frame Sync Length" mask="0x000F0000" name="FSLEN"/>
|
||
|
|
<bitfield caption="Receive Frame Sync Output Selection" mask="0x00700000" name="FSOS" values="SSC_RFMR__FSOS"/>
|
||
|
|
<bitfield caption="Frame Sync Edge Detection" mask="0x01000000" name="FSEDGE" values="SSC_RFMR__FSEDGE"/>
|
||
|
|
<bitfield caption="FSLEN Field Extension" mask="0xF0000000" name="FSLEN_EXT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Clock Mode Register" name="SSC_TCMR" offset="0x18" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Clock Selection" mask="0x00000003" name="CKS" values="SSC_TCMR__CKS"/>
|
||
|
|
<bitfield caption="Transmit Clock Output Mode Selection" mask="0x0000001C" name="CKO" values="SSC_TCMR__CKO"/>
|
||
|
|
<bitfield caption="Transmit Clock Inversion" mask="0x00000020" name="CKI"/>
|
||
|
|
<bitfield caption="Transmit Clock Gating Selection" mask="0x000000C0" name="CKG" values="SSC_TCMR__CKG"/>
|
||
|
|
<bitfield caption="Transmit Start Selection" mask="0x00000F00" name="START" values="SSC_TCMR__START"/>
|
||
|
|
<bitfield caption="Transmit Start Delay" mask="0x00FF0000" name="STTDLY"/>
|
||
|
|
<bitfield caption="Transmit Period Divider Selection" mask="0xFF000000" name="PERIOD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Frame Mode Register" name="SSC_TFMR" offset="0x1C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Data Length" mask="0x0000001F" name="DATLEN"/>
|
||
|
|
<bitfield caption="Data Default Value" mask="0x00000020" name="DATDEF"/>
|
||
|
|
<bitfield caption="Most Significant Bit First" mask="0x00000080" name="MSBF"/>
|
||
|
|
<bitfield caption="Data Number per frame" mask="0x00000F00" name="DATNB"/>
|
||
|
|
<bitfield caption="Transmit Frame Sync Length" mask="0x000F0000" name="FSLEN"/>
|
||
|
|
<bitfield caption="Transmit Frame Sync Output Selection" mask="0x00700000" name="FSOS" values="SSC_TFMR__FSOS"/>
|
||
|
|
<bitfield caption="Frame Sync Data Enable" mask="0x00800000" name="FSDEN"/>
|
||
|
|
<bitfield caption="Frame Sync Edge Detection" mask="0x01000000" name="FSEDGE" values="SSC_TFMR__FSEDGE"/>
|
||
|
|
<bitfield caption="FSLEN Field Extension" mask="0xF0000000" name="FSLEN_EXT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Holding Register" name="SSC_RHR" offset="0x20" rw="R" size="4">
|
||
|
|
<bitfield caption="Receive Data" mask="0xFFFFFFFF" name="RDAT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Holding Register" name="SSC_THR" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmit Data" mask="0xFFFFFFFF" name="TDAT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Sync. Holding Register" name="SSC_RSHR" offset="0x30" rw="R" size="4">
|
||
|
|
<bitfield caption="Receive Synchronization Data" mask="0x0000FFFF" name="RSDAT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Sync. Holding Register" name="SSC_TSHR" offset="0x34" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Synchronization Data" mask="0x0000FFFF" name="TSDAT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Compare 0 Register" name="SSC_RC0R" offset="0x38" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Compare Data 0" mask="0x0000FFFF" name="CP0"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Compare 1 Register" name="SSC_RC1R" offset="0x3C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Compare Data 1" mask="0x0000FFFF" name="CP1"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="SSC_SR" offset="0x40" rw="R" size="4">
|
||
|
|
<bitfield caption="Transmit Ready" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="Transmit Empty" mask="0x00000002" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="End of Transmission" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Receive Ready" mask="0x00000010" name="RXRDY"/>
|
||
|
|
<bitfield caption="Receive Overrun" mask="0x00000020" name="OVRUN"/>
|
||
|
|
<bitfield caption="End of Reception" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full" mask="0x00000080" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Compare 0" mask="0x00000100" name="CP0"/>
|
||
|
|
<bitfield caption="Compare 1" mask="0x00000200" name="CP1"/>
|
||
|
|
<bitfield caption="Transmit Sync" mask="0x00000400" name="TXSYN"/>
|
||
|
|
<bitfield caption="Receive Sync" mask="0x00000800" name="RXSYN"/>
|
||
|
|
<bitfield caption="Transmit Enable" mask="0x00010000" name="TXEN"/>
|
||
|
|
<bitfield caption="Receive Enable" mask="0x00020000" name="RXEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="SSC_IER" offset="0x44" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Enable" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="Transmit Empty Interrupt Enable" mask="0x00000002" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="End of Transmission Interrupt Enable" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Enable" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Receive Ready Interrupt Enable" mask="0x00000010" name="RXRDY"/>
|
||
|
|
<bitfield caption="Receive Overrun Interrupt Enable" mask="0x00000020" name="OVRUN"/>
|
||
|
|
<bitfield caption="End of Reception Interrupt Enable" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Enable" mask="0x00000080" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Compare 0 Interrupt Enable" mask="0x00000100" name="CP0"/>
|
||
|
|
<bitfield caption="Compare 1 Interrupt Enable" mask="0x00000200" name="CP1"/>
|
||
|
|
<bitfield caption="Tx Sync Interrupt Enable" mask="0x00000400" name="TXSYN"/>
|
||
|
|
<bitfield caption="Rx Sync Interrupt Enable" mask="0x00000800" name="RXSYN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="SSC_IDR" offset="0x48" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Disable" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="Transmit Empty Interrupt Disable" mask="0x00000002" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="End of Transmission Interrupt Disable" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Disable" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Receive Ready Interrupt Disable" mask="0x00000010" name="RXRDY"/>
|
||
|
|
<bitfield caption="Receive Overrun Interrupt Disable" mask="0x00000020" name="OVRUN"/>
|
||
|
|
<bitfield caption="End of Reception Interrupt Disable" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Disable" mask="0x00000080" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Compare 0 Interrupt Disable" mask="0x00000100" name="CP0"/>
|
||
|
|
<bitfield caption="Compare 1 Interrupt Disable" mask="0x00000200" name="CP1"/>
|
||
|
|
<bitfield caption="Tx Sync Interrupt Enable" mask="0x00000400" name="TXSYN"/>
|
||
|
|
<bitfield caption="Rx Sync Interrupt Enable" mask="0x00000800" name="RXSYN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="SSC_IMR" offset="0x4C" rw="R" size="4">
|
||
|
|
<bitfield caption="Transmit Ready Interrupt Mask" mask="0x00000001" name="TXRDY"/>
|
||
|
|
<bitfield caption="Transmit Empty Interrupt Mask" mask="0x00000002" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="End of Transmission Interrupt Mask" mask="0x00000004" name="ENDTX"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Mask" mask="0x00000008" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Receive Ready Interrupt Mask" mask="0x00000010" name="RXRDY"/>
|
||
|
|
<bitfield caption="Receive Overrun Interrupt Mask" mask="0x00000020" name="OVRUN"/>
|
||
|
|
<bitfield caption="End of Reception Interrupt Mask" mask="0x00000040" name="ENDRX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Mask" mask="0x00000080" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Compare 0 Interrupt Mask" mask="0x00000100" name="CP0"/>
|
||
|
|
<bitfield caption="Compare 1 Interrupt Mask" mask="0x00000200" name="CP1"/>
|
||
|
|
<bitfield caption="Tx Sync Interrupt Mask" mask="0x00000400" name="TXSYN"/>
|
||
|
|
<bitfield caption="Rx Sync Interrupt Mask" mask="0x00000800" name="RXSYN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="SSC_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="SSC_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="SSC_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="SSC_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="SSC_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="SSC_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="SSC_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="SSC_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="SSC_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="SSC_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="SSC_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="SSC_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="SSC_RCMR__CKS">
|
||
|
|
<value caption="Divided Clock" name="MCK" value="0x0"/>
|
||
|
|
<value caption="TK Clock signal" name="TK" value="0x1"/>
|
||
|
|
<value caption="RK pin" name="RK" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_RCMR__CKO">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Continuous Receive Clock" name="CONTINUOUS" value="0x1"/>
|
||
|
|
<value caption="Receive Clock only during data transfers" name="TRANSFER" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_RCMR__CKG">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Continuous Receive Clock" name="CONTINUOUS" value="0x1"/>
|
||
|
|
<value caption="Receive Clock only during data transfers" name="TRANSFER" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_RCMR__START">
|
||
|
|
<value caption="Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data." name="CONTINUOUS" value="0x0"/>
|
||
|
|
<value caption="Transmit start" name="TRANSMIT" value="0x1"/>
|
||
|
|
<value caption="Detection of a low level on RF signal" name="RF_LOW" value="0x2"/>
|
||
|
|
<value caption="Detection of a high level on RF signal" name="RF_HIGH" value="0x3"/>
|
||
|
|
<value caption="Detection of a falling edge on RF signal" name="RF_FALLING" value="0x4"/>
|
||
|
|
<value caption="Detection of a rising edge on RF signal" name="RF_RISING" value="0x5"/>
|
||
|
|
<value caption="Detection of any level change on RF signal" name="RF_LEVEL" value="0x6"/>
|
||
|
|
<value caption="Detection of any edge on RF signal" name="RF_EDGE" value="0x7"/>
|
||
|
|
<value caption="Compare 0" name="CMP_0" value="0x8"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_RFMR__FSOS">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Negative Pulse" name="NEGATIVE" value="0x1"/>
|
||
|
|
<value caption="Positive Pulse" name="POSITIVE" value="0x2"/>
|
||
|
|
<value caption="Driven Low during data transfer" name="LOW" value="0x3"/>
|
||
|
|
<value caption="Driven High during data transfer" name="HIGH" value="0x4"/>
|
||
|
|
<value caption="Toggling at each start of data transfer" name="TOGGLING" value="0x5"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_RFMR__FSEDGE">
|
||
|
|
<value caption="Positive Edge Detection" name="POSITIVE" value="0"/>
|
||
|
|
<value caption="Negative Edge Detection" name="NEGATIVE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_TCMR__CKS">
|
||
|
|
<value caption="Divided Clock" name="MCK" value="0x0"/>
|
||
|
|
<value caption="TK Clock signal" name="TK" value="0x1"/>
|
||
|
|
<value caption="RK pin" name="RK" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_TCMR__CKO">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Continuous Receive Clock" name="CONTINUOUS" value="0x1"/>
|
||
|
|
<value caption="Transmit Clock only during data transfers" name="TRANSFER" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_TCMR__CKG">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Transmit Clock enabled only if TF Low" name="CONTINUOUS" value="0x1"/>
|
||
|
|
<value caption="Transmit Clock enabled only if TF High" name="TRANSFER" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_TCMR__START">
|
||
|
|
<value caption="Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data." name="CONTINUOUS" value="0x0"/>
|
||
|
|
<value caption="Receive start" name="RECEIVE" value="0x1"/>
|
||
|
|
<value caption="Detection of a low level on TF signal" name="RF_LOW" value="0x2"/>
|
||
|
|
<value caption="Detection of a high level on TF signal" name="RF_HIGH" value="0x3"/>
|
||
|
|
<value caption="Detection of a falling edge on TF signal" name="RF_FALLING" value="0x4"/>
|
||
|
|
<value caption="Detection of a rising edge on TF signal" name="RF_RISING" value="0x5"/>
|
||
|
|
<value caption="Detection of any level change on TF signal" name="RF_LEVEL" value="0x6"/>
|
||
|
|
<value caption="Detection of any edge on TF signal" name="RF_EDGE" value="0x7"/>
|
||
|
|
<value caption="Compare 0" name="CMP_0" value="0x8"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_TFMR__FSOS">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Negative Pulse" name="NEGATIVE" value="0x1"/>
|
||
|
|
<value caption="Positive Pulse" name="POSITIVE" value="0x2"/>
|
||
|
|
<value caption="Driven Low during data transfer" name="LOW" value="0x3"/>
|
||
|
|
<value caption="Driven High during data transfer" name="HIGH" value="0x4"/>
|
||
|
|
<value caption="Toggling at each start of data transfer" name="TOGGLING" value="0x5"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SSC_TFMR__FSEDGE">
|
||
|
|
<value caption="Positive Edge Detection" name="POSITIVE" value="0"/>
|
||
|
|
<value caption="Negative Edge Detection" name="NEGATIVE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Supply Controller" name="SUPC" version="6452M">
|
||
|
|
<register-group name="SUPC">
|
||
|
|
<register caption="Supply Controller Control Register" name="SUPC_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Voltage Regulator Off" mask="0x00000004" name="VROFF" values="SUPC_CR__VROFF"/>
|
||
|
|
<bitfield caption="Crystal Oscillator Select" mask="0x00000008" name="XTALSEL" values="SUPC_CR__XTALSEL"/>
|
||
|
|
<bitfield caption="Password" mask="0xFF000000" name="KEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Supply Controller Supply Monitor Mode Register" name="SUPC_SMMR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Supply Monitor Threshold" mask="0x0000000F" name="SMTH" values="SUPC_SMMR__SMTH"/>
|
||
|
|
<bitfield caption="Supply Monitor Sampling Period" mask="0x00000700" name="SMSMPL" values="SUPC_SMMR__SMSMPL"/>
|
||
|
|
<bitfield caption="Supply Monitor Reset Enable" mask="0x00001000" name="SMRSTEN" values="SUPC_SMMR__SMRSTEN"/>
|
||
|
|
<bitfield caption="Supply Monitor Interrupt Enable" mask="0x00002000" name="SMIEN" values="SUPC_SMMR__SMIEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Supply Controller Mode Register" name="SUPC_MR" offset="0x08" rw="RW" size="4">
|
||
|
|
<bitfield caption="Brownout Detector Reset Enable" mask="0x00001000" name="BODRSTEN" values="SUPC_MR__BODRSTEN"/>
|
||
|
|
<bitfield caption="Brownout Detector Disable" mask="0x00002000" name="BODDIS" values="SUPC_MR__BODDIS"/>
|
||
|
|
<bitfield caption="Voltage Regulator enable" mask="0x00004000" name="ONREG" values="SUPC_MR__ONREG"/>
|
||
|
|
<bitfield caption="Oscillator Bypass" mask="0x00100000" name="OSCBYPASS" values="SUPC_MR__OSCBYPASS"/>
|
||
|
|
<bitfield caption="Password Key" mask="0xFF000000" name="KEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Supply Controller Wake Up Mode Register" name="SUPC_WUMR" offset="0x0C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Supply Monitor Wake Up Enable" mask="0x00000002" name="SMEN" values="SUPC_WUMR__SMEN"/>
|
||
|
|
<bitfield caption="Real Time Timer Wake Up Enable" mask="0x00000004" name="RTTEN" values="SUPC_WUMR__RTTEN"/>
|
||
|
|
<bitfield caption="Real Time Clock Wake Up Enable" mask="0x00000008" name="RTCEN" values="SUPC_WUMR__RTCEN"/>
|
||
|
|
<bitfield caption="Low power Debouncer ENable WKUP0" mask="0x00000020" name="LPDBCEN0" values="SUPC_WUMR__LPDBCEN0"/>
|
||
|
|
<bitfield caption="Low power Debouncer ENable WKUP1" mask="0x00000040" name="LPDBCEN1" values="SUPC_WUMR__LPDBCEN1"/>
|
||
|
|
<bitfield caption="Low power Debouncer Clear" mask="0x00000080" name="LPDBCCLR" values="SUPC_WUMR__LPDBCCLR"/>
|
||
|
|
<bitfield caption="Wake Up Inputs Debouncer Period" mask="0x00007000" name="WKUPDBC" values="SUPC_WUMR__WKUPDBC"/>
|
||
|
|
<bitfield caption="Low Power DeBounCer Period" mask="0x00070000" name="LPDBC" values="SUPC_WUMR__LPDBC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Supply Controller Wake Up Inputs Register" name="SUPC_WUIR" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Wake Up Input Enable 0" mask="0x00000001" name="WKUPEN0" values="SUPC_WUIR__WKUPEN0"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 1" mask="0x00000002" name="WKUPEN1" values="SUPC_WUIR__WKUPEN1"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 2" mask="0x00000004" name="WKUPEN2" values="SUPC_WUIR__WKUPEN2"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 3" mask="0x00000008" name="WKUPEN3" values="SUPC_WUIR__WKUPEN3"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 4" mask="0x00000010" name="WKUPEN4" values="SUPC_WUIR__WKUPEN4"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 5" mask="0x00000020" name="WKUPEN5" values="SUPC_WUIR__WKUPEN5"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 6" mask="0x00000040" name="WKUPEN6" values="SUPC_WUIR__WKUPEN6"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 7" mask="0x00000080" name="WKUPEN7" values="SUPC_WUIR__WKUPEN7"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 8" mask="0x00000100" name="WKUPEN8" values="SUPC_WUIR__WKUPEN8"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 9" mask="0x00000200" name="WKUPEN9" values="SUPC_WUIR__WKUPEN9"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 10" mask="0x00000400" name="WKUPEN10" values="SUPC_WUIR__WKUPEN10"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 11" mask="0x00000800" name="WKUPEN11" values="SUPC_WUIR__WKUPEN11"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 12" mask="0x00001000" name="WKUPEN12" values="SUPC_WUIR__WKUPEN12"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 13" mask="0x00002000" name="WKUPEN13" values="SUPC_WUIR__WKUPEN13"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 14" mask="0x00004000" name="WKUPEN14" values="SUPC_WUIR__WKUPEN14"/>
|
||
|
|
<bitfield caption="Wake Up Input Enable 15" mask="0x00008000" name="WKUPEN15" values="SUPC_WUIR__WKUPEN15"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 0" mask="0x00010000" name="WKUPT0" values="SUPC_WUIR__WKUPT0"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 1" mask="0x00020000" name="WKUPT1" values="SUPC_WUIR__WKUPT1"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 2" mask="0x00040000" name="WKUPT2" values="SUPC_WUIR__WKUPT2"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 3" mask="0x00080000" name="WKUPT3" values="SUPC_WUIR__WKUPT3"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 4" mask="0x00100000" name="WKUPT4" values="SUPC_WUIR__WKUPT4"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 5" mask="0x00200000" name="WKUPT5" values="SUPC_WUIR__WKUPT5"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 6" mask="0x00400000" name="WKUPT6" values="SUPC_WUIR__WKUPT6"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 7" mask="0x00800000" name="WKUPT7" values="SUPC_WUIR__WKUPT7"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 8" mask="0x01000000" name="WKUPT8" values="SUPC_WUIR__WKUPT8"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 9" mask="0x02000000" name="WKUPT9" values="SUPC_WUIR__WKUPT9"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 10" mask="0x04000000" name="WKUPT10" values="SUPC_WUIR__WKUPT10"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 11" mask="0x08000000" name="WKUPT11" values="SUPC_WUIR__WKUPT11"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 12" mask="0x10000000" name="WKUPT12" values="SUPC_WUIR__WKUPT12"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 13" mask="0x20000000" name="WKUPT13" values="SUPC_WUIR__WKUPT13"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 14" mask="0x40000000" name="WKUPT14" values="SUPC_WUIR__WKUPT14"/>
|
||
|
|
<bitfield caption="Wake Up Input Type 15" mask="0x80000000" name="WKUPT15" values="SUPC_WUIR__WKUPT15"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Supply Controller Status Register" name="SUPC_SR" offset="0x14" rw="R" size="4">
|
||
|
|
<bitfield caption="WKUP Wake Up Status" mask="0x00000002" name="WKUPS" values="SUPC_SR__WKUPS"/>
|
||
|
|
<bitfield caption="Supply Monitor Detection Wake Up Status" mask="0x00000004" name="SMWS" values="SUPC_SR__SMWS"/>
|
||
|
|
<bitfield caption="Brownout Detector Reset Status" mask="0x00000008" name="BODRSTS" values="SUPC_SR__BODRSTS"/>
|
||
|
|
<bitfield caption="Supply Monitor Reset Status" mask="0x00000010" name="SMRSTS" values="SUPC_SR__SMRSTS"/>
|
||
|
|
<bitfield caption="Supply Monitor Status" mask="0x00000020" name="SMS" values="SUPC_SR__SMS"/>
|
||
|
|
<bitfield caption="Supply Monitor Output Status" mask="0x00000040" name="SMOS" values="SUPC_SR__SMOS"/>
|
||
|
|
<bitfield caption="32-kHz Oscillator Selection Status" mask="0x00000080" name="OSCSEL" values="SUPC_SR__OSCSEL"/>
|
||
|
|
<bitfield caption="Low Power Debouncer Wake Up Status on WKUP0" mask="0x00002000" name="LPDBCS0" values="SUPC_SR__LPDBCS0"/>
|
||
|
|
<bitfield caption="Low Power Debouncer Wake Up Status on WKUP1" mask="0x00004000" name="LPDBCS1" values="SUPC_SR__LPDBCS1"/>
|
||
|
|
<bitfield caption="WKUP Input Status 0" mask="0x00010000" name="WKUPIS0" values="SUPC_SR__WKUPIS0"/>
|
||
|
|
<bitfield caption="WKUP Input Status 1" mask="0x00020000" name="WKUPIS1" values="SUPC_SR__WKUPIS1"/>
|
||
|
|
<bitfield caption="WKUP Input Status 2" mask="0x00040000" name="WKUPIS2" values="SUPC_SR__WKUPIS2"/>
|
||
|
|
<bitfield caption="WKUP Input Status 3" mask="0x00080000" name="WKUPIS3" values="SUPC_SR__WKUPIS3"/>
|
||
|
|
<bitfield caption="WKUP Input Status 4" mask="0x00100000" name="WKUPIS4" values="SUPC_SR__WKUPIS4"/>
|
||
|
|
<bitfield caption="WKUP Input Status 5" mask="0x00200000" name="WKUPIS5" values="SUPC_SR__WKUPIS5"/>
|
||
|
|
<bitfield caption="WKUP Input Status 6" mask="0x00400000" name="WKUPIS6" values="SUPC_SR__WKUPIS6"/>
|
||
|
|
<bitfield caption="WKUP Input Status 7" mask="0x00800000" name="WKUPIS7" values="SUPC_SR__WKUPIS7"/>
|
||
|
|
<bitfield caption="WKUP Input Status 8" mask="0x01000000" name="WKUPIS8" values="SUPC_SR__WKUPIS8"/>
|
||
|
|
<bitfield caption="WKUP Input Status 9" mask="0x02000000" name="WKUPIS9" values="SUPC_SR__WKUPIS9"/>
|
||
|
|
<bitfield caption="WKUP Input Status 10" mask="0x04000000" name="WKUPIS10" values="SUPC_SR__WKUPIS10"/>
|
||
|
|
<bitfield caption="WKUP Input Status 11" mask="0x08000000" name="WKUPIS11" values="SUPC_SR__WKUPIS11"/>
|
||
|
|
<bitfield caption="WKUP Input Status 12" mask="0x10000000" name="WKUPIS12" values="SUPC_SR__WKUPIS12"/>
|
||
|
|
<bitfield caption="WKUP Input Status 13" mask="0x20000000" name="WKUPIS13" values="SUPC_SR__WKUPIS13"/>
|
||
|
|
<bitfield caption="WKUP Input Status 14" mask="0x40000000" name="WKUPIS14" values="SUPC_SR__WKUPIS14"/>
|
||
|
|
<bitfield caption="WKUP Input Status 15" mask="0x80000000" name="WKUPIS15" values="SUPC_SR__WKUPIS15"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="SUPC_CR__VROFF">
|
||
|
|
<value caption="no effect." name="NO_EFFECT" value="0"/>
|
||
|
|
<value caption="if KEY is correct, asserts vddcore_nreset and stops the voltage regulator." name="STOP_VREG" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_CR__XTALSEL">
|
||
|
|
<value caption="no effect." name="NO_EFFECT" value="0"/>
|
||
|
|
<value caption="if KEY is correct, switches the slow clock on the crystal oscillator output." name="CRYSTAL_SEL" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SMMR__SMTH">
|
||
|
|
<value caption="1.9 V" name="_1_9V" value="0x0"/>
|
||
|
|
<value caption="2.0 V" name="_2_0V" value="0x1"/>
|
||
|
|
<value caption="2.1 V" name="_2_1V" value="0x2"/>
|
||
|
|
<value caption="2.2 V" name="_2_2V" value="0x3"/>
|
||
|
|
<value caption="2.3 V" name="_2_3V" value="0x4"/>
|
||
|
|
<value caption="2.4 V" name="_2_4V" value="0x5"/>
|
||
|
|
<value caption="2.5 V" name="_2_5V" value="0x6"/>
|
||
|
|
<value caption="2.6 V" name="_2_6V" value="0x7"/>
|
||
|
|
<value caption="2.7 V" name="_2_7V" value="0x8"/>
|
||
|
|
<value caption="2.8 V" name="_2_8V" value="0x9"/>
|
||
|
|
<value caption="2.9 V" name="_2_9V" value="0xA"/>
|
||
|
|
<value caption="3.0 V" name="_3_0V" value="0xB"/>
|
||
|
|
<value caption="3.1 V" name="_3_1V" value="0xC"/>
|
||
|
|
<value caption="3.2 V" name="_3_2V" value="0xD"/>
|
||
|
|
<value caption="3.3 V" name="_3_3V" value="0xE"/>
|
||
|
|
<value caption="3.4 V" name="_3_4V" value="0xF"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SMMR__SMSMPL">
|
||
|
|
<value caption="Supply Monitor disabled" name="SMD" value="0x0"/>
|
||
|
|
<value caption="Continuous Supply Monitor" name="CSM" value="0x1"/>
|
||
|
|
<value caption="Supply Monitor enabled one SLCK period every 32 SLCK periods" name="_32SLCK" value="0x2"/>
|
||
|
|
<value caption="Supply Monitor enabled one SLCK period every 256 SLCK periods" name="_256SLCK" value="0x3"/>
|
||
|
|
<value caption="Supply Monitor enabled one SLCK period every 2,048 SLCK periods" name="_2048SLCK" value="0x4"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SMMR__SMRSTEN">
|
||
|
|
<value caption="the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SMMR__SMIEN">
|
||
|
|
<value caption="the SUPC interrupt signal is not affected when a supply monitor detection occurs." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the SUPC interrupt signal is asserted when a supply monitor detection occurs." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_MR__BODRSTEN">
|
||
|
|
<value caption="the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the core reset signal, vddcore_nreset is asserted when a brownout detection occurs." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_MR__BODDIS">
|
||
|
|
<value caption="the core brownout detector is enabled." name="ENABLE" value="0"/>
|
||
|
|
<value caption="the core brownout detector is disabled." name="DISABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_MR__ONREG">
|
||
|
|
<value caption="Voltage Regulator is not used" name="ONREG_UNUSED" value="0"/>
|
||
|
|
<value caption="Voltage Regulator is used" name="ONREG_USED" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_MR__OSCBYPASS">
|
||
|
|
<value caption="no effect. Clock selection depends on XTALSEL value." name="NO_EFFECT" value="0"/>
|
||
|
|
<value caption="the 32-KHz XTAL oscillator is selected and is put in bypass mode." name="BYPASS" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__SMEN">
|
||
|
|
<value caption="the supply monitor detection has no wake up effect." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the supply monitor detection forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__RTTEN">
|
||
|
|
<value caption="the RTT alarm signal has no wake up effect." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the RTT alarm signal forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__RTCEN">
|
||
|
|
<value caption="the RTC alarm signal has no wake up effect." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the RTC alarm signal forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__LPDBCEN0">
|
||
|
|
<value caption="the WKUP0 input pin is not connected with low power debouncer." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the WKUP0 input pin is connected with low power debouncer and can force a core wake up." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__LPDBCEN1">
|
||
|
|
<value caption="the WKUP1input pin is not connected with low power debouncer." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="the WKUP1 input pin is connected with low power debouncer and can force a core wake up." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__LPDBCCLR">
|
||
|
|
<value caption="a low power debounce event does not create an immediate clear on first half GPBR registers." name="NOT_ENABLE" value="0"/>
|
||
|
|
<value caption="a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on first half GPBR registers." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__WKUPDBC">
|
||
|
|
<value caption="Immediate, no debouncing, detected active at least on one Slow Clock edge." name="IMMEDIATE" value="0x0"/>
|
||
|
|
<value caption="WKUPx shall be in its active state for at least 3 SLCK periods" name="_3_SCLK" value="0x1"/>
|
||
|
|
<value caption="WKUPx shall be in its active state for at least 32 SLCK periods" name="_32_SCLK" value="0x2"/>
|
||
|
|
<value caption="WKUPx shall be in its active state for at least 512 SLCK periods" name="_512_SCLK" value="0x3"/>
|
||
|
|
<value caption="WKUPx shall be in its active state for at least 4,096 SLCK periods" name="_4096_SCLK" value="0x4"/>
|
||
|
|
<value caption="WKUPx shall be in its active state for at least 32,768 SLCK periods" name="_32768_SCLK" value="0x5"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUMR__LPDBC">
|
||
|
|
<value caption="Disable the low power debouncer." name="DISABLE" value="0x0"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 2 RTCOUT0 periods" name="_2_RTCOUT0" value="0x1"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 3 RTCOUT0 periods" name="_3_RTCOUT0" value="0x2"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 4 RTCOUT0 periods" name="_4_RTCOUT0" value="0x3"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 5 RTCOUT0 periods" name="_5_RTCOUT0" value="0x4"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 6 RTCOUT0 periods" name="_6_RTCOUT0" value="0x5"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 7 RTCOUT0 periods" name="_7_RTCOUT0" value="0x6"/>
|
||
|
|
<value caption="WKUP0/1 in its active state for at least 8 RTCOUT0 periods" name="_8_RTCOUT0" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN0">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN1">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN2">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN3">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN4">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN5">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN6">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN7">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN8">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN9">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN10">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN11">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN12">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN13">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN14">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPEN15">
|
||
|
|
<value caption="the corresponding wake-up input has no wake up effect." name="DISABLE" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input forces the wake up of the core power supply." name="ENABLE" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT0">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT1">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT2">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT3">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT4">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT5">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT6">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT7">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT8">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT9">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT10">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT11">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT12">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT13">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT14">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_WUIR__WKUPT15">
|
||
|
|
<value caption="a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake up of the core power supply." name="LOW" value="0"/>
|
||
|
|
<value caption="a high levelfor a period defined by WKUPDBC on the correspond-ing wake-up input forces the wake up of the core power supply." name="HIGH" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPS">
|
||
|
|
<value caption="no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__SMWS">
|
||
|
|
<value caption="no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__BODRSTS">
|
||
|
|
<value caption="no core brownout rising edge event has been detected since the last read of the SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one brownout output rising edge event has been detected since the last read of the SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__SMRSTS">
|
||
|
|
<value caption="no supply monitor detection has generated a core reset since the last read of the SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__SMS">
|
||
|
|
<value caption="no supply monitor detection since the last read of SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one supply monitor detection since the last read of SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__SMOS">
|
||
|
|
<value caption="the supply monitor detected VDDIO higher than its threshold at its last measurement." name="HIGH" value="0"/>
|
||
|
|
<value caption="the supply monitor detected VDDIO lower than its threshold at its last measurement." name="LOW" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__OSCSEL">
|
||
|
|
<value caption="the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator." name="RC" value="0"/>
|
||
|
|
<value caption="the slow clock, SLCK is generated by the 32-kHz crystal oscillator." name="CRYST" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__LPDBCS0">
|
||
|
|
<value caption="no wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one wake up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__LPDBCS1">
|
||
|
|
<value caption="no wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR." name="NO" value="0"/>
|
||
|
|
<value caption="at least one wake up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR." name="PRESENT" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS0">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS1">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS2">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS3">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS4">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS5">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS6">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS7">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS8">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS9">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS10">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS11">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS12">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS13">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS14">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="SUPC_SR__WKUPIS15">
|
||
|
|
<value caption="the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event." name="DIS" value="0"/>
|
||
|
|
<value caption="the corresponding wake-up input was active at the time the debouncer triggered a wake up event." name="EN" value="1"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Timer Counter" name="TC" version="6082Q">
|
||
|
|
<register-group name="TC">
|
||
|
|
<register caption="Channel Control Register (channel = 0)" name="TC_CCR0" offset="0x0" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Clock Enable Command" mask="0x00000001" name="CLKEN"/>
|
||
|
|
<bitfield caption="Counter Clock Disable Command" mask="0x00000002" name="CLKDIS"/>
|
||
|
|
<bitfield caption="Software Trigger Command" mask="0x00000004" name="SWTRG"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Mode Register (channel = 0)" name="TC_CMR0" offset="0x4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Selection" mask="0x00000007" name="TCCLKS" values="TC_CMR0__TCCLKS"/>
|
||
|
|
<bitfield caption="Clock Invert" mask="0x00000008" name="CLKI"/>
|
||
|
|
<bitfield caption="Burst Signal Selection" mask="0x00000030" name="BURST" values="TC_CMR0__BURST"/>
|
||
|
|
<bitfield caption="Counter Clock Stopped with RB Loading" mask="0x00000040" name="LDBSTOP"/>
|
||
|
|
<bitfield caption="Counter Clock Disable with RB Loading" mask="0x00000080" name="LDBDIS"/>
|
||
|
|
<bitfield caption="External Trigger Edge Selection" mask="0x00000300" name="ETRGEDG" values="TC_CMR0__ETRGEDG"/>
|
||
|
|
<bitfield caption="TIOA or TIOB External Trigger Selection" mask="0x00000400" name="ABETRG"/>
|
||
|
|
<bitfield caption="RC Compare Trigger Enable" mask="0x00004000" name="CPCTRG"/>
|
||
|
|
<bitfield caption="Waveform Mode" mask="0x00008000" name="WAVE"/>
|
||
|
|
<bitfield caption="RA Loading Edge Selection" mask="0x00030000" name="LDRA" values="TC_CMR0__LDRA"/>
|
||
|
|
<bitfield caption="RB Loading Edge Selection" mask="0x000C0000" name="LDRB" values="TC_CMR0__LDRB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Stepper Motor Mode Register (channel = 0)" name="TC_SMMR0" offset="0x8" rw="RW" size="4">
|
||
|
|
<bitfield caption="Gray Count Enable" mask="0x00000001" name="GCEN"/>
|
||
|
|
<bitfield caption="DOWN Count" mask="0x00000002" name="DOWN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Counter Value (channel = 0)" name="TC_CV0" offset="0x10" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Value" mask="0xFFFFFFFF" name="CV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register A (channel = 0)" name="TC_RA0" offset="0x14" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register A" mask="0xFFFFFFFF" name="RA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register B (channel = 0)" name="TC_RB0" offset="0x18" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register B" mask="0xFFFFFFFF" name="RB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register C (channel = 0)" name="TC_RC0" offset="0x1C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register C" mask="0xFFFFFFFF" name="RC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register (channel = 0)" name="TC_SR0" offset="0x20" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Overflow Status" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun Status" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare Status" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare Status" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare Status" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading Status" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading Status" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger Status" mask="0x00000080" name="ETRGS"/>
|
||
|
|
<bitfield caption="Clock Enabling Status" mask="0x00010000" name="CLKSTA"/>
|
||
|
|
<bitfield caption="TIOA Mirror" mask="0x00020000" name="MTIOA"/>
|
||
|
|
<bitfield caption="TIOB Mirror" mask="0x00040000" name="MTIOB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register (channel = 0)" name="TC_IER0" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register (channel = 0)" name="TC_IDR0" offset="0x28" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register (channel = 0)" name="TC_IMR0" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Control Register (channel = 1)" name="TC_CCR1" offset="0x40" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Clock Enable Command" mask="0x00000001" name="CLKEN"/>
|
||
|
|
<bitfield caption="Counter Clock Disable Command" mask="0x00000002" name="CLKDIS"/>
|
||
|
|
<bitfield caption="Software Trigger Command" mask="0x00000004" name="SWTRG"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Mode Register (channel = 1)" name="TC_CMR1" offset="0x44" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Selection" mask="0x00000007" name="TCCLKS" values="TC_CMR1__TCCLKS"/>
|
||
|
|
<bitfield caption="Clock Invert" mask="0x00000008" name="CLKI"/>
|
||
|
|
<bitfield caption="Burst Signal Selection" mask="0x00000030" name="BURST" values="TC_CMR1__BURST"/>
|
||
|
|
<bitfield caption="Counter Clock Stopped with RB Loading" mask="0x00000040" name="LDBSTOP"/>
|
||
|
|
<bitfield caption="Counter Clock Disable with RB Loading" mask="0x00000080" name="LDBDIS"/>
|
||
|
|
<bitfield caption="External Trigger Edge Selection" mask="0x00000300" name="ETRGEDG" values="TC_CMR1__ETRGEDG"/>
|
||
|
|
<bitfield caption="TIOA or TIOB External Trigger Selection" mask="0x00000400" name="ABETRG"/>
|
||
|
|
<bitfield caption="RC Compare Trigger Enable" mask="0x00004000" name="CPCTRG"/>
|
||
|
|
<bitfield caption="Waveform Mode" mask="0x00008000" name="WAVE"/>
|
||
|
|
<bitfield caption="RA Loading Edge Selection" mask="0x00030000" name="LDRA" values="TC_CMR1__LDRA"/>
|
||
|
|
<bitfield caption="RB Loading Edge Selection" mask="0x000C0000" name="LDRB" values="TC_CMR1__LDRB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Stepper Motor Mode Register (channel = 1)" name="TC_SMMR1" offset="0x48" rw="RW" size="4">
|
||
|
|
<bitfield caption="Gray Count Enable" mask="0x00000001" name="GCEN"/>
|
||
|
|
<bitfield caption="DOWN Count" mask="0x00000002" name="DOWN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Counter Value (channel = 1)" name="TC_CV1" offset="0x50" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Value" mask="0xFFFFFFFF" name="CV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register A (channel = 1)" name="TC_RA1" offset="0x54" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register A" mask="0xFFFFFFFF" name="RA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register B (channel = 1)" name="TC_RB1" offset="0x58" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register B" mask="0xFFFFFFFF" name="RB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register C (channel = 1)" name="TC_RC1" offset="0x5C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register C" mask="0xFFFFFFFF" name="RC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register (channel = 1)" name="TC_SR1" offset="0x60" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Overflow Status" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun Status" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare Status" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare Status" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare Status" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading Status" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading Status" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger Status" mask="0x00000080" name="ETRGS"/>
|
||
|
|
<bitfield caption="Clock Enabling Status" mask="0x00010000" name="CLKSTA"/>
|
||
|
|
<bitfield caption="TIOA Mirror" mask="0x00020000" name="MTIOA"/>
|
||
|
|
<bitfield caption="TIOB Mirror" mask="0x00040000" name="MTIOB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register (channel = 1)" name="TC_IER1" offset="0x64" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register (channel = 1)" name="TC_IDR1" offset="0x68" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register (channel = 1)" name="TC_IMR1" offset="0x6C" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Control Register (channel = 2)" name="TC_CCR2" offset="0x80" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Clock Enable Command" mask="0x00000001" name="CLKEN"/>
|
||
|
|
<bitfield caption="Counter Clock Disable Command" mask="0x00000002" name="CLKDIS"/>
|
||
|
|
<bitfield caption="Software Trigger Command" mask="0x00000004" name="SWTRG"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Mode Register (channel = 2)" name="TC_CMR2" offset="0x84" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Selection" mask="0x00000007" name="TCCLKS" values="TC_CMR2__TCCLKS"/>
|
||
|
|
<bitfield caption="Clock Invert" mask="0x00000008" name="CLKI"/>
|
||
|
|
<bitfield caption="Burst Signal Selection" mask="0x00000030" name="BURST" values="TC_CMR2__BURST"/>
|
||
|
|
<bitfield caption="Counter Clock Stopped with RB Loading" mask="0x00000040" name="LDBSTOP"/>
|
||
|
|
<bitfield caption="Counter Clock Disable with RB Loading" mask="0x00000080" name="LDBDIS"/>
|
||
|
|
<bitfield caption="External Trigger Edge Selection" mask="0x00000300" name="ETRGEDG" values="TC_CMR2__ETRGEDG"/>
|
||
|
|
<bitfield caption="TIOA or TIOB External Trigger Selection" mask="0x00000400" name="ABETRG"/>
|
||
|
|
<bitfield caption="RC Compare Trigger Enable" mask="0x00004000" name="CPCTRG"/>
|
||
|
|
<bitfield caption="Waveform Mode" mask="0x00008000" name="WAVE"/>
|
||
|
|
<bitfield caption="RA Loading Edge Selection" mask="0x00030000" name="LDRA" values="TC_CMR2__LDRA"/>
|
||
|
|
<bitfield caption="RB Loading Edge Selection" mask="0x000C0000" name="LDRB" values="TC_CMR2__LDRB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Stepper Motor Mode Register (channel = 2)" name="TC_SMMR2" offset="0x88" rw="RW" size="4">
|
||
|
|
<bitfield caption="Gray Count Enable" mask="0x00000001" name="GCEN"/>
|
||
|
|
<bitfield caption="DOWN Count" mask="0x00000002" name="DOWN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Counter Value (channel = 2)" name="TC_CV2" offset="0x90" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Value" mask="0xFFFFFFFF" name="CV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register A (channel = 2)" name="TC_RA2" offset="0x94" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register A" mask="0xFFFFFFFF" name="RA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register B (channel = 2)" name="TC_RB2" offset="0x98" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register B" mask="0xFFFFFFFF" name="RB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Register C (channel = 2)" name="TC_RC2" offset="0x9C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Register C" mask="0xFFFFFFFF" name="RC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register (channel = 2)" name="TC_SR2" offset="0xA0" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Overflow Status" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun Status" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare Status" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare Status" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare Status" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading Status" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading Status" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger Status" mask="0x00000080" name="ETRGS"/>
|
||
|
|
<bitfield caption="Clock Enabling Status" mask="0x00010000" name="CLKSTA"/>
|
||
|
|
<bitfield caption="TIOA Mirror" mask="0x00020000" name="MTIOA"/>
|
||
|
|
<bitfield caption="TIOB Mirror" mask="0x00040000" name="MTIOB"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register (channel = 2)" name="TC_IER2" offset="0xA4" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register (channel = 2)" name="TC_IDR2" offset="0xA8" rw="W" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register (channel = 2)" name="TC_IMR2" offset="0xAC" rw="R" size="4">
|
||
|
|
<bitfield caption="Counter Overflow" mask="0x00000001" name="COVFS"/>
|
||
|
|
<bitfield caption="Load Overrun" mask="0x00000002" name="LOVRS"/>
|
||
|
|
<bitfield caption="RA Compare" mask="0x00000004" name="CPAS"/>
|
||
|
|
<bitfield caption="RB Compare" mask="0x00000008" name="CPBS"/>
|
||
|
|
<bitfield caption="RC Compare" mask="0x00000010" name="CPCS"/>
|
||
|
|
<bitfield caption="RA Loading" mask="0x00000020" name="LDRAS"/>
|
||
|
|
<bitfield caption="RB Loading" mask="0x00000040" name="LDRBS"/>
|
||
|
|
<bitfield caption="External Trigger" mask="0x00000080" name="ETRGS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Block Control Register" name="TC_BCR" offset="0xC0" rw="W" size="4">
|
||
|
|
<bitfield caption="Synchro Command" mask="0x00000001" name="SYNC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Block Mode Register" name="TC_BMR" offset="0xC4" rw="RW" size="4">
|
||
|
|
<bitfield caption="External Clock Signal 0 Selection" mask="0x00000003" name="TC0XC0S" values="TC_BMR__TC0XC0S"/>
|
||
|
|
<bitfield caption="External Clock Signal 1 Selection" mask="0x0000000C" name="TC1XC1S" values="TC_BMR__TC1XC1S"/>
|
||
|
|
<bitfield caption="External Clock Signal 2 Selection" mask="0x00000030" name="TC2XC2S" values="TC_BMR__TC2XC2S"/>
|
||
|
|
<bitfield caption="Quadrature Decoder ENabled" mask="0x00000100" name="QDEN"/>
|
||
|
|
<bitfield caption="POSition ENabled" mask="0x00000200" name="POSEN"/>
|
||
|
|
<bitfield caption="SPEED ENabled" mask="0x00000400" name="SPEEDEN"/>
|
||
|
|
<bitfield caption="Quadrature Decoding TRANSparent" mask="0x00000800" name="QDTRANS"/>
|
||
|
|
<bitfield caption="EDGe on PHA count mode" mask="0x00001000" name="EDGPHA"/>
|
||
|
|
<bitfield caption="INVerted phA" mask="0x00002000" name="INVA"/>
|
||
|
|
<bitfield caption="INVerted phB" mask="0x00004000" name="INVB"/>
|
||
|
|
<bitfield caption="INVerted InDeX" mask="0x00008000" name="INVIDX"/>
|
||
|
|
<bitfield caption="SWAP PHA and PHB" mask="0x00010000" name="SWAP"/>
|
||
|
|
<bitfield caption="InDeX pin is PHB pin" mask="0x00020000" name="IDXPHB"/>
|
||
|
|
<bitfield caption="" mask="0x00080000" name="FILTER"/>
|
||
|
|
<bitfield caption="MAXimum FILTer" mask="0x03F00000" name="MAXFILT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="QDEC Interrupt Enable Register" name="TC_QIER" offset="0xC8" rw="W" size="4">
|
||
|
|
<bitfield caption="InDeX" mask="0x00000001" name="IDX"/>
|
||
|
|
<bitfield caption="DIRection CHanGe" mask="0x00000002" name="DIRCHG"/>
|
||
|
|
<bitfield caption="Quadrature ERRor" mask="0x00000004" name="QERR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="QDEC Interrupt Disable Register" name="TC_QIDR" offset="0xCC" rw="W" size="4">
|
||
|
|
<bitfield caption="InDeX" mask="0x00000001" name="IDX"/>
|
||
|
|
<bitfield caption="DIRection CHanGe" mask="0x00000002" name="DIRCHG"/>
|
||
|
|
<bitfield caption="Quadrature ERRor" mask="0x00000004" name="QERR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="QDEC Interrupt Mask Register" name="TC_QIMR" offset="0xD0" rw="R" size="4">
|
||
|
|
<bitfield caption="InDeX" mask="0x00000001" name="IDX"/>
|
||
|
|
<bitfield caption="DIRection CHanGe" mask="0x00000002" name="DIRCHG"/>
|
||
|
|
<bitfield caption="Quadrature ERRor" mask="0x00000004" name="QERR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="QDEC Interrupt Status Register" name="TC_QISR" offset="0xD4" rw="R" size="4">
|
||
|
|
<bitfield caption="InDeX" mask="0x00000001" name="IDX"/>
|
||
|
|
<bitfield caption="DIRection CHanGe" mask="0x00000002" name="DIRCHG"/>
|
||
|
|
<bitfield caption="Quadrature ERRor" mask="0x00000004" name="QERR"/>
|
||
|
|
<bitfield caption="DIRection" mask="0x00000100" name="DIR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Fault Mode Register" name="TC_FMR" offset="0xD8" rw="RW" size="4">
|
||
|
|
<bitfield caption="ENable Compare Fault Channel 0" mask="0x00000001" name="ENCF0"/>
|
||
|
|
<bitfield caption="ENable Compare Fault Channel 1" mask="0x00000002" name="ENCF1"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="TC_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="TC_CMR0__TCCLKS">
|
||
|
|
<value caption="Clock selected: TCLK1" name="TIMER_CLOCK1" value="0x0"/>
|
||
|
|
<value caption="Clock selected: TCLK2" name="TIMER_CLOCK2" value="0x1"/>
|
||
|
|
<value caption="Clock selected: TCLK3" name="TIMER_CLOCK3" value="0x2"/>
|
||
|
|
<value caption="Clock selected: TCLK4" name="TIMER_CLOCK4" value="0x3"/>
|
||
|
|
<value caption="Clock selected: TCLK5" name="TIMER_CLOCK5" value="0x4"/>
|
||
|
|
<value caption="Clock selected: XC0" name="XC0" value="0x5"/>
|
||
|
|
<value caption="Clock selected: XC1" name="XC1" value="0x6"/>
|
||
|
|
<value caption="Clock selected: XC2" name="XC2" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR0__BURST">
|
||
|
|
<value caption="The clock is not gated by an external signal." name="NONE" value="0x0"/>
|
||
|
|
<value caption="XC0 is ANDed with the selected clock." name="XC0" value="0x1"/>
|
||
|
|
<value caption="XC1 is ANDed with the selected clock." name="XC1" value="0x2"/>
|
||
|
|
<value caption="XC2 is ANDed with the selected clock." name="XC2" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR0__ETRGEDG">
|
||
|
|
<value caption="The clock is not gated by an external signal." name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR0__LDRA">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge of TIOA" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge of TIOA" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge of TIOA" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR0__LDRB">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge of TIOA" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge of TIOA" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge of TIOA" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR1__TCCLKS">
|
||
|
|
<value caption="Clock selected: TCLK1" name="TIMER_CLOCK1" value="0x0"/>
|
||
|
|
<value caption="Clock selected: TCLK2" name="TIMER_CLOCK2" value="0x1"/>
|
||
|
|
<value caption="Clock selected: TCLK3" name="TIMER_CLOCK3" value="0x2"/>
|
||
|
|
<value caption="Clock selected: TCLK4" name="TIMER_CLOCK4" value="0x3"/>
|
||
|
|
<value caption="Clock selected: TCLK5" name="TIMER_CLOCK5" value="0x4"/>
|
||
|
|
<value caption="Clock selected: XC0" name="XC0" value="0x5"/>
|
||
|
|
<value caption="Clock selected: XC1" name="XC1" value="0x6"/>
|
||
|
|
<value caption="Clock selected: XC2" name="XC2" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR1__BURST">
|
||
|
|
<value caption="The clock is not gated by an external signal." name="NONE" value="0x0"/>
|
||
|
|
<value caption="XC0 is ANDed with the selected clock." name="XC0" value="0x1"/>
|
||
|
|
<value caption="XC1 is ANDed with the selected clock." name="XC1" value="0x2"/>
|
||
|
|
<value caption="XC2 is ANDed with the selected clock." name="XC2" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR1__ETRGEDG">
|
||
|
|
<value caption="The clock is not gated by an external signal." name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR1__LDRA">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge of TIOA" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge of TIOA" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge of TIOA" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR1__LDRB">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge of TIOA" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge of TIOA" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge of TIOA" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR2__TCCLKS">
|
||
|
|
<value caption="Clock selected: TCLK1" name="TIMER_CLOCK1" value="0x0"/>
|
||
|
|
<value caption="Clock selected: TCLK2" name="TIMER_CLOCK2" value="0x1"/>
|
||
|
|
<value caption="Clock selected: TCLK3" name="TIMER_CLOCK3" value="0x2"/>
|
||
|
|
<value caption="Clock selected: TCLK4" name="TIMER_CLOCK4" value="0x3"/>
|
||
|
|
<value caption="Clock selected: TCLK5" name="TIMER_CLOCK5" value="0x4"/>
|
||
|
|
<value caption="Clock selected: XC0" name="XC0" value="0x5"/>
|
||
|
|
<value caption="Clock selected: XC1" name="XC1" value="0x6"/>
|
||
|
|
<value caption="Clock selected: XC2" name="XC2" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR2__BURST">
|
||
|
|
<value caption="The clock is not gated by an external signal." name="NONE" value="0x0"/>
|
||
|
|
<value caption="XC0 is ANDed with the selected clock." name="XC0" value="0x1"/>
|
||
|
|
<value caption="XC1 is ANDed with the selected clock." name="XC1" value="0x2"/>
|
||
|
|
<value caption="XC2 is ANDed with the selected clock." name="XC2" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR2__ETRGEDG">
|
||
|
|
<value caption="The clock is not gated by an external signal." name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR2__LDRA">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge of TIOA" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge of TIOA" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge of TIOA" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_CMR2__LDRB">
|
||
|
|
<value caption="None" name="NONE" value="0x0"/>
|
||
|
|
<value caption="Rising edge of TIOA" name="RISING" value="0x1"/>
|
||
|
|
<value caption="Falling edge of TIOA" name="FALLING" value="0x2"/>
|
||
|
|
<value caption="Each edge of TIOA" name="EDGE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_BMR__TC0XC0S">
|
||
|
|
<value caption="Signal connected to XC0: TCLK0" name="TCLK0" value="0x0"/>
|
||
|
|
<value caption="Signal connected to XC0: TIOA1" name="TIOA1" value="0x2"/>
|
||
|
|
<value caption="Signal connected to XC0: TIOA2" name="TIOA2" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_BMR__TC1XC1S">
|
||
|
|
<value caption="Signal connected to XC1: TCLK1" name="TCLK1" value="0x0"/>
|
||
|
|
<value caption="Signal connected to XC1: TIOA0" name="TIOA0" value="0x2"/>
|
||
|
|
<value caption="Signal connected to XC1: TIOA2" name="TIOA2" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="TC_BMR__TC2XC2S">
|
||
|
|
<value caption="Signal connected to XC2: TCLK2" name="TCLK2" value="0x0"/>
|
||
|
|
<value caption="Signal connected to XC2: TIOA1" name="TIOA1" value="0x2"/>
|
||
|
|
<value caption="Signal connected to XC2: TIOA2" name="TIOA2" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Two-wire Interface" name="TWI" version="6212L">
|
||
|
|
<register-group name="TWI">
|
||
|
|
<register caption="Control Register" name="TWI_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Send a START Condition" mask="0x00000001" name="START"/>
|
||
|
|
<bitfield caption="Send a STOP Condition" mask="0x00000002" name="STOP"/>
|
||
|
|
<bitfield caption="TWI Master Mode Enabled" mask="0x00000004" name="MSEN"/>
|
||
|
|
<bitfield caption="TWI Master Mode Disabled" mask="0x00000008" name="MSDIS"/>
|
||
|
|
<bitfield caption="TWI Slave Mode Enabled" mask="0x00000010" name="SVEN"/>
|
||
|
|
<bitfield caption="TWI Slave Mode Disabled" mask="0x00000020" name="SVDIS"/>
|
||
|
|
<bitfield caption="SMBUS Quick Command" mask="0x00000040" name="QUICK"/>
|
||
|
|
<bitfield caption="Software Reset" mask="0x00000080" name="SWRST"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Master Mode Register" name="TWI_MMR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Internal Device Address Size" mask="0x00000300" name="IADRSZ" values="TWI_MMR__IADRSZ"/>
|
||
|
|
<bitfield caption="Master Read Direction" mask="0x00001000" name="MREAD"/>
|
||
|
|
<bitfield caption="Device Address" mask="0x007F0000" name="DADR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Slave Mode Register" name="TWI_SMR" offset="0x08" rw="RW" size="4">
|
||
|
|
<bitfield caption="Slave Address" mask="0x007F0000" name="SADR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Internal Address Register" name="TWI_IADR" offset="0x0C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Internal Address" mask="0x00FFFFFF" name="IADR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Clock Waveform Generator Register" name="TWI_CWGR" offset="0x10" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Low Divider" mask="0x000000FF" name="CLDIV"/>
|
||
|
|
<bitfield caption="Clock High Divider" mask="0x0000FF00" name="CHDIV"/>
|
||
|
|
<bitfield caption="Clock Divider" mask="0x00070000" name="CKDIV"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="TWI_SR" offset="0x20" rw="R" size="4">
|
||
|
|
<bitfield caption="Transmission Completed (automatically set / reset)" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Holding Register Ready (automatically set / reset)" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Holding Register Ready (automatically set / reset)" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Slave Read (automatically set / reset)" mask="0x00000008" name="SVREAD"/>
|
||
|
|
<bitfield caption="Slave Access (automatically set / reset)" mask="0x00000010" name="SVACC"/>
|
||
|
|
<bitfield caption="General Call Access (clear on read)" mask="0x00000020" name="GACC"/>
|
||
|
|
<bitfield caption="Overrun Error (clear on read)" mask="0x00000040" name="OVRE"/>
|
||
|
|
<bitfield caption="Not Acknowledged (clear on read)" mask="0x00000100" name="NACK"/>
|
||
|
|
<bitfield caption="Arbitration Lost (clear on read)" mask="0x00000200" name="ARBLST"/>
|
||
|
|
<bitfield caption="Clock Wait State (automatically set / reset)" mask="0x00000400" name="SCLWS"/>
|
||
|
|
<bitfield caption="End Of Slave Access (clear on read)" mask="0x00000800" name="EOSACC"/>
|
||
|
|
<bitfield caption="End of RX buffer" mask="0x00001000" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of TX buffer" mask="0x00002000" name="ENDTX"/>
|
||
|
|
<bitfield caption="RX Buffer Full" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="TX Buffer Empty" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="TWI_IER" offset="0x24" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmission Completed Interrupt Enable" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Holding Register Ready Interrupt Enable" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Holding Register Ready Interrupt Enable" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Slave Access Interrupt Enable" mask="0x00000010" name="SVACC"/>
|
||
|
|
<bitfield caption="General Call Access Interrupt Enable" mask="0x00000020" name="GACC"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Enable" mask="0x00000040" name="OVRE"/>
|
||
|
|
<bitfield caption="Not Acknowledge Interrupt Enable" mask="0x00000100" name="NACK"/>
|
||
|
|
<bitfield caption="Arbitration Lost Interrupt Enable" mask="0x00000200" name="ARBLST"/>
|
||
|
|
<bitfield caption="Clock Wait State Interrupt Enable" mask="0x00000400" name="SCL_WS"/>
|
||
|
|
<bitfield caption="End Of Slave Access Interrupt Enable" mask="0x00000800" name="EOSACC"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Enable" mask="0x00001000" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Enable" mask="0x00002000" name="ENDTX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Enable" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Enable" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="TWI_IDR" offset="0x28" rw="W" size="4">
|
||
|
|
<bitfield caption="Transmission Completed Interrupt Disable" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Holding Register Ready Interrupt Disable" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Holding Register Ready Interrupt Disable" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Slave Access Interrupt Disable" mask="0x00000010" name="SVACC"/>
|
||
|
|
<bitfield caption="General Call Access Interrupt Disable" mask="0x00000020" name="GACC"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Disable" mask="0x00000040" name="OVRE"/>
|
||
|
|
<bitfield caption="Not Acknowledge Interrupt Disable" mask="0x00000100" name="NACK"/>
|
||
|
|
<bitfield caption="Arbitration Lost Interrupt Disable" mask="0x00000200" name="ARBLST"/>
|
||
|
|
<bitfield caption="Clock Wait State Interrupt Disable" mask="0x00000400" name="SCL_WS"/>
|
||
|
|
<bitfield caption="End Of Slave Access Interrupt Disable" mask="0x00000800" name="EOSACC"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Disable" mask="0x00001000" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Disable" mask="0x00002000" name="ENDTX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Disable" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Disable" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="TWI_IMR" offset="0x2C" rw="R" size="4">
|
||
|
|
<bitfield caption="Transmission Completed Interrupt Mask" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Holding Register Ready Interrupt Mask" mask="0x00000002" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmit Holding Register Ready Interrupt Mask" mask="0x00000004" name="TXRDY"/>
|
||
|
|
<bitfield caption="Slave Access Interrupt Mask" mask="0x00000010" name="SVACC"/>
|
||
|
|
<bitfield caption="General Call Access Interrupt Mask" mask="0x00000020" name="GACC"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Mask" mask="0x00000040" name="OVRE"/>
|
||
|
|
<bitfield caption="Not Acknowledge Interrupt Mask" mask="0x00000100" name="NACK"/>
|
||
|
|
<bitfield caption="Arbitration Lost Interrupt Mask" mask="0x00000200" name="ARBLST"/>
|
||
|
|
<bitfield caption="Clock Wait State Interrupt Mask" mask="0x00000400" name="SCL_WS"/>
|
||
|
|
<bitfield caption="End Of Slave Access Interrupt Mask" mask="0x00000800" name="EOSACC"/>
|
||
|
|
<bitfield caption="End of Receive Buffer Interrupt Mask" mask="0x00001000" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Buffer Interrupt Mask" mask="0x00002000" name="ENDTX"/>
|
||
|
|
<bitfield caption="Receive Buffer Full Interrupt Mask" mask="0x00004000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Transmit Buffer Empty Interrupt Mask" mask="0x00008000" name="TXBUFE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Holding Register" name="TWI_RHR" offset="0x30" rw="R" size="4">
|
||
|
|
<bitfield caption="Master or Slave Receive Holding Data" mask="0x000000FF" name="RXDATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Holding Register" name="TWI_THR" offset="0x34" rw="W" size="4">
|
||
|
|
<bitfield caption="Master or Slave Transmit Holding Data" mask="0x000000FF" name="TXDATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="TWI_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="TWI_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="TWI_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="TWI_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="TWI_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="TWI_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="TWI_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="TWI_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="TWI_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="TWI_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="TWI_MMR__IADRSZ">
|
||
|
|
<value caption="No internal device address" name="NONE" value="0x0"/>
|
||
|
|
<value caption="One-byte internal device address" name="_1_BYTE" value="0x1"/>
|
||
|
|
<value caption="Two-byte internal device address" name="_2_BYTE" value="0x2"/>
|
||
|
|
<value caption="Three-byte internal device address" name="_3_BYTE" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Universal Asynchronous Receiver Transmitter" name="UART" version="6418E">
|
||
|
|
<register-group name="UART">
|
||
|
|
<register caption="Control Register" name="UART_CR" offset="0x0000" rw="W" size="4">
|
||
|
|
<bitfield caption="Reset Receiver" mask="0x00000004" name="RSTRX"/>
|
||
|
|
<bitfield caption="Reset Transmitter" mask="0x00000008" name="RSTTX"/>
|
||
|
|
<bitfield caption="Receiver Enable" mask="0x00000010" name="RXEN"/>
|
||
|
|
<bitfield caption="Receiver Disable" mask="0x00000020" name="RXDIS"/>
|
||
|
|
<bitfield caption="Transmitter Enable" mask="0x00000040" name="TXEN"/>
|
||
|
|
<bitfield caption="Transmitter Disable" mask="0x00000080" name="TXDIS"/>
|
||
|
|
<bitfield caption="Reset Status Bits" mask="0x00000100" name="RSTSTA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="UART_MR" offset="0x0004" rw="RW" size="4">
|
||
|
|
<bitfield caption="Parity Type" mask="0x00000E00" name="PAR" values="UART_MR__PAR"/>
|
||
|
|
<bitfield caption="Channel Mode" mask="0x0000C000" name="CHMODE" values="UART_MR__CHMODE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="UART_IER" offset="0x0008" rw="W" size="4">
|
||
|
|
<bitfield caption="Enable RXRDY Interrupt" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="Enable TXRDY Interrupt" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Enable End of Receive Transfer Interrupt" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="Enable End of Transmit Interrupt" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Enable Overrun Error Interrupt" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Enable Framing Error Interrupt" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Enable Parity Error Interrupt" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Enable TXEMPTY Interrupt" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Enable Buffer Empty Interrupt" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Enable Buffer Full Interrupt" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="UART_IDR" offset="0x000C" rw="W" size="4">
|
||
|
|
<bitfield caption="Disable RXRDY Interrupt" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="Disable TXRDY Interrupt" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Disable End of Receive Transfer Interrupt" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="Disable End of Transmit Interrupt" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Disable Overrun Error Interrupt" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Disable Framing Error Interrupt" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Disable Parity Error Interrupt" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Disable TXEMPTY Interrupt" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Disable Buffer Empty Interrupt" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Disable Buffer Full Interrupt" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="UART_IMR" offset="0x0010" rw="R" size="4">
|
||
|
|
<bitfield caption="Mask RXRDY Interrupt" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="Disable TXRDY Interrupt" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Mask End of Receive Transfer Interrupt" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="Mask End of Transmit Interrupt" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Mask Overrun Error Interrupt" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Mask Framing Error Interrupt" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Mask Parity Error Interrupt" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Mask TXEMPTY Interrupt" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Mask TXBUFE Interrupt" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Mask RXBUFF Interrupt" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="UART_SR" offset="0x0014" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Ready" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmitter Ready" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="End of Receiver Transfer" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmitter Transfer" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Overrun Error" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Framing Error" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Parity Error" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Transmitter Empty" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Transmission Buffer Empty" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Receive Buffer Full" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Holding Register" name="UART_RHR" offset="0x0018" rw="R" size="4">
|
||
|
|
<bitfield caption="Received Character" mask="0x000000FF" name="RXCHR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Holding Register" name="UART_THR" offset="0x001C" rw="W" size="4">
|
||
|
|
<bitfield caption="Character to be Transmitted" mask="0x000000FF" name="TXCHR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Baud Rate Generator Register" name="UART_BRGR" offset="0x0020" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Divisor" mask="0x0000FFFF" name="CD"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="UART_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="UART_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="UART_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="UART_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="UART_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="UART_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="UART_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="UART_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="UART_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="UART_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="UART_MR__PAR">
|
||
|
|
<value caption="Even parity" name="EVEN" value="0x0"/>
|
||
|
|
<value caption="Odd parity" name="ODD" value="0x1"/>
|
||
|
|
<value caption="Space: parity forced to 0" name="SPACE" value="0x2"/>
|
||
|
|
<value caption="Mark: parity forced to 1" name="MARK" value="0x3"/>
|
||
|
|
<value caption="No parity" name="NO" value="0x4"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UART_MR__CHMODE">
|
||
|
|
<value caption="Normal Mode" name="NORMAL" value="0x0"/>
|
||
|
|
<value caption="Automatic Echo" name="AUTOMATIC" value="0x1"/>
|
||
|
|
<value caption="Local Loopback" name="LOCAL_LOOPBACK" value="0x2"/>
|
||
|
|
<value caption="Remote Loopback" name="REMOTE_LOOPBACK" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="USB Device Port" name="UDP" version="6083V">
|
||
|
|
<register-group name="UDP">
|
||
|
|
<register caption="Frame Number Register" name="UDP_FRM_NUM" offset="0x000" rw="R" size="4">
|
||
|
|
<bitfield caption="Frame Number as Defined in the Packet Field Formats" mask="0x000007FF" name="FRM_NUM"/>
|
||
|
|
<bitfield caption="Frame Error" mask="0x00010000" name="FRM_ERR"/>
|
||
|
|
<bitfield caption="Frame OK" mask="0x00020000" name="FRM_OK"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Global State Register" name="UDP_GLB_STAT" offset="0x004" rw="RW" size="4">
|
||
|
|
<bitfield caption="Function Address Enable" mask="0x00000001" name="FADDEN"/>
|
||
|
|
<bitfield caption="Configured" mask="0x00000002" name="CONFG"/>
|
||
|
|
<bitfield caption="Enable Send Resume" mask="0x00000004" name="ESR"/>
|
||
|
|
<bitfield mask="0x00000008" name="RSMINPR"/>
|
||
|
|
<bitfield caption="Remote Wake Up Enable" mask="0x00000010" name="RMWUPE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Function Address Register" name="UDP_FADDR" offset="0x008" rw="RW" size="4">
|
||
|
|
<bitfield caption="Function Address Value" mask="0x0000007F" name="FADD"/>
|
||
|
|
<bitfield caption="Function Enable" mask="0x00000100" name="FEN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="UDP_IER" offset="0x010" rw="W" size="4">
|
||
|
|
<bitfield caption="Enable Endpoint 0 Interrupt" mask="0x00000001" name="EP0INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 1 Interrupt" mask="0x00000002" name="EP1INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 2Interrupt" mask="0x00000004" name="EP2INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 3 Interrupt" mask="0x00000008" name="EP3INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 4 Interrupt" mask="0x00000010" name="EP4INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 5 Interrupt" mask="0x00000020" name="EP5INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 6 Interrupt" mask="0x00000040" name="EP6INT"/>
|
||
|
|
<bitfield caption="Enable Endpoint 7 Interrupt" mask="0x00000080" name="EP7INT"/>
|
||
|
|
<bitfield caption="Enable UDP Suspend Interrupt" mask="0x00000100" name="RXSUSP"/>
|
||
|
|
<bitfield caption="Enable UDP Resume Interrupt" mask="0x00000200" name="RXRSM"/>
|
||
|
|
<bitfield mask="0x00000400" name="EXTRSM"/>
|
||
|
|
<bitfield caption="Enable Start Of Frame Interrupt" mask="0x00000800" name="SOFINT"/>
|
||
|
|
<bitfield caption="Enable UDP bus Wakeup Interrupt" mask="0x00002000" name="WAKEUP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="UDP_IDR" offset="0x014" rw="W" size="4">
|
||
|
|
<bitfield caption="Disable Endpoint 0 Interrupt" mask="0x00000001" name="EP0INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 1 Interrupt" mask="0x00000002" name="EP1INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 2 Interrupt" mask="0x00000004" name="EP2INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 3 Interrupt" mask="0x00000008" name="EP3INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 4 Interrupt" mask="0x00000010" name="EP4INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 5 Interrupt" mask="0x00000020" name="EP5INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 6 Interrupt" mask="0x00000040" name="EP6INT"/>
|
||
|
|
<bitfield caption="Disable Endpoint 7 Interrupt" mask="0x00000080" name="EP7INT"/>
|
||
|
|
<bitfield caption="Disable UDP Suspend Interrupt" mask="0x00000100" name="RXSUSP"/>
|
||
|
|
<bitfield caption="Disable UDP Resume Interrupt" mask="0x00000200" name="RXRSM"/>
|
||
|
|
<bitfield mask="0x00000400" name="EXTRSM"/>
|
||
|
|
<bitfield caption="Disable Start Of Frame Interrupt" mask="0x00000800" name="SOFINT"/>
|
||
|
|
<bitfield caption="Disable USB Bus Interrupt" mask="0x00002000" name="WAKEUP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="UDP_IMR" offset="0x018" rw="R" size="4">
|
||
|
|
<bitfield caption="Mask Endpoint 0 Interrupt" mask="0x00000001" name="EP0INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 1 Interrupt" mask="0x00000002" name="EP1INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 2 Interrupt" mask="0x00000004" name="EP2INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 3 Interrupt" mask="0x00000008" name="EP3INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 4 Interrupt" mask="0x00000010" name="EP4INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 5 Interrupt" mask="0x00000020" name="EP5INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 6 Interrupt" mask="0x00000040" name="EP6INT"/>
|
||
|
|
<bitfield caption="Mask Endpoint 7 Interrupt" mask="0x00000080" name="EP7INT"/>
|
||
|
|
<bitfield caption="Mask UDP Suspend Interrupt" mask="0x00000100" name="RXSUSP"/>
|
||
|
|
<bitfield caption="Mask UDP Resume Interrupt." mask="0x00000200" name="RXRSM"/>
|
||
|
|
<bitfield mask="0x00000400" name="EXTRSM"/>
|
||
|
|
<bitfield caption="Mask Start Of Frame Interrupt" mask="0x00000800" name="SOFINT"/>
|
||
|
|
<bitfield caption="UDP_IMR Bit 12" mask="0x00001000" name="BIT12"/>
|
||
|
|
<bitfield caption="USB Bus WAKEUP Interrupt" mask="0x00002000" name="WAKEUP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Status Register" name="UDP_ISR" offset="0x01C" rw="R" size="4">
|
||
|
|
<bitfield caption="Endpoint 0 Interrupt Status" mask="0x00000001" name="EP0INT"/>
|
||
|
|
<bitfield caption="Endpoint 1 Interrupt Status" mask="0x00000002" name="EP1INT"/>
|
||
|
|
<bitfield caption="Endpoint 2 Interrupt Status" mask="0x00000004" name="EP2INT"/>
|
||
|
|
<bitfield caption="Endpoint 3 Interrupt Status" mask="0x00000008" name="EP3INT"/>
|
||
|
|
<bitfield caption="Endpoint 4 Interrupt Status" mask="0x00000010" name="EP4INT"/>
|
||
|
|
<bitfield caption="Endpoint 5 Interrupt Status" mask="0x00000020" name="EP5INT"/>
|
||
|
|
<bitfield caption="Endpoint 6 Interrupt Status" mask="0x00000040" name="EP6INT"/>
|
||
|
|
<bitfield caption="Endpoint 7Interrupt Status" mask="0x00000080" name="EP7INT"/>
|
||
|
|
<bitfield caption="UDP Suspend Interrupt Status" mask="0x00000100" name="RXSUSP"/>
|
||
|
|
<bitfield caption="UDP Resume Interrupt Status" mask="0x00000200" name="RXRSM"/>
|
||
|
|
<bitfield mask="0x00000400" name="EXTRSM"/>
|
||
|
|
<bitfield caption="Start of Frame Interrupt Status" mask="0x00000800" name="SOFINT"/>
|
||
|
|
<bitfield caption="End of BUS Reset Interrupt Status" mask="0x00001000" name="ENDBUSRES"/>
|
||
|
|
<bitfield caption="UDP Resume Interrupt Status" mask="0x00002000" name="WAKEUP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Clear Register" name="UDP_ICR" offset="0x020" rw="W" size="4">
|
||
|
|
<bitfield caption="Clear UDP Suspend Interrupt" mask="0x00000100" name="RXSUSP"/>
|
||
|
|
<bitfield caption="Clear UDP Resume Interrupt" mask="0x00000200" name="RXRSM"/>
|
||
|
|
<bitfield mask="0x00000400" name="EXTRSM"/>
|
||
|
|
<bitfield caption="Clear Start Of Frame Interrupt" mask="0x00000800" name="SOFINT"/>
|
||
|
|
<bitfield caption="Clear End of Bus Reset Interrupt" mask="0x00001000" name="ENDBUSRES"/>
|
||
|
|
<bitfield caption="Clear Wakeup Interrupt" mask="0x00002000" name="WAKEUP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Reset Endpoint Register" name="UDP_RST_EP" offset="0x028" rw="RW" size="4">
|
||
|
|
<bitfield caption="Reset Endpoint 0" mask="0x00000001" name="EP0"/>
|
||
|
|
<bitfield caption="Reset Endpoint 1" mask="0x00000002" name="EP1"/>
|
||
|
|
<bitfield caption="Reset Endpoint 2" mask="0x00000004" name="EP2"/>
|
||
|
|
<bitfield caption="Reset Endpoint 3" mask="0x00000008" name="EP3"/>
|
||
|
|
<bitfield caption="Reset Endpoint 4" mask="0x00000010" name="EP4"/>
|
||
|
|
<bitfield caption="Reset Endpoint 5" mask="0x00000020" name="EP5"/>
|
||
|
|
<bitfield caption="Reset Endpoint 6" mask="0x00000040" name="EP6"/>
|
||
|
|
<bitfield caption="Reset Endpoint 7" mask="0x00000080" name="EP7"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 0" name="UDP_CSR0" offset="0x30" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 1" name="UDP_CSR1" offset="0x34" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 2" name="UDP_CSR2" offset="0x38" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 3" name="UDP_CSR3" offset="0x3C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 4" name="UDP_CSR4" offset="0x40" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 5" name="UDP_CSR5" offset="0x44" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 6" name="UDP_CSR6" offset="0x48" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint Control and Status Register 7" name="UDP_CSR7" offset="0x4C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Generates an IN Packet with Data Previously Written in the DPR" mask="0x00000001" name="TXCOMP"/>
|
||
|
|
<bitfield caption="Receive Data Bank 0" mask="0x00000002" name="RX_DATA_BK0"/>
|
||
|
|
<bitfield caption="Received Setup" mask="0x00000004" name="RXSETUP"/>
|
||
|
|
<bitfield caption="Stall Sent" mask="0x00000008" name="STALLSENT"/>
|
||
|
|
<bitfield caption="Transmit Packet Ready" mask="0x00000010" name="TXPKTRDY"/>
|
||
|
|
<bitfield caption="Force Stall (used by Control, Bulk and Isochronous Endpoints)" mask="0x00000020" name="FORCESTALL"/>
|
||
|
|
<bitfield caption="Receive Data Bank 1 (only used by endpoints with ping-pong attributes)" mask="0x00000040" name="RX_DATA_BK1"/>
|
||
|
|
<bitfield caption="Transfer Direction (only available for control endpoints)" mask="0x00000080" name="DIR"/>
|
||
|
|
<bitfield caption="Endpoint Type" mask="0x00000700" name="EPTYPE" values="UDP_CSR__EPTYPE"/>
|
||
|
|
<bitfield caption="Data Toggle" mask="0x00000800" name="DTGLE"/>
|
||
|
|
<bitfield caption="Endpoint Enable Disable" mask="0x00008000" name="EPEDS"/>
|
||
|
|
<bitfield caption="Number of Bytes Available in the FIFO" mask="0x07FF0000" name="RXBYTECNT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 0" name="UDP_FDR0" offset="0x50" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 1" name="UDP_FDR1" offset="0x54" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 2" name="UDP_FDR2" offset="0x58" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 3" name="UDP_FDR3" offset="0x5C" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 4" name="UDP_FDR4" offset="0x60" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 5" name="UDP_FDR5" offset="0x64" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 6" name="UDP_FDR6" offset="0x68" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Endpoint FIFO Data Register 7" name="UDP_FDR7" offset="0x6C" rw="RW" size="4">
|
||
|
|
<bitfield caption="FIFO Data Value" mask="0x000000FF" name="FIFO_DATA"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transceiver Control Register" name="UDP_TXVC" offset="0x074" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transceiver Disable" mask="0x00000100" name="TXVDIS"/>
|
||
|
|
<bitfield caption="Pull-up On" mask="0x00000200" name="PUON"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="UDP_CSR__EPTYPE">
|
||
|
|
<value caption="Control" name="CTRL" value="0x0"/>
|
||
|
|
<value caption="Isochronous OUT" name="ISO_OUT" value="0x1"/>
|
||
|
|
<value caption="Bulk OUT" name="BULK_OUT" value="0x2"/>
|
||
|
|
<value caption="Interrupt OUT" name="INT_OUT" value="0x3"/>
|
||
|
|
<value caption="Isochronous IN" name="ISO_IN" value="0x5"/>
|
||
|
|
<value caption="Bulk IN" name="BULK_IN" value="0x6"/>
|
||
|
|
<value caption="Interrupt IN" name="INT_IN" value="0x7"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Universal Synchronous Asynchronous Receiver Transmitter" name="USART" version="6089Y">
|
||
|
|
<register-group name="USART">
|
||
|
|
<register caption="Control Register" name="US_CR" offset="0x0000" rw="W" size="4">
|
||
|
|
<bitfield caption="Reset Receiver" mask="0x00000004" name="RSTRX"/>
|
||
|
|
<bitfield caption="Reset Transmitter" mask="0x00000008" name="RSTTX"/>
|
||
|
|
<bitfield caption="Receiver Enable" mask="0x00000010" name="RXEN"/>
|
||
|
|
<bitfield caption="Receiver Disable" mask="0x00000020" name="RXDIS"/>
|
||
|
|
<bitfield caption="Transmitter Enable" mask="0x00000040" name="TXEN"/>
|
||
|
|
<bitfield caption="Transmitter Disable" mask="0x00000080" name="TXDIS"/>
|
||
|
|
<bitfield caption="Reset Status Bits" mask="0x00000100" name="RSTSTA"/>
|
||
|
|
<bitfield caption="Start Break" mask="0x00000200" name="STTBRK"/>
|
||
|
|
<bitfield caption="Stop Break" mask="0x00000400" name="STPBRK"/>
|
||
|
|
<bitfield caption="Start Time-out" mask="0x00000800" name="STTTO"/>
|
||
|
|
<bitfield caption="Send Address" mask="0x00001000" name="SENDA"/>
|
||
|
|
<bitfield caption="Reset Iterations" mask="0x00002000" name="RSTIT"/>
|
||
|
|
<bitfield caption="Reset Non Acknowledge" mask="0x00004000" name="RSTNACK"/>
|
||
|
|
<bitfield caption="Rearm Time-out" mask="0x00008000" name="RETTO"/>
|
||
|
|
<bitfield caption="Data Terminal Ready Enable" mask="0x00010000" name="DTREN"/>
|
||
|
|
<bitfield caption="Data Terminal Ready Disable" mask="0x00020000" name="DTRDIS"/>
|
||
|
|
<bitfield caption="Request to Send Enable" mask="0x00040000" name="RTSEN"/>
|
||
|
|
<bitfield caption="Request to Send Disable" mask="0x00080000" name="RTSDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="US_MR" offset="0x0004" rw="RW" size="4">
|
||
|
|
<bitfield caption="USART Mode of Operation" mask="0x0000000F" name="USART_MODE" values="US_MR__USART_MODE"/>
|
||
|
|
<bitfield caption="Clock Selection" mask="0x00000030" name="USCLKS" values="US_MR__USCLKS"/>
|
||
|
|
<bitfield caption="Character Length." mask="0x000000C0" name="CHRL" values="US_MR__CHRL"/>
|
||
|
|
<bitfield caption="Synchronous Mode Select" mask="0x00000100" name="SYNC"/>
|
||
|
|
<bitfield caption="Parity Type" mask="0x00000E00" name="PAR" values="US_MR__PAR"/>
|
||
|
|
<bitfield caption="Number of Stop Bits" mask="0x00003000" name="NBSTOP" values="US_MR__NBSTOP"/>
|
||
|
|
<bitfield caption="Channel Mode" mask="0x0000C000" name="CHMODE" values="US_MR__CHMODE"/>
|
||
|
|
<bitfield caption="Bit Order" mask="0x00010000" name="MSBF"/>
|
||
|
|
<bitfield caption="9-bit Character Length" mask="0x00020000" name="MODE9"/>
|
||
|
|
<bitfield caption="Clock Output Select" mask="0x00040000" name="CLKO"/>
|
||
|
|
<bitfield caption="Oversampling Mode" mask="0x00080000" name="OVER"/>
|
||
|
|
<bitfield caption="Inhibit Non Acknowledge" mask="0x00100000" name="INACK"/>
|
||
|
|
<bitfield caption="Disable Successive NACK" mask="0x00200000" name="DSNACK"/>
|
||
|
|
<bitfield caption="Variable Synchronization of Command/Data Sync Start Frame Delimiter" mask="0x00400000" name="VAR_SYNC"/>
|
||
|
|
<bitfield caption="INverted Data" mask="0x00800000" name="INVDATA"/>
|
||
|
|
<bitfield caption="Maximum Number of Automatic Iteration" mask="0x07000000" name="MAX_ITERATION"/>
|
||
|
|
<bitfield caption="Infrared Receive Line Filter" mask="0x10000000" name="FILTER"/>
|
||
|
|
<bitfield caption="Manchester Encoder/Decoder Enable" mask="0x20000000" name="MAN"/>
|
||
|
|
<bitfield caption="Manchester Synchronization Mode" mask="0x40000000" name="MODSYNC"/>
|
||
|
|
<bitfield caption="Start Frame Delimiter Selector" mask="0x80000000" name="ONEBIT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Enable Register" name="US_IER" offset="0x0008" rw="W" size="4">
|
||
|
|
<bitfield caption="RXRDY Interrupt Enable" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="TXRDY Interrupt Enable" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Receiver Break Interrupt Enable" mask="0x00000004" name="RXBRK"/>
|
||
|
|
<bitfield caption="End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Interrupt Enable (available in all USART modes of operation)" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Enable" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Framing Error Interrupt Enable" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Parity Error Interrupt Enable" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Time-out Interrupt Enable" mask="0x00000100" name="TIMEOUT"/>
|
||
|
|
<bitfield caption="TXEMPTY Interrupt Enable" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Max number of Repetitions Reached Interrupt Enable" mask="0x00000400" name="ITER"/>
|
||
|
|
<bitfield caption="Buffer Empty Interrupt Enable (available in all USART modes of operation)" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Buffer Full Interrupt Enable (available in all USART modes of operation)" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Non AcknowledgeInterrupt Enable" mask="0x00002000" name="NACK"/>
|
||
|
|
<bitfield caption="Ring Indicator Input Change Enable" mask="0x00010000" name="RIIC"/>
|
||
|
|
<bitfield caption="Data Set Ready Input Change Enable" mask="0x00020000" name="DSRIC"/>
|
||
|
|
<bitfield caption="Data Carrier Detect Input Change Interrupt Enable" mask="0x00040000" name="DCDIC"/>
|
||
|
|
<bitfield caption="Clear to Send Input Change Interrupt Enable" mask="0x00080000" name="CTSIC"/>
|
||
|
|
<bitfield caption="Manchester Error Interrupt Enable" mask="0x01000000" name="MANE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Disable Register" name="US_IDR" offset="0x000C" rw="W" size="4">
|
||
|
|
<bitfield caption="RXRDY Interrupt Disable" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="TXRDY Interrupt Disable" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Receiver Break Interrupt Disable" mask="0x00000004" name="RXBRK"/>
|
||
|
|
<bitfield caption="End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Interrupt Disable (available in all USART modes of operation)" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Enable" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Framing Error Interrupt Disable" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Parity Error Interrupt Disable" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Time-out Interrupt Disable" mask="0x00000100" name="TIMEOUT"/>
|
||
|
|
<bitfield caption="TXEMPTY Interrupt Disable" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Max number of Repetitions Reached Interrupt Disable" mask="0x00000400" name="ITER"/>
|
||
|
|
<bitfield caption="Buffer Empty Interrupt Disable (available in all USART modes of operation)" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Buffer Full Interrupt Disable (available in all USART modes of operation)" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Non AcknowledgeInterrupt Disable" mask="0x00002000" name="NACK"/>
|
||
|
|
<bitfield caption="Ring Indicator Input Change Disable" mask="0x00010000" name="RIIC"/>
|
||
|
|
<bitfield caption="Data Set Ready Input Change Disable" mask="0x00020000" name="DSRIC"/>
|
||
|
|
<bitfield caption="Data Carrier Detect Input Change Interrupt Disable" mask="0x00040000" name="DCDIC"/>
|
||
|
|
<bitfield caption="Clear to Send Input Change Interrupt Disable" mask="0x00080000" name="CTSIC"/>
|
||
|
|
<bitfield caption="Manchester Error Interrupt Disable" mask="0x01000000" name="MANE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Interrupt Mask Register" name="US_IMR" offset="0x0010" rw="R" size="4">
|
||
|
|
<bitfield caption="RXRDY Interrupt Mask" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="TXRDY Interrupt Mask" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Receiver Break Interrupt Mask" mask="0x00000004" name="RXBRK"/>
|
||
|
|
<bitfield caption="End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmit Interrupt Mask (available in all USART modes of operation)" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Overrun Error Interrupt Mask" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Framing Error Interrupt Mask" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Parity Error Interrupt Mask" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Time-out Interrupt Mask" mask="0x00000100" name="TIMEOUT"/>
|
||
|
|
<bitfield caption="TXEMPTY Interrupt Mask" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Max number of Repetitions Reached Interrupt Mask" mask="0x00000400" name="ITER"/>
|
||
|
|
<bitfield caption="Buffer Empty Interrupt Mask (available in all USART modes of operation)" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Buffer Full Interrupt Mask (available in all USART modes of operation)" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Non AcknowledgeInterrupt Mask" mask="0x00002000" name="NACK"/>
|
||
|
|
<bitfield caption="Ring Indicator Input Change Mask" mask="0x00010000" name="RIIC"/>
|
||
|
|
<bitfield caption="Data Set Ready Input Change Mask" mask="0x00020000" name="DSRIC"/>
|
||
|
|
<bitfield caption="Data Carrier Detect Input Change Interrupt Mask" mask="0x00040000" name="DCDIC"/>
|
||
|
|
<bitfield caption="Clear to Send Input Change Interrupt Mask" mask="0x00080000" name="CTSIC"/>
|
||
|
|
<bitfield caption="Manchester Error Interrupt Mask" mask="0x01000000" name="MANE"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Channel Status Register" name="US_CSR" offset="0x0014" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Ready" mask="0x00000001" name="RXRDY"/>
|
||
|
|
<bitfield caption="Transmitter Ready" mask="0x00000002" name="TXRDY"/>
|
||
|
|
<bitfield caption="Break Received/End of Break" mask="0x00000004" name="RXBRK"/>
|
||
|
|
<bitfield caption="End of Receiver Transfer" mask="0x00000008" name="ENDRX"/>
|
||
|
|
<bitfield caption="End of Transmitter Transfer" mask="0x00000010" name="ENDTX"/>
|
||
|
|
<bitfield caption="Overrun Error" mask="0x00000020" name="OVRE"/>
|
||
|
|
<bitfield caption="Framing Error" mask="0x00000040" name="FRAME"/>
|
||
|
|
<bitfield caption="Parity Error" mask="0x00000080" name="PARE"/>
|
||
|
|
<bitfield caption="Receiver Time-out" mask="0x00000100" name="TIMEOUT"/>
|
||
|
|
<bitfield caption="Transmitter Empty" mask="0x00000200" name="TXEMPTY"/>
|
||
|
|
<bitfield caption="Max number of Repetitions Reached" mask="0x00000400" name="ITER"/>
|
||
|
|
<bitfield caption="Transmission Buffer Empty" mask="0x00000800" name="TXBUFE"/>
|
||
|
|
<bitfield caption="Reception Buffer Full" mask="0x00001000" name="RXBUFF"/>
|
||
|
|
<bitfield caption="Non AcknowledgeInterrupt" mask="0x00002000" name="NACK"/>
|
||
|
|
<bitfield caption="Ring Indicator Input Change Flag" mask="0x00010000" name="RIIC"/>
|
||
|
|
<bitfield caption="Data Set Ready Input Change Flag" mask="0x00020000" name="DSRIC"/>
|
||
|
|
<bitfield caption="Data Carrier Detect Input Change Flag" mask="0x00040000" name="DCDIC"/>
|
||
|
|
<bitfield caption="Clear to Send Input Change Flag" mask="0x00080000" name="CTSIC"/>
|
||
|
|
<bitfield caption="Image of RI Input" mask="0x00100000" name="RI"/>
|
||
|
|
<bitfield caption="Image of DSR Input" mask="0x00200000" name="DSR"/>
|
||
|
|
<bitfield caption="Image of DCD Input" mask="0x00400000" name="DCD"/>
|
||
|
|
<bitfield caption="Image of CTS Input" mask="0x00800000" name="CTS"/>
|
||
|
|
<bitfield caption="Manchester Error" mask="0x01000000" name="MANERR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receiver Holding Register" name="US_RHR" offset="0x0018" rw="R" size="4">
|
||
|
|
<bitfield caption="Received Character" mask="0x000001FF" name="RXCHR"/>
|
||
|
|
<bitfield caption="Received Sync" mask="0x00008000" name="RXSYNH"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmitter Holding Register" name="US_THR" offset="0x001C" rw="W" size="4">
|
||
|
|
<bitfield caption="Character to be Transmitted" mask="0x000001FF" name="TXCHR"/>
|
||
|
|
<bitfield caption="Sync Field to be transmitted" mask="0x00008000" name="TXSYNH"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Baud Rate Generator Register" name="US_BRGR" offset="0x0020" rw="RW" size="4">
|
||
|
|
<bitfield caption="Clock Divider" mask="0x0000FFFF" name="CD"/>
|
||
|
|
<bitfield caption="Fractional Part" mask="0x00070000" name="FP"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receiver Time-out Register" name="US_RTOR" offset="0x0024" rw="RW" size="4">
|
||
|
|
<bitfield caption="Time-out Value" mask="0x0000FFFF" name="TO"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmitter Timeguard Register" name="US_TTGR" offset="0x0028" rw="RW" size="4">
|
||
|
|
<bitfield caption="Timeguard Value" mask="0x000000FF" name="TG"/>
|
||
|
|
</register>
|
||
|
|
<register caption="FI DI Ratio Register" name="US_FIDI" offset="0x0040" rw="RW" size="4">
|
||
|
|
<bitfield caption="FI Over DI Ratio Value" mask="0x000007FF" name="FI_DI_RATIO"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Number of Errors Register" name="US_NER" offset="0x0044" rw="R" size="4">
|
||
|
|
<bitfield caption="Number of Errors" mask="0x000000FF" name="NB_ERRORS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="IrDA Filter Register" name="US_IF" offset="0x004C" rw="RW" size="4">
|
||
|
|
<bitfield caption="IrDA Filter" mask="0x000000FF" name="IRDA_FILTER"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Manchester Encoder Decoder Register" name="US_MAN" offset="0x0050" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmitter Preamble Length" mask="0x0000000F" name="TX_PL"/>
|
||
|
|
<bitfield caption="Transmitter Preamble Pattern" mask="0x00000300" name="TX_PP" values="US_MAN__TX_PP"/>
|
||
|
|
<bitfield caption="Transmitter Manchester Polarity" mask="0x00001000" name="TX_MPOL"/>
|
||
|
|
<bitfield caption="Receiver Preamble Length" mask="0x000F0000" name="RX_PL"/>
|
||
|
|
<bitfield caption="Receiver Preamble Pattern detected" mask="0x03000000" name="RX_PP" values="US_MAN__RX_PP"/>
|
||
|
|
<bitfield caption="Receiver Manchester Polarity" mask="0x10000000" name="RX_MPOL"/>
|
||
|
|
<bitfield caption="Must Be Set to 1" mask="0x20000000" name="ONE"/>
|
||
|
|
<bitfield caption="Drift compensation" mask="0x40000000" name="DRIFT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Mode Register" name="US_WPMR" offset="0xE4" rw="RW" size="4">
|
||
|
|
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
|
||
|
|
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Write Protect Status Register" name="US_WPSR" offset="0xE8" rw="R" size="4">
|
||
|
|
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
|
||
|
|
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Version Register" name="US_VERSION" offset="0xFC" rw="R" size="4">
|
||
|
|
<bitfield caption="Harware Module Version" mask="0x00000FFF" name="VERSION"/>
|
||
|
|
<bitfield caption="Metal Fix Number" mask="0x00070000" name="MFN"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Pointer Register" name="US_RPR" offset="0x100" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Counter Register" name="US_RCR" offset="0x104" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Pointer Register" name="US_TPR" offset="0x108" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Counter Register" name="US_TCR" offset="0x10C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Pointer Register" name="US_RNPR" offset="0x110" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Receive Next Counter Register" name="US_RNCR" offset="0x114" rw="RW" size="4">
|
||
|
|
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Pointer Register" name="US_TNPR" offset="0x118" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transmit Next Counter Register" name="US_TNCR" offset="0x11C" rw="RW" size="4">
|
||
|
|
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Control Register" name="US_PTCR" offset="0x120" rw="W" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Transfer Status Register" name="US_PTSR" offset="0x124" rw="R" size="4">
|
||
|
|
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
|
||
|
|
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group caption="" name="US_MR__USART_MODE">
|
||
|
|
<value caption="Normal mode" name="NORMAL" value="0x0"/>
|
||
|
|
<value caption="RS485" name="RS485" value="0x1"/>
|
||
|
|
<value caption="Hardware Handshaking" name="HW_HANDSHAKING" value="0x2"/>
|
||
|
|
<value caption="Modem" name="MODEM" value="0x3"/>
|
||
|
|
<value caption="IS07816 Protocol: T = 0" name="IS07816_T_0" value="0x4"/>
|
||
|
|
<value caption="IS07816 Protocol: T = 1" name="IS07816_T_1" value="0x6"/>
|
||
|
|
<value caption="IrDA" name="IRDA" value="0x8"/>
|
||
|
|
<value caption="SPI Master" name="SPI_MASTER" value="0xE"/>
|
||
|
|
<value caption="SPI Slave" name="SPI_SLAVE" value="0xF"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MR__USCLKS">
|
||
|
|
<value caption="Master Clock MCK is selected" name="MCK" value="0x0"/>
|
||
|
|
<value caption="Internal Clock Divided MCK/DIV (DIV=8) is selected" name="DIV" value="0x1"/>
|
||
|
|
<value caption="Serial Clock SLK is selected" name="SCK" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MR__CHRL">
|
||
|
|
<value caption="Character length is 5 bits" name="_5_BIT" value="0x0"/>
|
||
|
|
<value caption="Character length is 6 bits" name="_6_BIT" value="0x1"/>
|
||
|
|
<value caption="Character length is 7 bits" name="_7_BIT" value="0x2"/>
|
||
|
|
<value caption="Character length is 8 bits" name="_8_BIT" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MR__PAR">
|
||
|
|
<value caption="Even parity" name="EVEN" value="0x0"/>
|
||
|
|
<value caption="Odd parity" name="ODD" value="0x1"/>
|
||
|
|
<value caption="Parity forced to 0 (Space)" name="SPACE" value="0x2"/>
|
||
|
|
<value caption="Parity forced to 1 (Mark)" name="MARK" value="0x3"/>
|
||
|
|
<value caption="No parity" name="NO" value="0x4"/>
|
||
|
|
<value caption="Multidrop mode" name="MULTIDROP" value="0x6"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MR__NBSTOP">
|
||
|
|
<value caption="1 stop bit" name="_1_BIT" value="0x0"/>
|
||
|
|
<value caption="1.5 stop bit (SYNC = 0) or reserved (SYNC = 1)" name="_1_5_BIT" value="0x1"/>
|
||
|
|
<value caption="2 stop bits" name="_2_BIT" value="0x2"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MR__CHMODE">
|
||
|
|
<value caption="Normal Mode" name="NORMAL" value="0x0"/>
|
||
|
|
<value caption="Automatic Echo. Receiver input is connected to the TXD pin." name="AUTOMATIC" value="0x1"/>
|
||
|
|
<value caption="Local Loopback. Transmitter output is connected to the Receiver Input." name="LOCAL_LOOPBACK" value="0x2"/>
|
||
|
|
<value caption="Remote Loopback. RXD pin is internally connected to the TXD pin." name="REMOTE_LOOPBACK" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MAN__TX_PP">
|
||
|
|
<value caption="The preamble is composed of '1's" name="ALL_ONE" value="0x0"/>
|
||
|
|
<value caption="The preamble is composed of '0's" name="ALL_ZERO" value="0x1"/>
|
||
|
|
<value caption="The preamble is composed of '01's" name="ZERO_ONE" value="0x2"/>
|
||
|
|
<value caption="The preamble is composed of '10's" name="ONE_ZERO" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group caption="" name="US_MAN__RX_PP">
|
||
|
|
<value caption="The preamble is composed of '1's" name="ALL_ONE" value="0x0"/>
|
||
|
|
<value caption="The preamble is composed of '0's" name="ALL_ZERO" value="0x1"/>
|
||
|
|
<value caption="The preamble is composed of '01's" name="ZERO_ONE" value="0x2"/>
|
||
|
|
<value caption="The preamble is composed of '10's" name="ONE_ZERO" value="0x3"/>
|
||
|
|
</value-group>
|
||
|
|
</module>
|
||
|
|
<module caption="Watchdog Timer" name="WDT" version="6080B">
|
||
|
|
<register-group name="WDT">
|
||
|
|
<register caption="Control Register" name="WDT_CR" offset="0x00" rw="W" size="4">
|
||
|
|
<bitfield caption="Watchdog Restart" mask="0x00000001" name="WDRSTT"/>
|
||
|
|
<bitfield caption="Password" mask="0xFF000000" name="KEY"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Mode Register" name="WDT_MR" offset="0x04" rw="RW" size="4">
|
||
|
|
<bitfield caption="Watchdog Counter Value" mask="0x00000FFF" name="WDV"/>
|
||
|
|
<bitfield caption="Watchdog Fault Interrupt Enable" mask="0x00001000" name="WDFIEN"/>
|
||
|
|
<bitfield caption="Watchdog Reset Enable" mask="0x00002000" name="WDRSTEN"/>
|
||
|
|
<bitfield caption="Watchdog Reset Processor" mask="0x00004000" name="WDRPROC"/>
|
||
|
|
<bitfield caption="Watchdog Disable" mask="0x00008000" name="WDDIS"/>
|
||
|
|
<bitfield caption="Watchdog Delta Value" mask="0x0FFF0000" name="WDD"/>
|
||
|
|
<bitfield caption="Watchdog Debug Halt" mask="0x10000000" name="WDDBGHLT"/>
|
||
|
|
<bitfield caption="Watchdog Idle Halt" mask="0x20000000" name="WDIDLEHLT"/>
|
||
|
|
</register>
|
||
|
|
<register caption="Status Register" name="WDT_SR" offset="0x08" rw="R" size="4">
|
||
|
|
<bitfield caption="Watchdog Underflow" mask="0x00000001" name="WDUNF"/>
|
||
|
|
<bitfield caption="Watchdog Error" mask="0x00000002" name="WDERR"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module name="FUSES" version="1">
|
||
|
|
<register-group caption="GPNVM Bits" name="GPNVMBITS">
|
||
|
|
<register caption="GPNVM Bits" name="GPNVMBITS" offset="0x0" rw="RW" size="1">
|
||
|
|
<bitfield caption="Security Bit" mask="0x00000001" name="SECURITY_BIT" rw="R"/>
|
||
|
|
<bitfield caption="Boot Mode Selection" mask="0x00000002" name="BOOT_MODE"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module name="LOCKBIT" version="1">
|
||
|
|
<register-group name="LOCKBIT">
|
||
|
|
<register caption="Lock Bits" name="LOCKBIT" offset="0x0" rw="RW" size="4"><bitfield caption="Lock Region 0" mask="0x00000001" name="LOCK_REGION_0"/><bitfield caption="Lock Region 1" mask="0x00000002" name="LOCK_REGION_1"/><bitfield caption="Lock Region 2" mask="0x00000004" name="LOCK_REGION_2"/><bitfield caption="Lock Region 3" mask="0x00000008" name="LOCK_REGION_3"/><bitfield caption="Lock Region 4" mask="0x00000010" name="LOCK_REGION_4"/><bitfield caption="Lock Region 5" mask="0x00000020" name="LOCK_REGION_5"/><bitfield caption="Lock Region 6" mask="0x00000040" name="LOCK_REGION_6"/><bitfield caption="Lock Region 7" mask="0x00000080" name="LOCK_REGION_7"/><bitfield caption="Lock Region 8" mask="0x00000100" name="LOCK_REGION_8"/><bitfield caption="Lock Region 9" mask="0x00000200" name="LOCK_REGION_9"/><bitfield caption="Lock Region 10" mask="0x00000400" name="LOCK_REGION_10"/><bitfield caption="Lock Region 11" mask="0x00000800" name="LOCK_REGION_11"/><bitfield caption="Lock Region 12" mask="0x00001000" name="LOCK_REGION_12"/><bitfield caption="Lock Region 13" mask="0x00002000" name="LOCK_REGION_13"/><bitfield caption="Lock Region 14" mask="0x00004000" name="LOCK_REGION_14"/><bitfield caption="Lock Region 15" mask="0x00008000" name="LOCK_REGION_15"/></register>
|
||
|
|
</register-group>
|
||
|
|
</module>
|
||
|
|
<module name="SystemControl" caption="System Control Registers">
|
||
|
|
<register-group name="SystemControl" caption="System Control Registers">
|
||
|
|
<register offset="0x00000008" size="4" name="ACTLR" initval="0" caption="Auxiliary Control Register,">
|
||
|
|
<bitfield mask="0x00000001" name="DISMCYCINT" caption="Disables interruption of multi-cycle instructions."/>
|
||
|
|
<bitfield mask="0x00000002" name="DISDEFWBUF" caption="Disables write buffer use during default memory map accesses."/>
|
||
|
|
<bitfield mask="0x00000004" name="DISFOLD" caption="Disables folding of IT instructions."/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d00" size="4" name="CPUID" initval="0x410FC240" caption="CPUID Base Register">
|
||
|
|
<bitfield mask="0x0000000f" name="REVISION" caption="Indicates patch release: 0x0 = Patch 0"/>
|
||
|
|
<bitfield mask="0x0000fff0" name="PARTNO" caption="Indicates part number"/>
|
||
|
|
<bitfield mask="0x00f00000" name="VARIANT" caption="Indicates processor revision: 0x2 = Revision 2"/>
|
||
|
|
<bitfield mask="0xff000000" name="IMPLEMENTER" caption="Implementer code"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d04" size="4" name="ICSR" initval="0" caption="Interrupt Control and State Register">
|
||
|
|
<bitfield mask="0x000001ff" name="VECTACTIVE" caption="Active exception number"/>
|
||
|
|
<bitfield mask="0x00000800" name="RETTOBASE" values="RETTOBASE" caption="no description available"/>
|
||
|
|
<bitfield mask="0x0003f000" name="VECTPENDING" caption="Exception number of the highest priority pending enabled exception"/>
|
||
|
|
<bitfield mask="0x00400000" name="ISRPENDING" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00800000" name="ISRPREEMPT" values="ISRPREEMPT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x02000000" name="PENDSTCLR" values="PENDSTCLR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x04000000" name="PENDSTSET" values="PENDSTSET" caption="no description available"/>
|
||
|
|
<bitfield mask="0x08000000" name="PENDSVCLR" values="PENDSVCLR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x10000000" name="PENDSVSET" values="PENDSVSET" caption="no description available"/>
|
||
|
|
<bitfield mask="0x80000000" name="NMIPENDSET" values="NMIPENDSET" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d08" size="4" name="VTOR" initval="0" caption="Vector Table Offset Register">
|
||
|
|
<bitfield mask="0xffffff80" name="TBLOFF" caption="Vector table base offset"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d0c" size="4" name="AIRCR" initval="0" caption="Application Interrupt and Reset Control Register">
|
||
|
|
<bitfield mask="0x00000001" name="VECTRESET" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000002" name="VECTCLRACTIVE" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000004" name="SYSRESETREQ" values="SYSRESETREQ" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000700" name="PRIGROUP" caption="Interrupt priority grouping field. This field determines the split of group priority from subpriority."/>
|
||
|
|
<bitfield mask="0x00008000" name="ENDIANNESS" values="ENDIANNESS" caption="no description available"/>
|
||
|
|
<bitfield mask="0xffff0000" name="VECTKEY" caption="Register key"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d10" size="4" name="SCR" initval="0" caption="System Control Register">
|
||
|
|
<bitfield mask="0x00000002" name="SLEEPONEXIT" values="SLEEPONEXIT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000004" name="SLEEPDEEP" values="SLEEPDEEP" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000010" name="SEVONPEND" values="SEVONPEND" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d14" size="4" name="CCR" initval="0" caption="Configuration and Control Register">
|
||
|
|
<bitfield mask="0x00000001" name="NONBASETHRDENA" values="NONBASETHRDENA" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000002" name="USERSETMPEND" values="USERSETMPEND" caption="Enables unprivileged software access to the STIR"/>
|
||
|
|
<bitfield mask="0x00000008" name="UNALIGN_TRP" values="UNALIGN_TRP" caption="Enables unaligned access traps"/>
|
||
|
|
<bitfield mask="0x00000010" name="DIV_0_TRP" values="DIV_0_TRP" caption="Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0"/>
|
||
|
|
<bitfield mask="0x00000100" name="BFHFNMIGN" values="BFHFNMIGN" caption="Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions."/>
|
||
|
|
<bitfield mask="0x00000200" name="STKALIGN" values="STKALIGN" caption="Indicates stack alignment on exception entry"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d18" size="4" name="SHPR1" initval="0" caption="System Handler Priority Register 1">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI_4" caption="Priority of system handler 4, MemManage"/>
|
||
|
|
<bitfield mask="0x0000ff00" name="PRI_5" caption="Priority of system handler 5, BusFault"/>
|
||
|
|
<bitfield mask="0x00ff0000" name="PRI_6" caption="Priority of system handler 6, UsageFault"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d1c" size="4" name="SHPR2" initval="0" caption="System Handler Priority Register 2">
|
||
|
|
<bitfield mask="0xff000000" name="PRI_11" caption="Priority of system handler 11, SVCall"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d20" size="4" name="SHPR3" initval="0" caption="System Handler Priority Register 3">
|
||
|
|
<bitfield mask="0x00ff0000" name="PRI_14" caption="Priority of system handler 14, PendSV"/>
|
||
|
|
<bitfield mask="0xff000000" name="PRI_15" caption="Priority of system handler 15, SysTick exception"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d24" size="4" name="SHCSR" initval="0" caption="System Handler Control and State Register">
|
||
|
|
<bitfield mask="0x00000001" name="MEMFAULTACT" values="MEMFAULTACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000002" name="BUSFAULTACT" values="BUSFAULTACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000008" name="USGFAULTACT" values="USGFAULTACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000080" name="SVCALLACT" values="SVCALLACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000100" name="MONITORACT" values="MONITORACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000400" name="PENDSVACT" values="PENDSVACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000800" name="SYSTICKACT" values="SYSTICKACT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00001000" name="USGFAULTPENDED" values="USGFAULTPENDED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00002000" name="MEMFAULTPENDED" values="MEMFAULTPENDED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00004000" name="BUSFAULTPENDED" values="BUSFAULTPENDED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00008000" name="SVCALLPENDED" values="SVCALLPENDED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00010000" name="MEMFAULTENA" values="MEMFAULTENA" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00020000" name="BUSFAULTENA" values="BUSFAULTENA" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00040000" name="USGFAULTENA" values="USGFAULTENA" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d28" size="4" name="CFSR" initval="0" caption="Configurable Fault Status Registers">
|
||
|
|
<bitfield mask="0x00000001" name="IACCVIOL" values="IACCVIOL" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000002" name="DACCVIOL" values="DACCVIOL" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000008" name="MUNSTKERR" values="MUNSTKERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000010" name="MSTKERR" values="MSTKERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000020" name="MLSPERR" values="MLSPERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000080" name="MMARVALID" values="MMARVALID" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000100" name="IBUSERR" values="IBUSERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000200" name="PRECISERR" values="PRECISERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000400" name="IMPRECISERR" values="IMPRECISERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000800" name="UNSTKERR" values="UNSTKERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00001000" name="STKERR" values="STKERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00002000" name="LSPERR" values="LSPERR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00008000" name="BFARVALID" values="BFARVALID" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00010000" name="UNDEFINSTR" values="UNDEFINSTR" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00020000" name="INVSTATE" values="INVSTATE" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00040000" name="INVPC" values="INVPC" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00080000" name="NOCP" values="NOCP" caption="no description available"/>
|
||
|
|
<bitfield mask="0x01000000" name="UNALIGNED" values="UNALIGNED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x02000000" name="DIVBYZERO" values="DIVBYZERO" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d2c" size="4" name="HFSR" initval="0" caption="HardFault Status register">
|
||
|
|
<bitfield mask="0x00000002" name="VECTTBL" values="VECTTBL" caption="no description available"/>
|
||
|
|
<bitfield mask="0x40000000" name="FORCED" values="FORCED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x80000000" name="DEBUGEVT" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d30" size="4" name="DFSR" initval="0" caption="Debug Fault Status Register">
|
||
|
|
<bitfield mask="0x00000001" name="HALTED" values="HALTED" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000002" name="BKPT" values="BKPT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000004" name="DWTTRAP" values="DWTTRAP" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000008" name="VCATCH" values="VCATCH" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000010" name="EXTERNAL" values="EXTERNAL" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d34" size="4" name="MMFAR" initval="0" caption="MemManage Address Register">
|
||
|
|
<bitfield mask="0xffffffff" name="ADDRESS" caption="Address of MemManage fault location"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d38" size="4" name="BFAR" initval="0" caption="BusFault Address Register">
|
||
|
|
<bitfield mask="0xffffffff" name="ADDRESS" caption="Address of the BusFault location"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000d3c" size="4" name="AFSR" initval="0" caption="Auxiliary Fault Status Register">
|
||
|
|
<bitfield mask="0xffffffff" name="AUXFAULT" caption="Latched version of the AUXFAULT inputs"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group name="RETTOBASE">
|
||
|
|
<value value="0" name="VALUE_0" caption="there are preempted active exceptions to execute"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="there are no active exceptions, or the currently-executing exception is the only active exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="ISRPREEMPT">
|
||
|
|
<value value="0" name="VALUE_0" caption="Will not service"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="Will service a pending exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="PENDSTCLR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no effect"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="removes the pending state from the SysTick exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="PENDSTSET">
|
||
|
|
<value value="0" name="VALUE_0" caption="write: no effect; read: SysTick exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="write: changes SysTick exception state to pending; read: SysTick exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="PENDSVCLR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no effect"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="removes the pending state from the PendSV exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="PENDSVSET">
|
||
|
|
<value value="0" name="VALUE_0" caption="write: no effect; read: PendSV exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="write: changes PendSV exception state to pending; read: PendSV exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="NMIPENDSET">
|
||
|
|
<value value="0" name="VALUE_0" caption="write: no effect; read: NMI exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="write: changes NMI exception state to pending; read: NMI exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SYSRESETREQ">
|
||
|
|
<value value="0" name="VALUE_0" caption="no system reset request"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="asserts a signal to the outer system that requests a reset"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="ENDIANNESS">
|
||
|
|
<value value="0" name="VALUE_0" caption="Little-endian"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="Big-endian"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SLEEPONEXIT">
|
||
|
|
<value value="0" name="VALUE_0" caption="o not sleep when returning to Thread mode"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="enter sleep, or deep sleep, on return from an ISR"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SLEEPDEEP">
|
||
|
|
<value value="0" name="VALUE_0" caption="sleep"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="deep sleep"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SEVONPEND">
|
||
|
|
<value value="0" name="VALUE_0" caption="only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="enabled events and all interrupts, including disabled interrupts, can wakeup the processor"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="NONBASETHRDENA">
|
||
|
|
<value value="0" name="VALUE_0" caption="processor can enter Thread mode only when no exception is active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="processor can enter Thread mode from any level under the control of an EXC_RETURN value"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="USERSETMPEND">
|
||
|
|
<value value="0" name="VALUE_0" caption="disable"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="enable"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="UNALIGN_TRP">
|
||
|
|
<value value="0" name="VALUE_0" caption="do not trap unaligned halfword and word accesses"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="trap unaligned halfword and word accesses"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="DIV_0_TRP">
|
||
|
|
<value value="0" name="VALUE_0" caption="do not trap divide by 0"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="trap divide by 0"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="BFHFNMIGN">
|
||
|
|
<value value="0" name="VALUE_0" caption="data bus faults caused by load and store instructions cause a lock-up"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="STKALIGN">
|
||
|
|
<value value="0" name="VALUE_0" caption="4-byte aligned"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="8-byte aligned"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MEMFAULTACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="BUSFAULTACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="USGFAULTACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SVCALLACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MONITORACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="PENDSVACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SYSTICKACT">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not active"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="USGFAULTPENDED">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MEMFAULTPENDED">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="BUSFAULTPENDED">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SVCALLPENDED">
|
||
|
|
<value value="0" name="VALUE_0" caption="exception is not pending"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="exception is pending"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MEMFAULTENA">
|
||
|
|
<value value="0" name="VALUE_0" caption="disable the exception"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="enable the exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="BUSFAULTENA">
|
||
|
|
<value value="0" name="VALUE_0" caption="disable the exception"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="enable the exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="USGFAULTENA">
|
||
|
|
<value value="0" name="VALUE_0" caption="disable the exception"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="enable the exception"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="IACCVIOL">
|
||
|
|
<value value="0" name="VALUE_0" caption="no instruction access violation fault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor attempted an instruction fetch from a location that does not permit execution"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="DACCVIOL">
|
||
|
|
<value value="0" name="VALUE_0" caption="no data access violation fault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor attempted a load or store at a location that does not permit the operation"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MUNSTKERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no unstacking fault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="unstack for an exception return has caused one or more access violations"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MSTKERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no stacking fault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="stacking for an exception entry has caused one or more access violations"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MLSPERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="No MemManage fault occurred during floating-point lazy state preservation"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="A MemManage fault occurred during floating-point lazy state preservation"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="MMARVALID">
|
||
|
|
<value value="0" name="VALUE_0" caption="value in MMAR is not a valid fault address"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="MMAR holds a valid fault address"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="IBUSERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no instruction bus error"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="instruction bus error"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="PRECISERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no precise data bus error"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="IMPRECISERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no imprecise data bus error"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="UNSTKERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no unstacking fault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="unstack for an exception return has caused one or more BusFaults"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="STKERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no stacking fault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="stacking for an exception entry has caused one or more BusFaults"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="LSPERR">
|
||
|
|
<value value="0" name="VALUE_0" caption="No bus fault occurred during floating-point lazy state preservation"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="A bus fault occurred during floating-point lazy state preservation"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="BFARVALID">
|
||
|
|
<value value="0" name="VALUE_0" caption="value in BFAR is not a valid fault address"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="BFAR holds a valid fault address"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="UNDEFINSTR">
|
||
|
|
<value value="0" name="VALUE_0" caption="no undefined instruction UsageFault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor has attempted to execute an undefined instruction"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="INVSTATE">
|
||
|
|
<value value="0" name="VALUE_0" caption="no invalid state UsageFault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor has attempted to execute an instruction that makes illegal use of the EPSR"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="INVPC">
|
||
|
|
<value value="0" name="VALUE_0" caption="no invalid PC load UsageFault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor has attempted an illegal load of EXC_RETURN to the PC"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="NOCP">
|
||
|
|
<value value="0" name="VALUE_0" caption="no UsageFault caused by attempting to access a coprocessor"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor has attempted to access a coprocessor"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="UNALIGNED">
|
||
|
|
<value value="0" name="VALUE_0" caption="no unaligned access fault, or unaligned access trapping not enabled"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor has made an unaligned memory access"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="DIVBYZERO">
|
||
|
|
<value value="0" name="VALUE_0" caption="no divide by zero fault, or divide by zero trapping not enabled"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="the processor has executed an SDIV or UDIV instruction with a divisor of 0"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="VECTTBL">
|
||
|
|
<value value="0" name="VALUE_0" caption="no BusFault on vector table read"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="BusFault on vector table read"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="FORCED">
|
||
|
|
<value value="0" name="VALUE_0" caption="no forced HardFault"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="forced HardFault"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="HALTED">
|
||
|
|
<value value="0" name="VALUE_0" caption="No active halt request debug event"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="Halt request debug event active"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="BKPT">
|
||
|
|
<value value="0" name="VALUE_0" caption="No current breakpoint debug event"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="At least one current breakpoint debug event"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="DWTTRAP">
|
||
|
|
<value value="0" name="VALUE_0" caption="No current debug events generated by the DWT"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="At least one current debug event generated by the DWT"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="VCATCH">
|
||
|
|
<value value="0" name="VALUE_0" caption="No Vector catch triggered"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="Vector catch triggered"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="EXTERNAL">
|
||
|
|
<value value="0" name="VALUE_0" caption="No EDBGRQ debug event"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="EDBGRQ debug event"/>
|
||
|
|
</value-group>
|
||
|
|
</module><module name="SysTick" caption="System timer">
|
||
|
|
<register-group name="SysTick" caption="System timer">
|
||
|
|
<register offset="0x00000000" size="4" name="CSR" initval="0x4" caption="SysTick Control and Status Register">
|
||
|
|
<bitfield mask="0x00000001" name="ENABLE" values="ENABLE" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000002" name="TICKINT" values="TICKINT" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00000004" name="CLKSOURCE" values="CLKSOURCE" caption="no description available"/>
|
||
|
|
<bitfield mask="0x00010000" name="COUNTFLAG" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000004" size="4" name="RVR" initval="0" caption="SysTick Reload Value Register">
|
||
|
|
<bitfield mask="0x00ffffff" name="RELOAD" caption="Value to load into the SysTick Current Value Register when the counter reaches 0"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000008" size="4" name="CVR" initval="0" caption="SysTick Current Value Register">
|
||
|
|
<bitfield mask="0x00ffffff" name="CURRENT" caption="Current value at the time the register is accessed"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000000c" size="4" name="CALIB" initval="0" caption="SysTick Calibration Value Register">
|
||
|
|
<bitfield mask="0x00ffffff" name="TENMS" caption="Reload value to use for 10ms timing"/>
|
||
|
|
<bitfield mask="0x40000000" name="SKEW" values="SKEW" caption="no description available"/>
|
||
|
|
<bitfield mask="0x80000000" name="NOREF" values="NOREF" caption="no description available"/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
<value-group name="ENABLE">
|
||
|
|
<value value="0" name="VALUE_0" caption="counter disabled"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="counter enabled"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="TICKINT">
|
||
|
|
<value value="0" name="VALUE_0" caption="counting down to 0 does not assert the SysTick exception request"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="counting down to 0 asserts the SysTick exception request"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="CLKSOURCE">
|
||
|
|
<value value="0" name="VALUE_0" caption="external clock"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="processor clock"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="SKEW">
|
||
|
|
<value value="0" name="VALUE_0" caption="10ms calibration value is exact"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="10ms calibration value is inexact, because of the clock frequency"/>
|
||
|
|
</value-group>
|
||
|
|
<value-group name="NOREF">
|
||
|
|
<value value="0" name="VALUE_0" caption="The reference clock is provided"/>
|
||
|
|
<value value="1" name="VALUE_1" caption="The reference clock is not provided"/>
|
||
|
|
</value-group>
|
||
|
|
</module><module name="NVIC" caption="Nested Vectored Interrupt Controller">
|
||
|
|
<register-group name="NVIC" caption="Nested Vectored Interrupt Controller">
|
||
|
|
<register offset="0x00000000" size="4" name="NVICISER0" initval="0" caption="Interrupt Set Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000004" size="4" name="NVICISER1" initval="0" caption="Interrupt Set Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000008" size="4" name="NVICISER2" initval="0" caption="Interrupt Set Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000000c" size="4" name="NVICISER3" initval="0" caption="Interrupt Set Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETENA" caption="Interrupt set enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000080" size="4" name="NVICICER0" initval="0" caption="Interrupt Clear Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000084" size="4" name="NVICICER1" initval="0" caption="Interrupt Clear Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000088" size="4" name="NVICICER2" initval="0" caption="Interrupt Clear Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000008c" size="4" name="NVICICER3" initval="0" caption="Interrupt Clear Enable Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRENA" caption="Interrupt clear-enable bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000100" size="4" name="NVICISPR0" initval="0" caption="Interrupt Set Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000104" size="4" name="NVICISPR1" initval="0" caption="Interrupt Set Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000108" size="4" name="NVICISPR2" initval="0" caption="Interrupt Set Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000010c" size="4" name="NVICISPR3" initval="0" caption="Interrupt Set Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="SETPEND" caption="Interrupt set-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000180" size="4" name="NVICICPR0" initval="0" caption="Interrupt Clear Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000184" size="4" name="NVICICPR1" initval="0" caption="Interrupt Clear Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000188" size="4" name="NVICICPR2" initval="0" caption="Interrupt Clear Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000018c" size="4" name="NVICICPR3" initval="0" caption="Interrupt Clear Pending Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="CLRPEND" caption="Interrupt clear-pending bits"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000200" size="4" name="NVICIABR0" initval="0" caption="Interrupt Active bit Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000204" size="4" name="NVICIABR1" initval="0" caption="Interrupt Active bit Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000208" size="4" name="NVICIABR2" initval="0" caption="Interrupt Active bit Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000020c" size="4" name="NVICIABR3" initval="0" caption="Interrupt Active bit Register n">
|
||
|
|
<bitfield mask="0xffffffff" name="ACTIVE" caption="Interrupt active flags"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000300" size="1" name="NVICIP0" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI0" caption="Priority of interrupt 0"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000301" size="1" name="NVICIP1" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI1" caption="Priority of interrupt 1"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000302" size="1" name="NVICIP2" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI2" caption="Priority of interrupt 2"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000303" size="1" name="NVICIP3" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI3" caption="Priority of interrupt 3"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000304" size="1" name="NVICIP4" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI4" caption="Priority of interrupt 4"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000305" size="1" name="NVICIP5" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI5" caption="Priority of interrupt 5"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000306" size="1" name="NVICIP6" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI6" caption="Priority of interrupt 6"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000307" size="1" name="NVICIP7" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI7" caption="Priority of interrupt 7"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000308" size="1" name="NVICIP8" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI8" caption="Priority of interrupt 8"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000309" size="1" name="NVICIP9" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI9" caption="Priority of interrupt 9"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000030a" size="1" name="NVICIP10" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI10" caption="Priority of interrupt 10"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000030b" size="1" name="NVICIP11" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI11" caption="Priority of interrupt 11"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000030c" size="1" name="NVICIP12" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI12" caption="Priority of interrupt 12"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000030d" size="1" name="NVICIP13" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI13" caption="Priority of interrupt 13"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000030e" size="1" name="NVICIP14" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI14" caption="Priority of interrupt 14"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000030f" size="1" name="NVICIP15" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI15" caption="Priority of interrupt 15"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000310" size="1" name="NVICIP16" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI16" caption="Priority of interrupt 16"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000311" size="1" name="NVICIP17" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI17" caption="Priority of interrupt 17"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000312" size="1" name="NVICIP18" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI18" caption="Priority of interrupt 18"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000313" size="1" name="NVICIP19" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI19" caption="Priority of interrupt 19"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000314" size="1" name="NVICIP20" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI20" caption="Priority of interrupt 20"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000315" size="1" name="NVICIP21" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI21" caption="Priority of interrupt 21"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000316" size="1" name="NVICIP22" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI22" caption="Priority of interrupt 22"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000317" size="1" name="NVICIP23" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI23" caption="Priority of interrupt 23"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000318" size="1" name="NVICIP24" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI24" caption="Priority of interrupt 24"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000319" size="1" name="NVICIP25" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI25" caption="Priority of interrupt 25"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000031a" size="1" name="NVICIP26" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI26" caption="Priority of interrupt 26"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000031b" size="1" name="NVICIP27" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI27" caption="Priority of interrupt 27"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000031c" size="1" name="NVICIP28" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI28" caption="Priority of interrupt 28"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000031d" size="1" name="NVICIP29" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI29" caption="Priority of interrupt 29"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000031e" size="1" name="NVICIP30" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI30" caption="Priority of interrupt 30"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000031f" size="1" name="NVICIP31" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI31" caption="Priority of interrupt 31"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000320" size="1" name="NVICIP32" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI32" caption="Priority of interrupt 32"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000321" size="1" name="NVICIP33" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI33" caption="Priority of interrupt 33"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000322" size="1" name="NVICIP34" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI34" caption="Priority of interrupt 34"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000323" size="1" name="NVICIP35" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI35" caption="Priority of interrupt 35"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000324" size="1" name="NVICIP36" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI36" caption="Priority of interrupt 36"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000325" size="1" name="NVICIP37" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI37" caption="Priority of interrupt 37"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000326" size="1" name="NVICIP38" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI38" caption="Priority of interrupt 38"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000327" size="1" name="NVICIP39" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI39" caption="Priority of interrupt 39"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000328" size="1" name="NVICIP40" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI40" caption="Priority of interrupt 40"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000329" size="1" name="NVICIP41" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI41" caption="Priority of interrupt 41"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000032a" size="1" name="NVICIP42" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI42" caption="Priority of interrupt 42"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000032b" size="1" name="NVICIP43" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI43" caption="Priority of interrupt 43"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000032c" size="1" name="NVICIP44" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI44" caption="Priority of interrupt 44"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000032d" size="1" name="NVICIP45" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI45" caption="Priority of interrupt 45"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000032e" size="1" name="NVICIP46" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI46" caption="Priority of interrupt 46"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000032f" size="1" name="NVICIP47" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI47" caption="Priority of interrupt 47"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000330" size="1" name="NVICIP48" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI48" caption="Priority of interrupt 48"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000331" size="1" name="NVICIP49" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI49" caption="Priority of interrupt 49"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000332" size="1" name="NVICIP50" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI50" caption="Priority of interrupt 50"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000333" size="1" name="NVICIP51" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI51" caption="Priority of interrupt 51"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000334" size="1" name="NVICIP52" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI52" caption="Priority of interrupt 52"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000335" size="1" name="NVICIP53" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI53" caption="Priority of interrupt 53"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000336" size="1" name="NVICIP54" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI54" caption="Priority of interrupt 54"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000337" size="1" name="NVICIP55" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI55" caption="Priority of interrupt 55"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000338" size="1" name="NVICIP56" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI56" caption="Priority of interrupt 56"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000339" size="1" name="NVICIP57" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI57" caption="Priority of interrupt 57"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000033a" size="1" name="NVICIP58" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI58" caption="Priority of interrupt 58"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000033b" size="1" name="NVICIP59" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI59" caption="Priority of interrupt 59"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000033c" size="1" name="NVICIP60" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI60" caption="Priority of interrupt 60"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000033d" size="1" name="NVICIP61" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI61" caption="Priority of interrupt 61"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000033e" size="1" name="NVICIP62" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI62" caption="Priority of interrupt 62"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000033f" size="1" name="NVICIP63" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI63" caption="Priority of interrupt 63"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000340" size="1" name="NVICIP64" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI64" caption="Priority of interrupt 64"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000341" size="1" name="NVICIP65" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI65" caption="Priority of interrupt 65"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000342" size="1" name="NVICIP66" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI66" caption="Priority of interrupt 66"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000343" size="1" name="NVICIP67" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI67" caption="Priority of interrupt 67"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000344" size="1" name="NVICIP68" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI68" caption="Priority of interrupt 68"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000345" size="1" name="NVICIP69" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI69" caption="Priority of interrupt 69"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000346" size="1" name="NVICIP70" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI70" caption="Priority of interrupt 70"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000347" size="1" name="NVICIP71" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI71" caption="Priority of interrupt 71"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000348" size="1" name="NVICIP72" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI72" caption="Priority of interrupt 72"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000349" size="1" name="NVICIP73" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI73" caption="Priority of interrupt 73"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000034a" size="1" name="NVICIP74" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI74" caption="Priority of interrupt 74"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000034b" size="1" name="NVICIP75" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI75" caption="Priority of interrupt 75"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000034c" size="1" name="NVICIP76" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI76" caption="Priority of interrupt 76"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000034d" size="1" name="NVICIP77" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI77" caption="Priority of interrupt 77"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000034e" size="1" name="NVICIP78" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI78" caption="Priority of interrupt 78"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000034f" size="1" name="NVICIP79" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI79" caption="Priority of interrupt 79"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000350" size="1" name="NVICIP80" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI80" caption="Priority of interrupt 80"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000351" size="1" name="NVICIP81" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI81" caption="Priority of interrupt 81"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000352" size="1" name="NVICIP82" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI82" caption="Priority of interrupt 82"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000353" size="1" name="NVICIP83" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI83" caption="Priority of interrupt 83"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000354" size="1" name="NVICIP84" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI84" caption="Priority of interrupt 84"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000355" size="1" name="NVICIP85" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI85" caption="Priority of interrupt 85"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000356" size="1" name="NVICIP86" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI86" caption="Priority of interrupt 86"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000357" size="1" name="NVICIP87" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI87" caption="Priority of interrupt 87"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000358" size="1" name="NVICIP88" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI88" caption="Priority of interrupt 88"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000359" size="1" name="NVICIP89" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI89" caption="Priority of interrupt 89"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000035a" size="1" name="NVICIP90" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI90" caption="Priority of interrupt 90"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000035b" size="1" name="NVICIP91" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI91" caption="Priority of interrupt 91"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000035c" size="1" name="NVICIP92" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI92" caption="Priority of interrupt 92"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000035d" size="1" name="NVICIP93" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI93" caption="Priority of interrupt 93"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000035e" size="1" name="NVICIP94" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI94" caption="Priority of interrupt 94"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x0000035f" size="1" name="NVICIP95" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI95" caption="Priority of interrupt 95"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000360" size="1" name="NVICIP96" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI96" caption="Priority of interrupt 96"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000361" size="1" name="NVICIP97" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI97" caption="Priority of interrupt 97"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000362" size="1" name="NVICIP98" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI98" caption="Priority of interrupt 98"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000363" size="1" name="NVICIP99" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI99" caption="Priority of interrupt 99"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000364" size="1" name="NVICIP100" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI100" caption="Priority of interrupt 100"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000365" size="1" name="NVICIP101" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI101" caption="Priority of interrupt 101"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000366" size="1" name="NVICIP102" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI102" caption="Priority of interrupt 102"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000367" size="1" name="NVICIP103" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI103" caption="Priority of interrupt 103"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000368" size="1" name="NVICIP104" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI104" caption="Priority of interrupt 104"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000369" size="1" name="NVICIP105" initval="0" caption="Interrupt Priority Register n">
|
||
|
|
<bitfield mask="0x000000ff" name="PRI105" caption="Priority of interrupt 105"/>
|
||
|
|
</register>
|
||
|
|
<register offset="0x00000e00" size="4" name="NVICSTIR" initval="0" caption="Software Trigger Interrupt Register">
|
||
|
|
<bitfield mask="0x000001ff" name="INTID" caption="Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3."/>
|
||
|
|
</register>
|
||
|
|
</register-group>
|
||
|
|
</module></modules>
|
||
|
|
</avr-tools-device-file>
|