69 lines
5.9 KiB
C
69 lines
5.9 KiB
C
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3SD8_CRCCU_INSTANCE_
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#define _SAM3SD8_CRCCU_INSTANCE_
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/* ========== Register definition for CRCCU peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
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#define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
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#define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
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#define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
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#define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
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#define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
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#define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
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#define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
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#define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
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#define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
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#define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
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#define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
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#define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
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#define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
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#define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
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#else
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#define REG_CRCCU_DSCR (*(__IO uint32_t*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
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#define REG_CRCCU_DMA_EN (*(__O uint32_t*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
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#define REG_CRCCU_DMA_DIS (*(__O uint32_t*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
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#define REG_CRCCU_DMA_SR (*(__I uint32_t*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
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#define REG_CRCCU_DMA_IER (*(__O uint32_t*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
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#define REG_CRCCU_DMA_IDR (*(__O uint32_t*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
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#define REG_CRCCU_DMA_IMR (*(__I uint32_t*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
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#define REG_CRCCU_DMA_ISR (*(__I uint32_t*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
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#define REG_CRCCU_CR (*(__O uint32_t*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
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#define REG_CRCCU_MR (*(__IO uint32_t*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
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#define REG_CRCCU_SR (*(__I uint32_t*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
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#define REG_CRCCU_IER (*(__O uint32_t*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
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#define REG_CRCCU_IDR (*(__O uint32_t*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
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#define REG_CRCCU_IMR (*(__I uint32_t*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
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#define REG_CRCCU_ISR (*(__I uint32_t*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3SD8_CRCCU_INSTANCE_ */
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