97 lines
8.5 KiB
C
97 lines
8.5 KiB
C
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3S_HSMCI_INSTANCE_
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#define _SAM3S_HSMCI_INSTANCE_
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/* ========== Register definition for HSMCI peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */
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#define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */
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#define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
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#define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
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#define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */
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#define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */
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#define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */
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#define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
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#define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */
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#define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */
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#define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
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#define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */
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#define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
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#define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
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#define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
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#define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */
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#define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
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#define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
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#define REG_HSMCI_RPR (0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
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#define REG_HSMCI_RCR (0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
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#define REG_HSMCI_TPR (0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
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#define REG_HSMCI_TCR (0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
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#define REG_HSMCI_RNPR (0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
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#define REG_HSMCI_RNCR (0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
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#define REG_HSMCI_TNPR (0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
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#define REG_HSMCI_TNCR (0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
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#define REG_HSMCI_PTCR (0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
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#define REG_HSMCI_PTSR (0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
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#define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
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#else
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#define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */
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#define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */
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#define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */
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#define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
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#define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */
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#define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */
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#define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */
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#define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
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#define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */
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#define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */
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#define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */
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#define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */
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#define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */
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#define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */
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#define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */
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#define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */
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#define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */
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#define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */
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#define REG_HSMCI_RPR (*(__IO uint32_t*)0x40000100U) /**< \brief (HSMCI) Receive Pointer Register */
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#define REG_HSMCI_RCR (*(__IO uint32_t*)0x40000104U) /**< \brief (HSMCI) Receive Counter Register */
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#define REG_HSMCI_TPR (*(__IO uint32_t*)0x40000108U) /**< \brief (HSMCI) Transmit Pointer Register */
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#define REG_HSMCI_TCR (*(__IO uint32_t*)0x4000010CU) /**< \brief (HSMCI) Transmit Counter Register */
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#define REG_HSMCI_RNPR (*(__IO uint32_t*)0x40000110U) /**< \brief (HSMCI) Receive Next Pointer Register */
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#define REG_HSMCI_RNCR (*(__IO uint32_t*)0x40000114U) /**< \brief (HSMCI) Receive Next Counter Register */
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#define REG_HSMCI_TNPR (*(__IO uint32_t*)0x40000118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
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#define REG_HSMCI_TNCR (*(__IO uint32_t*)0x4000011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
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#define REG_HSMCI_PTCR (*(__O uint32_t*)0x40000120U) /**< \brief (HSMCI) Transfer Control Register */
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#define REG_HSMCI_PTSR (*(__I uint32_t*)0x40000124U) /**< \brief (HSMCI) Transfer Status Register */
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#define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3S_HSMCI_INSTANCE_ */
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