mes/module/mescc
W. J. van der Laan d0b1be6a5d mescc: RISC-V64 code generation.
* mes/module/mescc/mescc.mes: Import riscv64 code generation modules.
* mes/module/mescc/riscv64/as.mes: Imports for as.mes.
* mes/module/mescc/riscv64/info.mes: Imports for info.mes.
* module/mescc/mescc.scm (replace-suffix, arch-get, arch-get-info,
arch-get-machine, arch-get-m1-macros, .E?, .s?, .o?): Handle riscv64 and
some stubs for riscv32.
(arch-get-defines): Add defines for riscv32 and riscv64.
* module/mescc/riscv64/as.scm: New file: Code generator module for RISC-V64.
* module/mescc/riscv64/info.scm: New file: Architecture info for RISC-V64.
* build-aux/build-guile.sh (SCM_FILES): Add them.
2023-11-05 09:40:37 +01:00
..
armv4 mescc: Add r0-cmp-r1 instruction. 2023-11-05 09:39:29 +01:00
i386 mescc: Add r0-cmp-r1 instruction. 2023-11-05 09:39:29 +01:00
riscv64 mescc: RISC-V64 code generation. 2023-11-05 09:40:37 +01:00
x86_64 mescc: Add r0-cmp-r1 instruction. 2023-11-05 09:39:29 +01:00
as.scm mescc: x86_64 support: Refactor to abstracted assembly, add x86_64. 2018-08-15 18:26:55 +02:00
bytevectors.scm mescc: x86_64 support: Refactor to abstracted assembly, add x86_64. 2018-08-15 18:26:55 +02:00
compile.scm mescc: Add r0-cmp-r1 instruction. 2023-11-05 09:39:29 +01:00
info.scm mescc: Do not dump variables with extern storage. 2019-07-27 17:22:00 +02:00
M1.scm mescc: Fix hex2:immediate8 to work with mes/m2-compiled mes. 2023-11-05 09:36:26 +01:00
mescc.scm mescc: RISC-V64 code generation. 2023-11-05 09:40:37 +01:00
preprocess.scm mescc: Remove duplicate include. 2023-08-27 10:05:33 +02:00