16f4fc3263
* module/mescc/M1.scm (riscv:i-format, riscv:j-format, riscv:u-format): New procedures for RISC-V instruction formats. (info->M1): Use them to switch from !0xAB to M1 weird strings 'AB'. * module/mescc/riscv64/as.scm, lib/linux/riscv64-mes-m2/_exit.c ib/linux/riscv64-mes-m2/_write.c,. lib/linux/riscv64-mes-m2/crt1.M1,. lib/linux/riscv64-mes-m2/syscall.c,. lib/linux/riscv64-mes-mescc/_exit.c,. lib/linux/riscv64-mes-mescc/_write.c,. lib/linux/riscv64-mes-mescc/crt1.c,. lib/linux/riscv64-mes-mescc/syscall-internal.c,. lib/linux/riscv64-mes-mescc/syscall.c,. lib/m2/riscv64/riscv64_defs.M1,. lib/riscv64-mes-mescc/setjmp.c,. lib/riscv64-mes/riscv64.M1: Switch to riscv64 word-based macros. * lib/linux/open.c (open)[!SYS_open]: Add support using openat syscall. * include/linux/riscv64/syscall.h (MAKESTRING, MAKESTRING2, RISCV_SYSCALL): New macros.
241 lines
5.8 KiB
Plaintext
241 lines
5.8 KiB
Plaintext
## Copyright (C) 2021 Andrius Štikonas
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## This file is part of M2-Planet.
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##
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## M2-Planet is free software: you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation, either version 3 of the License, or
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## (at your option) any later version.
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##
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## M2-Planet is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with M2-Planet. If not, see <http://www.gnu.org/licenses/>.
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DEFINE NULL 0000000000000000
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;; Opcodes
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;; RV32I Base Instruction Set
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DEFINE lui 37000000
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DEFINE auipc 17000000
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DEFINE jal 6F000000
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DEFINE jalr 67000000
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DEFINE beq 63000000
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DEFINE bne 63100000
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DEFINE blt 63400000
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DEFINE bge 63500000
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DEFINE bltu 63600000
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DEFINE bgeu 63700000
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DEFINE lb 03000000
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DEFINE lh 03100000
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DEFINE lw 03200000
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DEFINE lbu 03400000
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DEFINE lhu 03500000
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DEFINE sb 23000000
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DEFINE sh 23100000
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DEFINE sw 23200000
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DEFINE addi 13000000
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DEFINE slti 13200000
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DEFINE sltiu 13300000
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DEFINE xori 13400000
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DEFINE ori 13600000
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DEFINE andi 13700000
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DEFINE slli 13100000
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DEFINE srli 13500000
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DEFINE srai 13500040
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DEFINE add 33000000
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DEFINE sub 33000040
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DEFINE sll 33100000
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DEFINE slt 33200000
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DEFINE sltu 33300000
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DEFINE xor 33400000
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DEFINE srl 33500000
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DEFINE sra 33500040
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DEFINE or 33600000
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DEFINE and 33700000
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DEFINE ecall 73000000
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DEFINE ebreak 73001000
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;; RV64I Base Instruction set
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DEFINE lwu 03600000
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DEFINE ld 03300000
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DEFINE sd 23300000
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DEFINE addiw 1B000000
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DEFINE slliw 1B100000
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DEFINE srliw 1B500000
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DEFINE sraiw 1B500040
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DEFINE addw 3B000000
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DEFINE subw 3B000040
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DEFINE sllw 3B100000
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DEFINE srlw 3B500000
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DEFINE sraw 3B500040
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;; RV32M Standard Extensions
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DEFINE mul 33000002
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DEFINE mulh 33100002
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DEFINE mulhsu 33200002
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DEFINE mulhu 33300002
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DEFINE div 33400002
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DEFINE divu 33500002
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DEFINE rem 33600002
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DEFINE remu 33700002
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;; RV64M Standard Extensions
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DEFINE mulw 3B000002
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DEFINE divw 3B400002
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DEFINE divuw 3B500002
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DEFINE remw 3B600002
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DEFINE remuw 3B700002
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;; Pseudoinstructions
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DEFINE nop 13000000 # addi
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DEFINE mv 13000000 # addi
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DEFINE not 1340F0FF # xori, RD, RS, -1
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DEFINE beqz 63000000 # beq
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DEFINE bnez 63100000 # bne
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DEFINE bltz 63400000 # blt
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DEFINE ret 67800000 # rs1_ra jalr
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;; Destination registers
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;; register_number << 7
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DEFINE rd_ra .80000000
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DEFINE rd_sp .00010000
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DEFINE rd_gp .80010000
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DEFINE rd_tp .00020000
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DEFINE rd_t0 .80020000
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DEFINE rd_t1 .00030000
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DEFINE rd_t2 .80030000
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DEFINE rd_s0 .00040000
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DEFINE rd_fp .00040000
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DEFINE rd_s1 .80040000
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DEFINE rd_a0 .00050000
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DEFINE rd_a1 .80050000
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DEFINE rd_a2 .00060000
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DEFINE rd_a3 .80060000
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DEFINE rd_a4 .00070000
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DEFINE rd_a5 .80070000
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DEFINE rd_a6 .00080000
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DEFINE rd_a7 .80080000
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DEFINE rd_s2 .00090000
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DEFINE rd_s3 .80090000
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DEFINE rd_s4 .000A0000
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DEFINE rd_s5 .800A0000
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DEFINE rd_s6 .000B0000
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DEFINE rd_s7 .800B0000
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DEFINE rd_s8 .000C0000
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DEFINE rd_s9 .800C0000
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DEFINE rd_s10 .000D0000
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DEFINE rd_s11 .800D0000
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DEFINE rd_t3 .000E0000
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DEFINE rd_t4 .800E0000
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DEFINE rd_t5 .000F0000
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DEFINE rd_t6 .800F0000
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;; First source registers
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;; register_number << 15
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DEFINE rs1_ra .00800000
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DEFINE rs1_sp .00000100
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DEFINE rs1_gp .00800100
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DEFINE rs1_tp .00000200
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DEFINE rs1_t0 .00800200
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DEFINE rs1_t1 .00000300
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DEFINE rs1_t2 .00800300
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DEFINE rs1_s0 .00000400
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DEFINE rs1_fp .00000400
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DEFINE rs1_s1 .00800400
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DEFINE rs1_a0 .00000500
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DEFINE rs1_a1 .00800500
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DEFINE rs1_a2 .00000600
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DEFINE rs1_a3 .00800600
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DEFINE rs1_a4 .00000700
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DEFINE rs1_a5 .00800700
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DEFINE rs1_a6 .00000800
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DEFINE rs1_a7 .00800800
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DEFINE rs1_s2 .00000900
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DEFINE rs1_s3 .00800900
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DEFINE rs1_s4 .00000A00
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DEFINE rs1_s5 .00800A00
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DEFINE rs1_s6 .00000B00
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DEFINE rs1_s7 .00800B00
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DEFINE rs1_s8 .00000C00
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DEFINE rs1_s9 .00800C00
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DEFINE rs1_s10 .00000D00
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DEFINE rs1_s11 .00800D00
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DEFINE rs1_t3 .00000E00
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DEFINE rs1_t4 .00800E00
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DEFINE rs1_t5 .00000F00
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DEFINE rs1_t6 .00800F00
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;; Second source registers
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;; register_number << 20
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DEFINE rs2_ra .00001000
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DEFINE rs2_sp .00002000
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DEFINE rs2_gp .00003000
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DEFINE rs2_tp .00004000
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DEFINE rs2_t0 .00005000
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DEFINE rs2_t1 .00006000
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DEFINE rs2_t2 .00007000
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DEFINE rs2_s0 .00008000
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DEFINE rs2_fp .00008000
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DEFINE rs2_s1 .00009000
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DEFINE rs2_a0 .0000A000
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DEFINE rs2_a1 .0000B000
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DEFINE rs2_a2 .0000C000
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DEFINE rs2_a3 .0000D000
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DEFINE rs2_a4 .0000E000
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DEFINE rs2_a5 .0000F000
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DEFINE rs2_a6 .00000001
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DEFINE rs2_a7 .00001001
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DEFINE rs2_s2 .00002001
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DEFINE rs2_s3 .00003001
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DEFINE rs2_s4 .00004001
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DEFINE rs2_s5 .00005001
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DEFINE rs2_s6 .00006001
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DEFINE rs2_s7 .00007001
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DEFINE rs2_s8 .00008001
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DEFINE rs2_s9 .00009001
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DEFINE rs2_s10 .0000A001
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DEFINE rs2_s11 .0000B001
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DEFINE rs2_t3 .0000C001
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DEFINE rs2_t4 .0000D001
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DEFINE rs2_t5 .0000E001
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DEFINE rs2_t6 .0000F001
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DEFINE rs1_x0 .00000000
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DEFINE rs2_x0 .00000000
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DEFINE rs2_x1 .00001000
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DEFINE rs2_x2 .00002000
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DEFINE rs2_x3 .00003000
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DEFINE rs2_x4 .00004000
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DEFINE rs2_x5 .00005000
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DEFINE rs2_x6 .00006000
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DEFINE rs2_x7 .00007000
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DEFINE rs2_x8 .00008000
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DEFINE rs2_x9 .00009000
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DEFINE rs2_x10 .0000A000
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DEFINE rs2_x11 .0000B000
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DEFINE rs2_x12 .0000C000
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DEFINE rs2_x13 .0000D000
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DEFINE rs2_x14 .0000E000
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DEFINE rs2_x15 .0000F000
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DEFINE rs2_x16 .00000001
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DEFINE rs2_x17 .00001001
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DEFINE rs2_x18 .00002001
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DEFINE rs2_x19 .00003001
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DEFINE rs2_x20 .00004001
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DEFINE rs2_x21 .00005001
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DEFINE rs2_x22 .00006001
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DEFINE rs2_x23 .00007001
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DEFINE rs2_x24 .00008001
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DEFINE rs2_x25 .00009001
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DEFINE rs2_x26 .0000A001
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DEFINE rs2_x27 .0000B001
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DEFINE rs2_x28 .0000C001
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DEFINE rs2_x29 .0000D001
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DEFINE rs2_x30 .0000E001
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DEFINE rs2_x31 .0000F001
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