This instruction is used to compare two registers and set the flags
accordingly. In current architectures this is the same as r0-r1, but for
RISCV it will be different. RISC-V does not have condition flags so
(until a better solution) we are going to emulate them there.
* module/mescc/armv4/as.scm (armv4:instructions): Add r0-cmp-r1 as alias
of r0-r1.
* module/mescc/i386/as.scm: Same.
* module/mescc/x86_64/as.scm: Same.
* module/mescc/compile.scm (expr->register): Make use of the new
r0-cmp-r1 instruction.
This inexplicably fixes a segfault in tcc-boot0.
* module/mescc/armv4/as.scm (armv4:r0/r1): Instead of using "push 0",
use explicit slot for remainder.
* lib/arm-mes/arm.M1 (mov____%esp,%r3): New macro.
* module/mescc/armv4/as.scm (armv4:r0%r1): Use it to avoid overwriting
%r0 before caling __mesabi_uldiv.
* lib/mes/div.c (__aeabi_idiv): Move for conditional compilation.
(__mesabi_idiv): New procedure.
* module/mescc/armv4/as.scm (armv4:r0/r1): Use __mesabi_idiv.
* module/mescc/armv4/as.scm (optimize-immediate): New macro.
(immediate->r0): Use it.
(armv4:value->r): Use it.
(armv4:local->r): Use it.
(armv4:r->local+n): Use it.
(armv4:r-byte-mem-add): Use it.
(armv4:r-word-mem-add): Use it.
(armv4:local-ptr->r): Use it.
(armv4:r+value): Use it.
(armv4:r-cmp-value): Use it.
(armv4:r0+value): Use it.
(armv4:byte-r->local+n): Use it.
(armv4:word-r->local+n): Use it.
* build-aux/build-guile.sh: Add ARM backend.
* lib/arm-mes/arm.M1: New file.
* module/mescc/armv4/as.scm: New file.
* module/mescc/armv4/info.scm: New file.
* module/mescc/mescc.scm: Use it.
* module/mescc/M1.scm (info->M1): Support ARM symbolic instructions,
including little endian instructions. Align functions.
